From nobody Mon May 6 20:54:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1606430113; cv=none; d=zohomail.com; s=zohoarc; b=HR2u189dry3qIh3o4wAKBJJ305lgPu9isUxtxRJidAKIoIrqAAn5tJUFWhVI/4cAl3MarU6RraHhptbvyQuCVRw9QGosEtQQ6STFJ6N/JQhNjbnSk23JaDofk5+TpiN78DTCw96Ga5326wB7yMjsVYmgufiu8Qaj0SZPFEHAdFM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606430113; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XXmNxpnSMTnR6WPItA1UjouE8wfOqsFSPYuH4JndJns=; b=K+1Po+8nJ3EV/fJr1+CjT7WqSeE8b3pjNAF73jq+5z4iB/JqPZ28U5mNAsV6JkmWH0sK/FLcB/M2YOwb88HTPxzMGwCO3axQGaXUkPpsHaRkQ40PVUnJ2Dhn1ZtRMMXd2TtxNJPzi5zJvOSg8AZNs49RNrHeu4QyVmavxB4MNFU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606430113787687.1457097940319; Thu, 26 Nov 2020 14:35:13 -0800 (PST) Received: from localhost ([::1]:60688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kiPr6-0003zS-JM for importer@patchew.org; Thu, 26 Nov 2020 17:35:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43946) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoU-0001NR-99 for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:31 -0500 Received: from mx2.suse.de ([195.135.220.15]:44294) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoP-0003Ek-P8 for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:30 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 89CFEAE42; Thu, 26 Nov 2020 22:32:23 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC v6 01/11] i386: move kvm accel files into kvm/ Date: Thu, 26 Nov 2020 23:32:08 +0100 Message-Id: <20201126223218.31480-2-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201126223218.31480-1-cfontana@suse.de> References: <20201126223218.31480-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana --- MAINTAINERS | 2 +- hw/i386/fw_cfg.c | 2 +- hw/i386/intel_iommu.c | 2 +- hw/i386/kvm/apic.c | 2 +- hw/i386/kvm/clock.c | 2 +- hw/i386/microvm.c | 2 +- hw/i386/pc.c | 2 +- hw/i386/x86.c | 2 +- meson.build | 1 + target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 +- target/i386/helper.c | 2 +- target/i386/{ =3D> kvm}/hyperv-proto.h | 0 target/i386/{ =3D> kvm}/hyperv-stub.c | 0 target/i386/{ =3D> kvm}/hyperv.c | 0 target/i386/{ =3D> kvm}/hyperv.h | 0 target/i386/{ =3D> kvm}/kvm-stub.c | 0 target/i386/{ =3D> kvm}/kvm.c | 0 target/i386/{ =3D> kvm}/kvm_i386.h | 0 target/i386/kvm/meson.build | 3 +++ target/i386/kvm/trace-events | 7 +++++++ target/i386/kvm/trace.h | 1 + target/i386/machine.c | 4 ++-- target/i386/meson.build | 4 +--- target/i386/trace-events | 6 ------ 25 files changed, 26 insertions(+), 22 deletions(-) rename target/i386/{ =3D> kvm}/hyperv-proto.h (100%) rename target/i386/{ =3D> kvm}/hyperv-stub.c (100%) rename target/i386/{ =3D> kvm}/hyperv.c (100%) rename target/i386/{ =3D> kvm}/hyperv.h (100%) rename target/i386/{ =3D> kvm}/kvm-stub.c (100%) rename target/i386/{ =3D> kvm}/kvm.c (100%) rename target/i386/{ =3D> kvm}/kvm_i386.h (100%) create mode 100644 target/i386/kvm/meson.build create mode 100644 target/i386/kvm/trace-events create mode 100644 target/i386/kvm/trace.h diff --git a/MAINTAINERS b/MAINTAINERS index 2e018a0c1d..6a77faccf6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -424,7 +424,7 @@ M: Paolo Bonzini M: Marcelo Tosatti L: kvm@vger.kernel.org S: Supported -F: target/i386/kvm.c +F: target/i386/kvm/ F: scripts/kvm/vmxcap =20 Guest CPU Cores (other accelerators) diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index e06579490c..fae1bb380f 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -21,7 +21,7 @@ #include "hw/timer/hpet.h" #include "hw/nvram/fw_cfg.h" #include "e820_memory_layout.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include CONFIG_DEVICES =20 struct hpet_fw_config hpet_cfg =3D {.count =3D UINT8_MAX}; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 70ac837733..361b6cd238 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -37,7 +37,7 @@ #include "sysemu/kvm.h" #include "sysemu/sysemu.h" #include "hw/i386/apic_internal.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "trace.h" =20 diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c index dd29906061..07bebc1282 100644 --- a/hw/i386/kvm/apic.c +++ b/hw/i386/kvm/apic.c @@ -17,7 +17,7 @@ #include "hw/pci/msi.h" #include "sysemu/hw_accel.h" #include "sysemu/kvm.h" -#include "target/i386/kvm_i386.h" +#include "kvm/kvm_i386.h" =20 static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic, int reg_id, uint32_t val) diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index 24fe5091b6..2d8a366369 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -20,7 +20,7 @@ #include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "sysemu/hw_accel.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "hw/sysbus.h" #include "hw/kvm/clock.h" diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 5428448b70..3ed6adff83 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -51,7 +51,7 @@ =20 #include "cpu.h" #include "elf.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "hw/xen/start_info.h" =20 #define MICROVM_QBOOT_FILENAME "qboot.rom" diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 17b514d1da..299aaba8e9 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -61,7 +61,7 @@ #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "hw/xen/xen.h" #include "hw/xen/start_info.h" #include "ui/qemu-spice.h" diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 5944fc44ed..88d0c70e12 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -52,7 +52,7 @@ #include "elf.h" #include "standard-headers/asm-x86/bootparam.h" #include CONFIG_DEVICES -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" =20 #define BIOS_FILENAME "bios.bin" =20 diff --git a/meson.build b/meson.build index 5062407c70..d6158172b0 100644 --- a/meson.build +++ b/meson.build @@ -1468,6 +1468,7 @@ trace_events_subdirs +=3D [ 'target/arm', 'target/hppa', 'target/i386', + 'target/i386/kvm', 'target/mips', 'target/ppc', 'target/riscv', diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5a8c96072e..b9bd249c8f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -30,7 +30,7 @@ #include "sysemu/hvf.h" #include "sysemu/cpus.h" #include "sysemu/xen.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "sev_i386.h" =20 #include "qemu/error-report.h" diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 88e8586f8f..9ecda75aec 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -22,7 +22,7 @@ =20 #include "sysemu/tcg.h" #include "cpu-qom.h" -#include "hyperv-proto.h" +#include "kvm/hyperv-proto.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" =20 diff --git a/target/i386/helper.c b/target/i386/helper.c index 034f46bcc2..a1b3367ab2 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -24,7 +24,7 @@ #include "qemu/qemu-print.h" #include "sysemu/kvm.h" #include "sysemu/runstate.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY #include "sysemu/tcg.h" #include "sysemu/hw_accel.h" diff --git a/target/i386/hyperv-proto.h b/target/i386/kvm/hyperv-proto.h similarity index 100% rename from target/i386/hyperv-proto.h rename to target/i386/kvm/hyperv-proto.h diff --git a/target/i386/hyperv-stub.c b/target/i386/kvm/hyperv-stub.c similarity index 100% rename from target/i386/hyperv-stub.c rename to target/i386/kvm/hyperv-stub.c diff --git a/target/i386/hyperv.c b/target/i386/kvm/hyperv.c similarity index 100% rename from target/i386/hyperv.c rename to target/i386/kvm/hyperv.c diff --git a/target/i386/hyperv.h b/target/i386/kvm/hyperv.h similarity index 100% rename from target/i386/hyperv.h rename to target/i386/kvm/hyperv.h diff --git a/target/i386/kvm-stub.c b/target/i386/kvm/kvm-stub.c similarity index 100% rename from target/i386/kvm-stub.c rename to target/i386/kvm/kvm-stub.c diff --git a/target/i386/kvm.c b/target/i386/kvm/kvm.c similarity index 100% rename from target/i386/kvm.c rename to target/i386/kvm/kvm.c diff --git a/target/i386/kvm_i386.h b/target/i386/kvm/kvm_i386.h similarity index 100% rename from target/i386/kvm_i386.h rename to target/i386/kvm/kvm_i386.h diff --git a/target/i386/kvm/meson.build b/target/i386/kvm/meson.build new file mode 100644 index 0000000000..1d66559187 --- /dev/null +++ b/target/i386/kvm/meson.build @@ -0,0 +1,3 @@ +i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) +i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) +i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_= false: files('hyperv-stub.c')) diff --git a/target/i386/kvm/trace-events b/target/i386/kvm/trace-events new file mode 100644 index 0000000000..b4e2d9e4ea --- /dev/null +++ b/target/i386/kvm/trace-events @@ -0,0 +1,7 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# kvm.c +kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for = GSI %" PRIu32 +kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d" +kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d" +kvm_x86_update_msi_routes(int num) "Updated %d MSI routes" diff --git a/target/i386/kvm/trace.h b/target/i386/kvm/trace.h new file mode 100644 index 0000000000..46b75c6942 --- /dev/null +++ b/target/i386/kvm/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_i386_kvm.h" diff --git a/target/i386/machine.c b/target/i386/machine.c index 233e46bb70..1614e8c2f8 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -3,9 +3,9 @@ #include "exec/exec-all.h" #include "hw/isa/isa.h" #include "migration/cpu.h" -#include "hyperv.h" +#include "kvm/hyperv.h" #include "hw/i386/x86.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" =20 #include "sysemu/kvm.h" #include "sysemu/tcg.h" diff --git a/target/i386/meson.build b/target/i386/meson.build index a1a02f3e99..0209542a8a 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -18,7 +18,6 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files( 'smm_helper.c', 'svm_helper.c', 'translate.c'), if_false: files('tcg-stub.c')) -i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) =20 i386_softmmu_ss =3D ss.source_set() @@ -28,8 +27,6 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_= false: files('hyperv-stub.c')) -i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( 'whpx-all.c', 'whpx-cpus.c', @@ -42,6 +39,7 @@ i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('= hax-posix.c')) i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) =20 +subdir('kvm') subdir('hvf') =20 target_arch +=3D {'i386': i386_ss} diff --git a/target/i386/trace-events b/target/i386/trace-events index 789c700d4a..d166f9d5e0 100644 --- a/target/i386/trace-events +++ b/target/i386/trace-events @@ -1,11 +1,5 @@ # See docs/devel/tracing.txt for syntax documentation. =20 -# kvm.c -kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for = GSI %" PRIu32 -kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d" -kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d" -kvm_x86_update_msi_routes(int num) "Updated %d MSI routes" - # sev.c kvm_sev_init(void) "" kvm_memcrypt_register_region(void *addr, size_t len) "addr %p len 0x%zu" --=20 2.26.2 From nobody Mon May 6 20:54:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1606430083; cv=none; d=zohomail.com; s=zohoarc; b=Qb8OfuZklzP+NCMbWnQng+26OMU7p+0opLXHmJFB52oJPDPrHcqTIjnnEe9qotCBwKnlNeK5UtIMUFx4hMOpZ6DIvFkxjx311XwWnjU/2iX2ukkHGzPC6JpY40fXI9zihAuRnIHDfBt1sLQcbzM/ZclouWmWy4eofcXazNtE8Wc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606430083; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Gx7EbMKfiVMOUpOP+z/sYS5+4NG2eBvuvB7LNskBiCk=; b=dy56PfYiL4JaAOI0V1fQTEGuH4NuZT3YGvuXnI1N5jP2vccId+3/BDUUs50NU7gHyLpU7Ty6cWq0SJ99P7anAqcld3FW578mVUwg1G73fGz5T8RoT+rSmV5CNphWVQKW60DlVbWAWjZCSkGXYclZaB47xmOxqLH/MuKtyNdzKj4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606430083399678.1426754245997; Thu, 26 Nov 2020 14:34:43 -0800 (PST) Received: from localhost ([::1]:58500 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kiPqc-00037J-Af for importer@patchew.org; Thu, 26 Nov 2020 17:34:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoX-0001Q3-5o for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:33 -0500 Received: from mx2.suse.de ([195.135.220.15]:44340) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoP-0003Eu-Sj for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:32 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 6BD51AE35; Thu, 26 Nov 2020 22:32:24 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC v6 02/11] i386: move whpx accel files into whpx/ Date: Thu, 26 Nov 2020 23:32:09 +0100 Message-Id: <20201126223218.31480-3-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201126223218.31480-1-cfontana@suse.de> References: <20201126223218.31480-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana --- MAINTAINERS | 5 +---- target/i386/meson.build | 5 +---- target/i386/whpx/meson.build | 4 ++++ target/i386/{ =3D> whpx}/whp-dispatch.h | 0 target/i386/{ =3D> whpx}/whpx-all.c | 0 target/i386/{ =3D> whpx}/whpx-cpus.c | 0 target/i386/{ =3D> whpx}/whpx-cpus.h | 0 7 files changed, 6 insertions(+), 8 deletions(-) create mode 100644 target/i386/whpx/meson.build rename target/i386/{ =3D> whpx}/whp-dispatch.h (100%) rename target/i386/{ =3D> whpx}/whpx-all.c (100%) rename target/i386/{ =3D> whpx}/whpx-cpus.c (100%) rename target/i386/{ =3D> whpx}/whpx-cpus.h (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 6a77faccf6..02bc29ea2b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -450,10 +450,7 @@ F: include/sysemu/hvf.h WHPX CPUs M: Sunil Muthuswamy S: Supported -F: target/i386/whpx-all.c -F: target/i386/whpx-cpus.c -F: target/i386/whp-dispatch.h -F: accel/stubs/whpx-stub.c +F: target/i386/whpx/ F: include/sysemu/whpx.h =20 Guest CPU Cores (Xen) diff --git a/target/i386/meson.build b/target/i386/meson.build index 0209542a8a..62cd042915 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -27,10 +27,6 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( - 'whpx-all.c', - 'whpx-cpus.c', -)) i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( 'hax-all.c', 'hax-mem.c', @@ -40,6 +36,7 @@ i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'],= if_true: files('hax-po i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) =20 subdir('kvm') +subdir('whpx') subdir('hvf') =20 target_arch +=3D {'i386': i386_ss} diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build new file mode 100644 index 0000000000..94a72c8efc --- /dev/null +++ b/target/i386/whpx/meson.build @@ -0,0 +1,4 @@ +i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( + 'whpx-all.c', + 'whpx-cpus.c', +)) diff --git a/target/i386/whp-dispatch.h b/target/i386/whpx/whp-dispatch.h similarity index 100% rename from target/i386/whp-dispatch.h rename to target/i386/whpx/whp-dispatch.h diff --git a/target/i386/whpx-all.c b/target/i386/whpx/whpx-all.c similarity index 100% rename from target/i386/whpx-all.c rename to target/i386/whpx/whpx-all.c diff --git a/target/i386/whpx-cpus.c b/target/i386/whpx/whpx-cpus.c similarity index 100% rename from target/i386/whpx-cpus.c rename to target/i386/whpx/whpx-cpus.c diff --git a/target/i386/whpx-cpus.h b/target/i386/whpx/whpx-cpus.h similarity index 100% rename from target/i386/whpx-cpus.h rename to target/i386/whpx/whpx-cpus.h --=20 2.26.2 From nobody Mon May 6 20:54:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1606430411; cv=none; d=zohomail.com; s=zohoarc; b=nMnO5IBObkpCzEHTO7nbk8l12Q9nz6pkk66By0KEVuKAebQAI05Bo3SnjpdVN+kyYrHnfBbvmvpJMcw6a4yI/5VeDsPuVdjJXeO6/Yt/Zusz0aqtT3N4+l11Mz0pFKS+lvLsKEWP6JdRUFNac6S0t+D5Yyvd9IqCCRuCD+zh6WU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606430411; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1LmPWDoSQIff5HYcKvm5OtKPHaBOZusM2iiuor3L29s=; b=cY4+a1NkPN5cmfF+kID8QKc46fcIkdSpGG+2UjHugFd/0eXWqWF+Thcryk5HawEXPPfC7auKw2Gt5+BGyXbxLcDKJ4eyUMMTb0pcp00vf+RdzCiIHk0HDmUZeww1l+AdxkdduS29o3kj7cx9aAHe2WhSq9kYUae3qrj4QBwIkQE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606430411766787.8622140926581; Thu, 26 Nov 2020 14:40:11 -0800 (PST) Received: from localhost ([::1]:47092 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kiPvu-0001gE-O5 for importer@patchew.org; Thu, 26 Nov 2020 17:40:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoX-0001QS-BS for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:33 -0500 Received: from mx2.suse.de ([195.135.220.15]:44370) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoQ-0003F3-JS for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:33 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 57401AE47; Thu, 26 Nov 2020 22:32:25 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC v6 03/11] i386: move hax accel files into hax/ Date: Thu, 26 Nov 2020 23:32:10 +0100 Message-Id: <20201126223218.31480-4-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201126223218.31480-1-cfontana@suse.de> References: <20201126223218.31480-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana --- MAINTAINERS | 2 +- target/i386/{ =3D> hax}/hax-all.c | 0 target/i386/{ =3D> hax}/hax-cpus.c | 0 target/i386/{ =3D> hax}/hax-cpus.h | 0 target/i386/{ =3D> hax}/hax-i386.h | 6 +++--- target/i386/{ =3D> hax}/hax-interface.h | 0 target/i386/{ =3D> hax}/hax-mem.c | 0 target/i386/{ =3D> hax}/hax-posix.c | 0 target/i386/{ =3D> hax}/hax-posix.h | 0 target/i386/{ =3D> hax}/hax-windows.c | 0 target/i386/{ =3D> hax}/hax-windows.h | 0 target/i386/hax/meson.build | 7 +++++++ target/i386/meson.build | 8 +------- 13 files changed, 12 insertions(+), 11 deletions(-) rename target/i386/{ =3D> hax}/hax-all.c (100%) rename target/i386/{ =3D> hax}/hax-cpus.c (100%) rename target/i386/{ =3D> hax}/hax-cpus.h (100%) rename target/i386/{ =3D> hax}/hax-i386.h (95%) rename target/i386/{ =3D> hax}/hax-interface.h (100%) rename target/i386/{ =3D> hax}/hax-mem.c (100%) rename target/i386/{ =3D> hax}/hax-posix.c (100%) rename target/i386/{ =3D> hax}/hax-posix.h (100%) rename target/i386/{ =3D> hax}/hax-windows.c (100%) rename target/i386/{ =3D> hax}/hax-windows.h (100%) create mode 100644 target/i386/hax/meson.build diff --git a/MAINTAINERS b/MAINTAINERS index 02bc29ea2b..463317784c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -490,7 +490,7 @@ W: https://github.com/intel/haxm/issues S: Maintained F: accel/stubs/hax-stub.c F: include/sysemu/hax.h -F: target/i386/hax-* +F: target/i386/hax/ =20 Hosts ----- diff --git a/target/i386/hax-all.c b/target/i386/hax/hax-all.c similarity index 100% rename from target/i386/hax-all.c rename to target/i386/hax/hax-all.c diff --git a/target/i386/hax-cpus.c b/target/i386/hax/hax-cpus.c similarity index 100% rename from target/i386/hax-cpus.c rename to target/i386/hax/hax-cpus.c diff --git a/target/i386/hax-cpus.h b/target/i386/hax/hax-cpus.h similarity index 100% rename from target/i386/hax-cpus.h rename to target/i386/hax/hax-cpus.h diff --git a/target/i386/hax-i386.h b/target/i386/hax/hax-i386.h similarity index 95% rename from target/i386/hax-i386.h rename to target/i386/hax/hax-i386.h index 48c4abe14e..efbb346238 100644 --- a/target/i386/hax-i386.h +++ b/target/i386/hax/hax-i386.h @@ -84,13 +84,13 @@ void hax_memory_init(void); =20 =20 #ifdef CONFIG_POSIX -#include "target/i386/hax-posix.h" +#include "hax-posix.h" #endif =20 #ifdef CONFIG_WIN32 -#include "target/i386/hax-windows.h" +#include "hax-windows.h" #endif =20 -#include "target/i386/hax-interface.h" +#include "hax-interface.h" =20 #endif diff --git a/target/i386/hax-interface.h b/target/i386/hax/hax-interface.h similarity index 100% rename from target/i386/hax-interface.h rename to target/i386/hax/hax-interface.h diff --git a/target/i386/hax-mem.c b/target/i386/hax/hax-mem.c similarity index 100% rename from target/i386/hax-mem.c rename to target/i386/hax/hax-mem.c diff --git a/target/i386/hax-posix.c b/target/i386/hax/hax-posix.c similarity index 100% rename from target/i386/hax-posix.c rename to target/i386/hax/hax-posix.c diff --git a/target/i386/hax-posix.h b/target/i386/hax/hax-posix.h similarity index 100% rename from target/i386/hax-posix.h rename to target/i386/hax/hax-posix.h diff --git a/target/i386/hax-windows.c b/target/i386/hax/hax-windows.c similarity index 100% rename from target/i386/hax-windows.c rename to target/i386/hax/hax-windows.c diff --git a/target/i386/hax-windows.h b/target/i386/hax/hax-windows.h similarity index 100% rename from target/i386/hax-windows.h rename to target/i386/hax/hax-windows.h diff --git a/target/i386/hax/meson.build b/target/i386/hax/meson.build new file mode 100644 index 0000000000..77ea431b30 --- /dev/null +++ b/target/i386/hax/meson.build @@ -0,0 +1,7 @@ +i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( + 'hax-all.c', + 'hax-mem.c', + 'hax-cpus.c', +)) +i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('= hax-posix.c')) +i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) diff --git a/target/i386/meson.build b/target/i386/meson.build index 62cd042915..284d52ab81 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -27,15 +27,9 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( - 'hax-all.c', - 'hax-mem.c', - 'hax-cpus.c', -)) -i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('= hax-posix.c')) -i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) =20 subdir('kvm') +subdir('hax') subdir('whpx') subdir('hvf') =20 --=20 2.26.2 From nobody Mon May 6 20:54:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1606430510; cv=none; d=zohomail.com; s=zohoarc; b=gqch1wzc821x9KDKfIZ4Bjrl9Yeh3X7wavHbAwLK+kHah42GLhDOTKyzcp4wJvw8QD+QbXpsc8AOq0TXySGfq8U+mVsccd05SQaYVGcbTbaD5JNwtWqWTYOsXEpBz7FIBoT4ElUdw3vrh4rDV96CyxKlZYmTI0SDrjM+C6t4P8E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606430510; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uNW6O4dwzJMzdq14bjMLk0maLdtShV8fqAMD48eJTtk=; b=XXLrdSC9/dU6yKiy1y8kBQQiGX/vjQZLl8oStZukof8Ao0Z5eVhn1DDqo56HkLB958iMYMjqNXuswHgkpJW6DC0uCq60lNBKwvemkrEteqk7cY7hXTBeVlPG6hRRKOzpuUKINXUfHI/mUU+K7QU2qRy7IpWbGB4FRfz8XfYXIqQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606430510539539.7442056550227; Thu, 26 Nov 2020 14:41:50 -0800 (PST) Received: from localhost ([::1]:51376 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kiPxV-0003XZ-Do for importer@patchew.org; Thu, 26 Nov 2020 17:41:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44000) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoX-0001RJ-Tj for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:33 -0500 Received: from mx2.suse.de ([195.135.220.15]:44404) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoR-0003Fu-DQ for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:33 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 3407BAE59; Thu, 26 Nov 2020 22:32:26 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC v6 04/11] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs Date: Thu, 26 Nov 2020 23:32:11 +0100 Message-Id: <20201126223218.31480-5-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201126223218.31480-1-cfontana@suse.de> References: <20201126223218.31480-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana Reviewed-by: Roman Bolshakov --- MAINTAINERS | 1 - 1 file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 463317784c..e892dd2220 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -443,7 +443,6 @@ M: Cameron Esfahani M: Roman Bolshakov W: https://wiki.qemu.org/Features/HVF S: Maintained -F: accel/stubs/hvf-stub.c F: target/i386/hvf/ F: include/sysemu/hvf.h =20 --=20 2.26.2 From nobody Mon May 6 20:54:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1606430204; cv=none; d=zohomail.com; s=zohoarc; b=Zlv1cCcz6kI8so8i4A1FN4nbxOr1azPXntCLW6pAPcMdJq3l+LLhH1KyyRhX3CloJ5XgF/IHDDicNYxXmx8iYZosfI55nOusHXueFBkCdH9qm+3qAp9EqSccIbKeE7dx1tTza1OrwA6yfOgH9W/ZXLARUf42VnAWtcfncazurFs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606430204; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=H3di1s8TJrXAoLzBQvrJEzP7HlAhNFC20zzTrddvsQk=; b=W7r3uejB6HlhRgwX4jQWHSjInZrKSJ9kCqSUMpegIREm43HtAOn6GtdSxi9yv1HwjFMCEvX2lgvqzgYCuxxM5g+/FFyN6Q6/lmMkuB9179dXUIvrHJSlITHGhzWFnhWBsMnXxeYWFgEOcBQ0XzAB2381vzh1YlvisHNvkcEQUAg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606430204671149.41719254590873; Thu, 26 Nov 2020 14:36:44 -0800 (PST) Received: from localhost ([::1]:38942 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kiPsZ-0006i9-Eb for importer@patchew.org; Thu, 26 Nov 2020 17:36:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44014) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoY-0001S3-Fs for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:38 -0500 Received: from mx2.suse.de ([195.135.220.15]:44566) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoV-0003HF-GK for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:34 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 1590AAF10; Thu, 26 Nov 2020 22:32:27 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC v6 05/11] i386: move TCG accel files into tcg/ Date: Thu, 26 Nov 2020 23:32:12 +0100 Message-Id: <20201126223218.31480-6-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201126223218.31480-1-cfontana@suse.de> References: <20201126223218.31480-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana --- target/i386/meson.build | 14 +------------- target/i386/{ =3D> tcg}/bpt_helper.c | 0 target/i386/{ =3D> tcg}/cc_helper.c | 0 target/i386/{ =3D> tcg}/excp_helper.c | 0 target/i386/{ =3D> tcg}/fpu_helper.c | 0 target/i386/{ =3D> tcg}/int_helper.c | 0 target/i386/{ =3D> tcg}/mem_helper.c | 0 target/i386/tcg/meson.build | 13 +++++++++++++ target/i386/{ =3D> tcg}/misc_helper.c | 0 target/i386/{ =3D> tcg}/mpx_helper.c | 0 target/i386/{ =3D> tcg}/seg_helper.c | 0 target/i386/{ =3D> tcg}/smm_helper.c | 0 target/i386/{ =3D> tcg}/svm_helper.c | 0 target/i386/{ =3D> tcg}/tcg-stub.c | 0 target/i386/{ =3D> tcg}/translate.c | 0 15 files changed, 14 insertions(+), 13 deletions(-) rename target/i386/{ =3D> tcg}/bpt_helper.c (100%) rename target/i386/{ =3D> tcg}/cc_helper.c (100%) rename target/i386/{ =3D> tcg}/excp_helper.c (100%) rename target/i386/{ =3D> tcg}/fpu_helper.c (100%) rename target/i386/{ =3D> tcg}/int_helper.c (100%) rename target/i386/{ =3D> tcg}/mem_helper.c (100%) create mode 100644 target/i386/tcg/meson.build rename target/i386/{ =3D> tcg}/misc_helper.c (100%) rename target/i386/{ =3D> tcg}/mpx_helper.c (100%) rename target/i386/{ =3D> tcg}/seg_helper.c (100%) rename target/i386/{ =3D> tcg}/smm_helper.c (100%) rename target/i386/{ =3D> tcg}/svm_helper.c (100%) rename target/i386/{ =3D> tcg}/tcg-stub.c (100%) rename target/i386/{ =3D> tcg}/translate.c (100%) diff --git a/target/i386/meson.build b/target/i386/meson.build index 284d52ab81..750471c9f3 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -5,19 +5,6 @@ i386_ss.add(files( 'helper.c', 'xsave_helper.c', )) -i386_ss.add(when: 'CONFIG_TCG', if_true: files( - 'bpt_helper.c', - 'cc_helper.c', - 'excp_helper.c', - 'fpu_helper.c', - 'int_helper.c', - 'mem_helper.c', - 'misc_helper.c', - 'mpx_helper.c', - 'seg_helper.c', - 'smm_helper.c', - 'svm_helper.c', - 'translate.c'), if_false: files('tcg-stub.c')) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) =20 i386_softmmu_ss =3D ss.source_set() @@ -32,6 +19,7 @@ subdir('kvm') subdir('hax') subdir('whpx') subdir('hvf') +subdir('tcg') =20 target_arch +=3D {'i386': i386_ss} target_softmmu_arch +=3D {'i386': i386_softmmu_ss} diff --git a/target/i386/bpt_helper.c b/target/i386/tcg/bpt_helper.c similarity index 100% rename from target/i386/bpt_helper.c rename to target/i386/tcg/bpt_helper.c diff --git a/target/i386/cc_helper.c b/target/i386/tcg/cc_helper.c similarity index 100% rename from target/i386/cc_helper.c rename to target/i386/tcg/cc_helper.c diff --git a/target/i386/excp_helper.c b/target/i386/tcg/excp_helper.c similarity index 100% rename from target/i386/excp_helper.c rename to target/i386/tcg/excp_helper.c diff --git a/target/i386/fpu_helper.c b/target/i386/tcg/fpu_helper.c similarity index 100% rename from target/i386/fpu_helper.c rename to target/i386/tcg/fpu_helper.c diff --git a/target/i386/int_helper.c b/target/i386/tcg/int_helper.c similarity index 100% rename from target/i386/int_helper.c rename to target/i386/tcg/int_helper.c diff --git a/target/i386/mem_helper.c b/target/i386/tcg/mem_helper.c similarity index 100% rename from target/i386/mem_helper.c rename to target/i386/tcg/mem_helper.c diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build new file mode 100644 index 0000000000..02794226c2 --- /dev/null +++ b/target/i386/tcg/meson.build @@ -0,0 +1,13 @@ +i386_ss.add(when: 'CONFIG_TCG', if_true: files( + 'bpt_helper.c', + 'cc_helper.c', + 'excp_helper.c', + 'fpu_helper.c', + 'int_helper.c', + 'mem_helper.c', + 'misc_helper.c', + 'mpx_helper.c', + 'seg_helper.c', + 'smm_helper.c', + 'svm_helper.c', + 'translate.c'), if_false: files('tcg-stub.c')) diff --git a/target/i386/misc_helper.c b/target/i386/tcg/misc_helper.c similarity index 100% rename from target/i386/misc_helper.c rename to target/i386/tcg/misc_helper.c diff --git a/target/i386/mpx_helper.c b/target/i386/tcg/mpx_helper.c similarity index 100% rename from target/i386/mpx_helper.c rename to target/i386/tcg/mpx_helper.c diff --git a/target/i386/seg_helper.c b/target/i386/tcg/seg_helper.c similarity index 100% rename from target/i386/seg_helper.c rename to target/i386/tcg/seg_helper.c diff --git a/target/i386/smm_helper.c b/target/i386/tcg/smm_helper.c similarity index 100% rename from target/i386/smm_helper.c rename to target/i386/tcg/smm_helper.c diff --git a/target/i386/svm_helper.c b/target/i386/tcg/svm_helper.c similarity index 100% rename from target/i386/svm_helper.c rename to target/i386/tcg/svm_helper.c diff --git a/target/i386/tcg-stub.c b/target/i386/tcg/tcg-stub.c similarity index 100% rename from target/i386/tcg-stub.c rename to target/i386/tcg/tcg-stub.c diff --git a/target/i386/translate.c b/target/i386/tcg/translate.c similarity index 100% rename from target/i386/translate.c rename to target/i386/tcg/translate.c --=20 2.26.2 From nobody Mon May 6 20:54:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1606430203; cv=none; d=zohomail.com; s=zohoarc; b=XhVhkum7EgIT6Xlc53kYzFHX9i58uOe4jNiuwGIxVAlprj0vvUtDZU7DzvkVyhGyjutIrD+HfejPCyxnjDuQ1fQjXHM7F2ITTxIrZCr3D2/Ewo3NvUSw6G5qefl+ztSKOe8dCj747uBfycxAY//dJO/HAzw1O/WFrJZ9vyGiCKU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606430203; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vff1vd+5df4BwDlLGuYvmlL/QHCGTA4hs3JAPCEKGCY=; b=IbIXNwjbrbsmPOu/6FOysDMgOIHiEoeXTeRTzq2XHpYi1yKU2u4kC7Ttiur9KYqwRUv0DJ2JLv0CtVZTOLv88coGrQ1T7rEMw4OFi/CLDmJc0XayCVEXteL/OJsNzi9DEZetSYsmUhnkjPtFJaylJ7/GpwLbrduI5S75j2pXMWM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606430203732183.58806118350412; Thu, 26 Nov 2020 14:36:43 -0800 (PST) Received: from localhost ([::1]:38720 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kiPsY-0006cq-Bv for importer@patchew.org; Thu, 26 Nov 2020 17:36:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44072) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPod-0001Ut-Ii for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:39 -0500 Received: from mx2.suse.de ([195.135.220.15]:44568) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoV-0003HE-Gm for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:39 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id F2474AF3D; Thu, 26 Nov 2020 22:32:27 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC v6 06/11] i386: move cpu dump out of helper.c into cpu-dump.c Date: Thu, 26 Nov 2020 23:32:13 +0100 Message-Id: <20201126223218.31480-7-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201126223218.31480-1-cfontana@suse.de> References: <20201126223218.31480-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana --- target/i386/cpu-dump.c | 538 ++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 1 + target/i386/helper.c | 514 -------------------------------------- target/i386/meson.build | 1 + 4 files changed, 540 insertions(+), 514 deletions(-) create mode 100644 target/i386/cpu-dump.c diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c new file mode 100644 index 0000000000..1ddc47fb0c --- /dev/null +++ b/target/i386/cpu-dump.c @@ -0,0 +1,538 @@ +/* + * i386 CPU dump to FILE + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "qemu/qemu-print.h" +#ifndef CONFIG_USER_ONLY +#include "hw/i386/apic_internal.h" +#endif + +/***********************************************************/ +/* x86 debug */ + +static const char *cc_op_str[CC_OP_NB] =3D { + "DYNAMIC", + "EFLAGS", + + "MULB", + "MULW", + "MULL", + "MULQ", + + "ADDB", + "ADDW", + "ADDL", + "ADDQ", + + "ADCB", + "ADCW", + "ADCL", + "ADCQ", + + "SUBB", + "SUBW", + "SUBL", + "SUBQ", + + "SBBB", + "SBBW", + "SBBL", + "SBBQ", + + "LOGICB", + "LOGICW", + "LOGICL", + "LOGICQ", + + "INCB", + "INCW", + "INCL", + "INCQ", + + "DECB", + "DECW", + "DECL", + "DECQ", + + "SHLB", + "SHLW", + "SHLL", + "SHLQ", + + "SARB", + "SARW", + "SARL", + "SARQ", + + "BMILGB", + "BMILGW", + "BMILGL", + "BMILGQ", + + "ADCX", + "ADOX", + "ADCOX", + + "CLR", +}; + +static void +cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, + const char *name, struct SegmentCache *sc) +{ +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "%-3s=3D%04x %016" PRIx64 " %08x %08x", name, + sc->selector, sc->base, sc->limit, + sc->flags & 0x00ffff00); + } else +#endif + { + qemu_fprintf(f, "%-3s=3D%04x %08x %08x %08x", name, sc->selector, + (uint32_t)sc->base, sc->limit, + sc->flags & 0x00ffff00); + } + + if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK)) + goto done; + + qemu_fprintf(f, " DPL=3D%d ", + (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT); + if (sc->flags & DESC_S_MASK) { + if (sc->flags & DESC_CS_MASK) { + qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" : + ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16")); + qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-= ', + (sc->flags & DESC_R_MASK) ? 'R' : '-'); + } else { + qemu_fprintf(f, (sc->flags & DESC_B_MASK + || env->hflags & HF_LMA_MASK) + ? "DS " : "DS16"); + qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-= ', + (sc->flags & DESC_W_MASK) ? 'W' : '-'); + } + qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-'); + } else { + static const char *sys_type_name[2][16] =3D { + { /* 32 bit mode */ + "Reserved", "TSS16-avl", "LDT", "TSS16-busy", + "CallGate16", "TaskGate", "IntGate16", "TrapGate16", + "Reserved", "TSS32-avl", "Reserved", "TSS32-busy", + "CallGate32", "Reserved", "IntGate32", "TrapGate32" + }, + { /* 64 bit mode */ + "", "Reserved", "LDT", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved", + "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64", + "Reserved", "IntGate64", "TrapGate64" + } + }; + qemu_fprintf(f, "%s", + sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0] + [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]); + } +done: + qemu_fprintf(f, "\n"); +} + +#ifndef CONFIG_USER_ONLY + +/* ARRAY_SIZE check is not required because + * DeliveryMode(dm) has a size of 3 bit. + */ +static inline const char *dm2str(uint32_t dm) +{ + static const char *str[] =3D { + "Fixed", + "...", + "SMI", + "...", + "NMI", + "INIT", + "...", + "ExtINT" + }; + return str[dm]; +} + +static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer) +{ + uint32_t dm =3D (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT; + qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s", + name, lvt, + lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi", + lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge", + lvt & APIC_LVT_MASKED ? "masked" : "", + lvt & APIC_LVT_DELIV_STS ? "pending" : "", + !is_timer ? + "" : lvt & APIC_LVT_TIMER_PERIODIC ? + "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ? + "tsc-deadline" : "one-shot", + dm2str(dm)); + if (dm !=3D APIC_DM_NMI) { + qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK); + } else { + qemu_printf("\n"); + } +} + +/* ARRAY_SIZE check is not required because + * destination shorthand has a size of 2 bit. + */ +static inline const char *shorthand2str(uint32_t shorthand) +{ + const char *str[] =3D { + "no-shorthand", "self", "all-self", "all" + }; + return str[shorthand]; +} + +static inline uint8_t divider_conf(uint32_t divide_conf) +{ + uint8_t divide_val =3D ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3= ); + + return divide_val =3D=3D 7 ? 1 : 2 << divide_val; +} + +static inline void mask2str(char *str, uint32_t val, uint8_t size) +{ + while (size--) { + *str++ =3D (val >> size) & 1 ? '1' : '0'; + } + *str =3D 0; +} + +#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16 + +static void dump_apic_icr(APICCommonState *s, CPUX86State *env) +{ + uint32_t icr =3D s->icr[0], icr2 =3D s->icr[1]; + uint8_t dest_shorthand =3D \ + (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT; + bool logical_mod =3D icr & APIC_ICR_DEST_MOD; + char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1]; + uint32_t dest_field; + bool x2apic; + + qemu_printf("ICR\t 0x%08x %s %s %s %s\n", + icr, + logical_mod ? "logical" : "physical", + icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge", + icr & APIC_ICR_LEVEL ? "assert" : "de-assert", + shorthand2str(dest_shorthand)); + + qemu_printf("ICR2\t 0x%08x", icr2); + if (dest_shorthand !=3D 0) { + qemu_printf("\n"); + return; + } + x2apic =3D env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC; + dest_field =3D x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT; + + if (!logical_mod) { + if (x2apic) { + qemu_printf(" cpu %u (X2APIC ID)\n", dest_field); + } else { + qemu_printf(" cpu %u (APIC ID)\n", + dest_field & APIC_LOGDEST_XAPIC_ID); + } + return; + } + + if (s->dest_mode =3D=3D 0xf) { /* flat mode */ + mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8); + qemu_printf(" mask %s (APIC ID)\n", apic_id_str); + } else if (s->dest_mode =3D=3D 0) { /* cluster mode */ + if (x2apic) { + mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16); + qemu_printf(" cluster %u mask %s (X2APIC ID)\n", + dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_s= tr); + } else { + mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4); + qemu_printf(" cluster %u mask %s (APIC ID)\n", + dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_st= r); + } + } +} + +static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab, + uint32_t *tmr_tab) +{ + int i, empty =3D true; + + qemu_printf("%s\t ", name); + for (i =3D 0; i < 256; i++) { + if (apic_get_bit(ireg_tab, i)) { + qemu_printf("%u%s ", i, + apic_get_bit(tmr_tab, i) ? "(level)" : ""); + empty =3D false; + } + } + qemu_printf("%s\n", empty ? "(none)" : ""); +} + +void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) +{ + X86CPU *cpu =3D X86_CPU(cs); + APICCommonState *s =3D APIC_COMMON(cpu->apic_state); + if (!s) { + qemu_printf("local apic state not available\n"); + return; + } + uint32_t *lvt =3D s->lvt; + + qemu_printf("dumping local APIC state for CPU %-2u\n\n", + CPU(cpu)->cpu_index); + dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false); + dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false); + dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false); + dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false); + dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false); + dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true); + + qemu_printf("Timer\t DCR=3D0x%x (divide by %u) initial_count =3D %u" + " current_count =3D %u\n", + s->divide_conf & APIC_DCR_MASK, + divider_conf(s->divide_conf), + s->initial_count, apic_get_current_count(s)); + + qemu_printf("SPIV\t 0x%08x APIC %s, focus=3D%s, spurious vec %u\n", + s->spurious_vec, + s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disab= led", + s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off", + s->spurious_vec & APIC_VECTOR_MASK); + + dump_apic_icr(s, &cpu->env); + + qemu_printf("ESR\t 0x%08x\n", s->esr); + + dump_apic_interrupt("ISR", s->isr, s->tmr); + dump_apic_interrupt("IRR", s->irr, s->tmr); + + qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x", + s->arb_id, s->tpr, s->dest_mode, s->log_dest); + if (s->dest_mode =3D=3D 0) { + qemu_printf("(cluster %u: id %u)", + s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT, + s->log_dest & APIC_LOGDEST_XAPIC_ID); + } + qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s)); +} +#else +void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) +{ +} +#endif /* !CONFIG_USER_ONLY */ + +#define DUMP_CODE_BYTES_TOTAL 50 +#define DUMP_CODE_BYTES_BACKWARD 20 + +void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + int eflags, i, nb; + char cc_op_name[32]; + static const char *seg_name[6] =3D { "ES", "CS", "SS", "DS", "FS", "GS= " }; + + eflags =3D cpu_compute_eflags(env); +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "RAX=3D%016" PRIx64 " RBX=3D%016" PRIx64 " RCX=3D%= 016" PRIx64 " RDX=3D%016" PRIx64 "\n" + "RSI=3D%016" PRIx64 " RDI=3D%016" PRIx64 " RBP=3D%016= " PRIx64 " RSP=3D%016" PRIx64 "\n" + "R8 =3D%016" PRIx64 " R9 =3D%016" PRIx64 " R10=3D%016= " PRIx64 " R11=3D%016" PRIx64 "\n" + "R12=3D%016" PRIx64 " R13=3D%016" PRIx64 " R14=3D%016= " PRIx64 " R15=3D%016" PRIx64 "\n" + "RIP=3D%016" PRIx64 " RFL=3D%08x [%c%c%c%c%c%c%c] CPL= =3D%d II=3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", + env->regs[R_EAX], + env->regs[R_EBX], + env->regs[R_ECX], + env->regs[R_EDX], + env->regs[R_ESI], + env->regs[R_EDI], + env->regs[R_EBP], + env->regs[R_ESP], + env->regs[8], + env->regs[9], + env->regs[10], + env->regs[11], + env->regs[12], + env->regs[13], + env->regs[14], + env->regs[15], + env->eip, eflags, + eflags & DF_MASK ? 'D' : '-', + eflags & CC_O ? 'O' : '-', + eflags & CC_S ? 'S' : '-', + eflags & CC_Z ? 'Z' : '-', + eflags & CC_A ? 'A' : '-', + eflags & CC_P ? 'P' : '-', + eflags & CC_C ? 'C' : '-', + env->hflags & HF_CPL_MASK, + (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, + (env->a20_mask >> 20) & 1, + (env->hflags >> HF_SMM_SHIFT) & 1, + cs->halted); + } else +#endif + { + qemu_fprintf(f, "EAX=3D%08x EBX=3D%08x ECX=3D%08x EDX=3D%08x\n" + "ESI=3D%08x EDI=3D%08x EBP=3D%08x ESP=3D%08x\n" + "EIP=3D%08x EFL=3D%08x [%c%c%c%c%c%c%c] CPL=3D%d II= =3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", + (uint32_t)env->regs[R_EAX], + (uint32_t)env->regs[R_EBX], + (uint32_t)env->regs[R_ECX], + (uint32_t)env->regs[R_EDX], + (uint32_t)env->regs[R_ESI], + (uint32_t)env->regs[R_EDI], + (uint32_t)env->regs[R_EBP], + (uint32_t)env->regs[R_ESP], + (uint32_t)env->eip, eflags, + eflags & DF_MASK ? 'D' : '-', + eflags & CC_O ? 'O' : '-', + eflags & CC_S ? 'S' : '-', + eflags & CC_Z ? 'Z' : '-', + eflags & CC_A ? 'A' : '-', + eflags & CC_P ? 'P' : '-', + eflags & CC_C ? 'C' : '-', + env->hflags & HF_CPL_MASK, + (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, + (env->a20_mask >> 20) & 1, + (env->hflags >> HF_SMM_SHIFT) & 1, + cs->halted); + } + + for(i =3D 0; i < 6; i++) { + cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]); + } + cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt); + cpu_x86_dump_seg_cache(env, f, "TR", &env->tr); + +#ifdef TARGET_X86_64 + if (env->hflags & HF_LMA_MASK) { + qemu_fprintf(f, "GDT=3D %016" PRIx64 " %08x\n", + env->gdt.base, env->gdt.limit); + qemu_fprintf(f, "IDT=3D %016" PRIx64 " %08x\n", + env->idt.base, env->idt.limit); + qemu_fprintf(f, "CR0=3D%08x CR2=3D%016" PRIx64 " CR3=3D%016" PRIx6= 4 " CR4=3D%08x\n", + (uint32_t)env->cr[0], + env->cr[2], + env->cr[3], + (uint32_t)env->cr[4]); + for(i =3D 0; i < 4; i++) + qemu_fprintf(f, "DR%d=3D%016" PRIx64 " ", i, env->dr[i]); + qemu_fprintf(f, "\nDR6=3D%016" PRIx64 " DR7=3D%016" PRIx64 "\n", + env->dr[6], env->dr[7]); + } else +#endif + { + qemu_fprintf(f, "GDT=3D %08x %08x\n", + (uint32_t)env->gdt.base, env->gdt.limit); + qemu_fprintf(f, "IDT=3D %08x %08x\n", + (uint32_t)env->idt.base, env->idt.limit); + qemu_fprintf(f, "CR0=3D%08x CR2=3D%08x CR3=3D%08x CR4=3D%08x\n", + (uint32_t)env->cr[0], + (uint32_t)env->cr[2], + (uint32_t)env->cr[3], + (uint32_t)env->cr[4]); + for(i =3D 0; i < 4; i++) { + qemu_fprintf(f, "DR%d=3D" TARGET_FMT_lx " ", i, env->dr[i]); + } + qemu_fprintf(f, "\nDR6=3D" TARGET_FMT_lx " DR7=3D" TARGET_FMT_lx "= \n", + env->dr[6], env->dr[7]); + } + if (flags & CPU_DUMP_CCOP) { + if ((unsigned)env->cc_op < CC_OP_NB) + snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->= cc_op]); + else + snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "CCS=3D%016" PRIx64 " CCD=3D%016" PRIx64 " CCO= =3D%-8s\n", + env->cc_src, env->cc_dst, + cc_op_name); + } else +#endif + { + qemu_fprintf(f, "CCS=3D%08x CCD=3D%08x CCO=3D%-8s\n", + (uint32_t)env->cc_src, (uint32_t)env->cc_dst, + cc_op_name); + } + } + qemu_fprintf(f, "EFER=3D%016" PRIx64 "\n", env->efer); + if (flags & CPU_DUMP_FPU) { + int fptag; + fptag =3D 0; + for(i =3D 0; i < 8; i++) { + fptag |=3D ((!env->fptags[i]) << i); + } + update_mxcsr_from_sse_status(env); + qemu_fprintf(f, "FCW=3D%04x FSW=3D%04x [ST=3D%d] FTW=3D%02x MXCSR= =3D%08x\n", + env->fpuc, + (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11, + env->fpstt, + fptag, + env->mxcsr); + for(i=3D0;i<8;i++) { + CPU_LDoubleU u; + u.d =3D env->fpregs[i].d; + qemu_fprintf(f, "FPR%d=3D%016" PRIx64 " %04x", + i, u.l.lower, u.l.upper); + if ((i & 1) =3D=3D 1) + qemu_fprintf(f, "\n"); + else + qemu_fprintf(f, " "); + } + if (env->hflags & HF_CS64_MASK) + nb =3D 16; + else + nb =3D 8; + for(i=3D0;ixmm_regs[i].ZMM_L(3), + env->xmm_regs[i].ZMM_L(2), + env->xmm_regs[i].ZMM_L(1), + env->xmm_regs[i].ZMM_L(0)); + if ((i & 1) =3D=3D 1) + qemu_fprintf(f, "\n"); + else + qemu_fprintf(f, " "); + } + } + if (flags & CPU_DUMP_CODE) { + target_ulong base =3D env->segs[R_CS].base + env->eip; + target_ulong offs =3D MIN(env->eip, DUMP_CODE_BYTES_BACKWARD); + uint8_t code; + char codestr[3]; + + qemu_fprintf(f, "Code=3D"); + for (i =3D 0; i < DUMP_CODE_BYTES_TOTAL; i++) { + if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) =3D= =3D 0) { + snprintf(codestr, sizeof(codestr), "%02x", code); + } else { + snprintf(codestr, sizeof(codestr), "??"); + } + qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "", + i =3D=3D offs ? "<" : "", codestr, i =3D=3D offs = ? ">" : ""); + } + qemu_fprintf(f, "\n"); + } +} + diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9ecda75aec..d6ed45c5d7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2232,6 +2232,7 @@ void enable_compat_apic_id_mode(void); #define APIC_DEFAULT_ADDRESS 0xfee00000 #define APIC_SPACE_SIZE 0x100000 =20 +/* cpu-dump.c */ void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); =20 /* cpu.c */ diff --git a/target/i386/helper.c b/target/i386/helper.c index a1b3367ab2..6e7e0f507c 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -21,8 +21,6 @@ #include "qapi/qapi-events-run-state.h" #include "cpu.h" #include "exec/exec-all.h" -#include "qemu/qemu-print.h" -#include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY @@ -88,518 +86,6 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env) return 0; } =20 -/***********************************************************/ -/* x86 debug */ - -static const char *cc_op_str[CC_OP_NB] =3D { - "DYNAMIC", - "EFLAGS", - - "MULB", - "MULW", - "MULL", - "MULQ", - - "ADDB", - "ADDW", - "ADDL", - "ADDQ", - - "ADCB", - "ADCW", - "ADCL", - "ADCQ", - - "SUBB", - "SUBW", - "SUBL", - "SUBQ", - - "SBBB", - "SBBW", - "SBBL", - "SBBQ", - - "LOGICB", - "LOGICW", - "LOGICL", - "LOGICQ", - - "INCB", - "INCW", - "INCL", - "INCQ", - - "DECB", - "DECW", - "DECL", - "DECQ", - - "SHLB", - "SHLW", - "SHLL", - "SHLQ", - - "SARB", - "SARW", - "SARL", - "SARQ", - - "BMILGB", - "BMILGW", - "BMILGL", - "BMILGQ", - - "ADCX", - "ADOX", - "ADCOX", - - "CLR", -}; - -static void -cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, - const char *name, struct SegmentCache *sc) -{ -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "%-3s=3D%04x %016" PRIx64 " %08x %08x", name, - sc->selector, sc->base, sc->limit, - sc->flags & 0x00ffff00); - } else -#endif - { - qemu_fprintf(f, "%-3s=3D%04x %08x %08x %08x", name, sc->selector, - (uint32_t)sc->base, sc->limit, - sc->flags & 0x00ffff00); - } - - if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK)) - goto done; - - qemu_fprintf(f, " DPL=3D%d ", - (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT); - if (sc->flags & DESC_S_MASK) { - if (sc->flags & DESC_CS_MASK) { - qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" : - ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16")); - qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-= ', - (sc->flags & DESC_R_MASK) ? 'R' : '-'); - } else { - qemu_fprintf(f, (sc->flags & DESC_B_MASK - || env->hflags & HF_LMA_MASK) - ? "DS " : "DS16"); - qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-= ', - (sc->flags & DESC_W_MASK) ? 'W' : '-'); - } - qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-'); - } else { - static const char *sys_type_name[2][16] =3D { - { /* 32 bit mode */ - "Reserved", "TSS16-avl", "LDT", "TSS16-busy", - "CallGate16", "TaskGate", "IntGate16", "TrapGate16", - "Reserved", "TSS32-avl", "Reserved", "TSS32-busy", - "CallGate32", "Reserved", "IntGate32", "TrapGate32" - }, - { /* 64 bit mode */ - "", "Reserved", "LDT", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved", - "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64", - "Reserved", "IntGate64", "TrapGate64" - } - }; - qemu_fprintf(f, "%s", - sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0] - [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]); - } -done: - qemu_fprintf(f, "\n"); -} - -#ifndef CONFIG_USER_ONLY - -/* ARRAY_SIZE check is not required because - * DeliveryMode(dm) has a size of 3 bit. - */ -static inline const char *dm2str(uint32_t dm) -{ - static const char *str[] =3D { - "Fixed", - "...", - "SMI", - "...", - "NMI", - "INIT", - "...", - "ExtINT" - }; - return str[dm]; -} - -static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer) -{ - uint32_t dm =3D (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT; - qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s", - name, lvt, - lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi", - lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge", - lvt & APIC_LVT_MASKED ? "masked" : "", - lvt & APIC_LVT_DELIV_STS ? "pending" : "", - !is_timer ? - "" : lvt & APIC_LVT_TIMER_PERIODIC ? - "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ? - "tsc-deadline" : "one-shot", - dm2str(dm)); - if (dm !=3D APIC_DM_NMI) { - qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK); - } else { - qemu_printf("\n"); - } -} - -/* ARRAY_SIZE check is not required because - * destination shorthand has a size of 2 bit. - */ -static inline const char *shorthand2str(uint32_t shorthand) -{ - const char *str[] =3D { - "no-shorthand", "self", "all-self", "all" - }; - return str[shorthand]; -} - -static inline uint8_t divider_conf(uint32_t divide_conf) -{ - uint8_t divide_val =3D ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3= ); - - return divide_val =3D=3D 7 ? 1 : 2 << divide_val; -} - -static inline void mask2str(char *str, uint32_t val, uint8_t size) -{ - while (size--) { - *str++ =3D (val >> size) & 1 ? '1' : '0'; - } - *str =3D 0; -} - -#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16 - -static void dump_apic_icr(APICCommonState *s, CPUX86State *env) -{ - uint32_t icr =3D s->icr[0], icr2 =3D s->icr[1]; - uint8_t dest_shorthand =3D \ - (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT; - bool logical_mod =3D icr & APIC_ICR_DEST_MOD; - char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1]; - uint32_t dest_field; - bool x2apic; - - qemu_printf("ICR\t 0x%08x %s %s %s %s\n", - icr, - logical_mod ? "logical" : "physical", - icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge", - icr & APIC_ICR_LEVEL ? "assert" : "de-assert", - shorthand2str(dest_shorthand)); - - qemu_printf("ICR2\t 0x%08x", icr2); - if (dest_shorthand !=3D 0) { - qemu_printf("\n"); - return; - } - x2apic =3D env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC; - dest_field =3D x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT; - - if (!logical_mod) { - if (x2apic) { - qemu_printf(" cpu %u (X2APIC ID)\n", dest_field); - } else { - qemu_printf(" cpu %u (APIC ID)\n", - dest_field & APIC_LOGDEST_XAPIC_ID); - } - return; - } - - if (s->dest_mode =3D=3D 0xf) { /* flat mode */ - mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8); - qemu_printf(" mask %s (APIC ID)\n", apic_id_str); - } else if (s->dest_mode =3D=3D 0) { /* cluster mode */ - if (x2apic) { - mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16); - qemu_printf(" cluster %u mask %s (X2APIC ID)\n", - dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_s= tr); - } else { - mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4); - qemu_printf(" cluster %u mask %s (APIC ID)\n", - dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_st= r); - } - } -} - -static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab, - uint32_t *tmr_tab) -{ - int i, empty =3D true; - - qemu_printf("%s\t ", name); - for (i =3D 0; i < 256; i++) { - if (apic_get_bit(ireg_tab, i)) { - qemu_printf("%u%s ", i, - apic_get_bit(tmr_tab, i) ? "(level)" : ""); - empty =3D false; - } - } - qemu_printf("%s\n", empty ? "(none)" : ""); -} - -void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) -{ - X86CPU *cpu =3D X86_CPU(cs); - APICCommonState *s =3D APIC_COMMON(cpu->apic_state); - if (!s) { - qemu_printf("local apic state not available\n"); - return; - } - uint32_t *lvt =3D s->lvt; - - qemu_printf("dumping local APIC state for CPU %-2u\n\n", - CPU(cpu)->cpu_index); - dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false); - dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false); - dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false); - dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false); - dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false); - dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true); - - qemu_printf("Timer\t DCR=3D0x%x (divide by %u) initial_count =3D %u" - " current_count =3D %u\n", - s->divide_conf & APIC_DCR_MASK, - divider_conf(s->divide_conf), - s->initial_count, apic_get_current_count(s)); - - qemu_printf("SPIV\t 0x%08x APIC %s, focus=3D%s, spurious vec %u\n", - s->spurious_vec, - s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disab= led", - s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off", - s->spurious_vec & APIC_VECTOR_MASK); - - dump_apic_icr(s, &cpu->env); - - qemu_printf("ESR\t 0x%08x\n", s->esr); - - dump_apic_interrupt("ISR", s->isr, s->tmr); - dump_apic_interrupt("IRR", s->irr, s->tmr); - - qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x", - s->arb_id, s->tpr, s->dest_mode, s->log_dest); - if (s->dest_mode =3D=3D 0) { - qemu_printf("(cluster %u: id %u)", - s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT, - s->log_dest & APIC_LOGDEST_XAPIC_ID); - } - qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s)); -} -#else -void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) -{ -} -#endif /* !CONFIG_USER_ONLY */ - -#define DUMP_CODE_BYTES_TOTAL 50 -#define DUMP_CODE_BYTES_BACKWARD 20 - -void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - int eflags, i, nb; - char cc_op_name[32]; - static const char *seg_name[6] =3D { "ES", "CS", "SS", "DS", "FS", "GS= " }; - - eflags =3D cpu_compute_eflags(env); -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "RAX=3D%016" PRIx64 " RBX=3D%016" PRIx64 " RCX=3D%= 016" PRIx64 " RDX=3D%016" PRIx64 "\n" - "RSI=3D%016" PRIx64 " RDI=3D%016" PRIx64 " RBP=3D%016= " PRIx64 " RSP=3D%016" PRIx64 "\n" - "R8 =3D%016" PRIx64 " R9 =3D%016" PRIx64 " R10=3D%016= " PRIx64 " R11=3D%016" PRIx64 "\n" - "R12=3D%016" PRIx64 " R13=3D%016" PRIx64 " R14=3D%016= " PRIx64 " R15=3D%016" PRIx64 "\n" - "RIP=3D%016" PRIx64 " RFL=3D%08x [%c%c%c%c%c%c%c] CPL= =3D%d II=3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", - env->regs[R_EAX], - env->regs[R_EBX], - env->regs[R_ECX], - env->regs[R_EDX], - env->regs[R_ESI], - env->regs[R_EDI], - env->regs[R_EBP], - env->regs[R_ESP], - env->regs[8], - env->regs[9], - env->regs[10], - env->regs[11], - env->regs[12], - env->regs[13], - env->regs[14], - env->regs[15], - env->eip, eflags, - eflags & DF_MASK ? 'D' : '-', - eflags & CC_O ? 'O' : '-', - eflags & CC_S ? 'S' : '-', - eflags & CC_Z ? 'Z' : '-', - eflags & CC_A ? 'A' : '-', - eflags & CC_P ? 'P' : '-', - eflags & CC_C ? 'C' : '-', - env->hflags & HF_CPL_MASK, - (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, - (env->a20_mask >> 20) & 1, - (env->hflags >> HF_SMM_SHIFT) & 1, - cs->halted); - } else -#endif - { - qemu_fprintf(f, "EAX=3D%08x EBX=3D%08x ECX=3D%08x EDX=3D%08x\n" - "ESI=3D%08x EDI=3D%08x EBP=3D%08x ESP=3D%08x\n" - "EIP=3D%08x EFL=3D%08x [%c%c%c%c%c%c%c] CPL=3D%d II= =3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", - (uint32_t)env->regs[R_EAX], - (uint32_t)env->regs[R_EBX], - (uint32_t)env->regs[R_ECX], - (uint32_t)env->regs[R_EDX], - (uint32_t)env->regs[R_ESI], - (uint32_t)env->regs[R_EDI], - (uint32_t)env->regs[R_EBP], - (uint32_t)env->regs[R_ESP], - (uint32_t)env->eip, eflags, - eflags & DF_MASK ? 'D' : '-', - eflags & CC_O ? 'O' : '-', - eflags & CC_S ? 'S' : '-', - eflags & CC_Z ? 'Z' : '-', - eflags & CC_A ? 'A' : '-', - eflags & CC_P ? 'P' : '-', - eflags & CC_C ? 'C' : '-', - env->hflags & HF_CPL_MASK, - (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, - (env->a20_mask >> 20) & 1, - (env->hflags >> HF_SMM_SHIFT) & 1, - cs->halted); - } - - for(i =3D 0; i < 6; i++) { - cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]); - } - cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt); - cpu_x86_dump_seg_cache(env, f, "TR", &env->tr); - -#ifdef TARGET_X86_64 - if (env->hflags & HF_LMA_MASK) { - qemu_fprintf(f, "GDT=3D %016" PRIx64 " %08x\n", - env->gdt.base, env->gdt.limit); - qemu_fprintf(f, "IDT=3D %016" PRIx64 " %08x\n", - env->idt.base, env->idt.limit); - qemu_fprintf(f, "CR0=3D%08x CR2=3D%016" PRIx64 " CR3=3D%016" PRIx6= 4 " CR4=3D%08x\n", - (uint32_t)env->cr[0], - env->cr[2], - env->cr[3], - (uint32_t)env->cr[4]); - for(i =3D 0; i < 4; i++) - qemu_fprintf(f, "DR%d=3D%016" PRIx64 " ", i, env->dr[i]); - qemu_fprintf(f, "\nDR6=3D%016" PRIx64 " DR7=3D%016" PRIx64 "\n", - env->dr[6], env->dr[7]); - } else -#endif - { - qemu_fprintf(f, "GDT=3D %08x %08x\n", - (uint32_t)env->gdt.base, env->gdt.limit); - qemu_fprintf(f, "IDT=3D %08x %08x\n", - (uint32_t)env->idt.base, env->idt.limit); - qemu_fprintf(f, "CR0=3D%08x CR2=3D%08x CR3=3D%08x CR4=3D%08x\n", - (uint32_t)env->cr[0], - (uint32_t)env->cr[2], - (uint32_t)env->cr[3], - (uint32_t)env->cr[4]); - for(i =3D 0; i < 4; i++) { - qemu_fprintf(f, "DR%d=3D" TARGET_FMT_lx " ", i, env->dr[i]); - } - qemu_fprintf(f, "\nDR6=3D" TARGET_FMT_lx " DR7=3D" TARGET_FMT_lx "= \n", - env->dr[6], env->dr[7]); - } - if (flags & CPU_DUMP_CCOP) { - if ((unsigned)env->cc_op < CC_OP_NB) - snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->= cc_op]); - else - snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "CCS=3D%016" PRIx64 " CCD=3D%016" PRIx64 " CCO= =3D%-8s\n", - env->cc_src, env->cc_dst, - cc_op_name); - } else -#endif - { - qemu_fprintf(f, "CCS=3D%08x CCD=3D%08x CCO=3D%-8s\n", - (uint32_t)env->cc_src, (uint32_t)env->cc_dst, - cc_op_name); - } - } - qemu_fprintf(f, "EFER=3D%016" PRIx64 "\n", env->efer); - if (flags & CPU_DUMP_FPU) { - int fptag; - fptag =3D 0; - for(i =3D 0; i < 8; i++) { - fptag |=3D ((!env->fptags[i]) << i); - } - update_mxcsr_from_sse_status(env); - qemu_fprintf(f, "FCW=3D%04x FSW=3D%04x [ST=3D%d] FTW=3D%02x MXCSR= =3D%08x\n", - env->fpuc, - (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11, - env->fpstt, - fptag, - env->mxcsr); - for(i=3D0;i<8;i++) { - CPU_LDoubleU u; - u.d =3D env->fpregs[i].d; - qemu_fprintf(f, "FPR%d=3D%016" PRIx64 " %04x", - i, u.l.lower, u.l.upper); - if ((i & 1) =3D=3D 1) - qemu_fprintf(f, "\n"); - else - qemu_fprintf(f, " "); - } - if (env->hflags & HF_CS64_MASK) - nb =3D 16; - else - nb =3D 8; - for(i=3D0;ixmm_regs[i].ZMM_L(3), - env->xmm_regs[i].ZMM_L(2), - env->xmm_regs[i].ZMM_L(1), - env->xmm_regs[i].ZMM_L(0)); - if ((i & 1) =3D=3D 1) - qemu_fprintf(f, "\n"); - else - qemu_fprintf(f, " "); - } - } - if (flags & CPU_DUMP_CODE) { - target_ulong base =3D env->segs[R_CS].base + env->eip; - target_ulong offs =3D MIN(env->eip, DUMP_CODE_BYTES_BACKWARD); - uint8_t code; - char codestr[3]; - - qemu_fprintf(f, "Code=3D"); - for (i =3D 0; i < DUMP_CODE_BYTES_TOTAL; i++) { - if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) =3D= =3D 0) { - snprintf(codestr, sizeof(codestr), "%02x", code); - } else { - snprintf(codestr, sizeof(codestr), "??"); - } - qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "", - i =3D=3D offs ? "<" : "", codestr, i =3D=3D offs = ? ">" : ""); - } - qemu_fprintf(f, "\n"); - } -} - /***********************************************************/ /* x86 mmu */ /* XXX: add PGE support */ diff --git a/target/i386/meson.build b/target/i386/meson.build index 750471c9f3..c4bf20b319 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -4,6 +4,7 @@ i386_ss.add(files( 'gdbstub.c', 'helper.c', 'xsave_helper.c', + 'cpu-dump.c', )) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) =20 --=20 2.26.2 From nobody Mon May 6 20:54:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1606430396; cv=none; d=zohomail.com; s=zohoarc; b=dClyUwKFPXTxx3NSpLsUxkP0y+Mbay2GMyPOaz8gp4leX60dZ+JInGtt6lMwDhIzMFUHStxlhSQRhLmR/w/UakObal49EalOQ2so1bLWXMmXnWoUjVflR9lxddiWoAa6ZS9nrDBPW8xuOcB5RaL9laRhR6/yOXUyGO4ul6w2DwI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606430396; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gAa6/Zpj3TL2zoEukEuzgfsEHjiBprok8T62DxTG9cE=; b=L3taLgtYezi0IeXDF9zkHx2px3B0arRTRpFacx/14sxpsbUrGvtJmu4wSZh47wl3D4SxUJP4q67SBAHKmd3pYXnI0kTiYiOwfVpznpDh48LOPsj4yFlo7zIpBRA8FvUJk4cSv/8RkvYJp704b4BJaMymMn3U4Len3ZbOkl1/aKE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606430396218950.64446509116; Thu, 26 Nov 2020 14:39:56 -0800 (PST) Received: from localhost ([::1]:46058 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kiPve-0001Fm-1e for importer@patchew.org; Thu, 26 Nov 2020 17:39:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44080) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoe-0001WR-Av for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:40 -0500 Received: from mx2.suse.de ([195.135.220.15]:44642) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoW-0003HV-Uj for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:40 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id DA26FAF3E; Thu, 26 Nov 2020 22:32:28 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC v6 07/11] i386: move TCG cpu class initialization out of helper.c Date: Thu, 26 Nov 2020 23:32:14 +0100 Message-Id: <20201126223218.31480-8-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201126223218.31480-1-cfontana@suse.de> References: <20201126223218.31480-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana --- target/i386/cpu.c | 33 ++++------ target/i386/cpu.h | 97 ++--------------------------- target/i386/helper-tcg.h | 112 ++++++++++++++++++++++++++++++++++ target/i386/helper.c | 23 ------- target/i386/meson.build | 1 + target/i386/tcg-cpu.c | 71 +++++++++++++++++++++ target/i386/tcg-cpu.h | 15 +++++ target/i386/tcg/bpt_helper.c | 1 + target/i386/tcg/cc_helper.c | 1 + target/i386/tcg/excp_helper.c | 1 + target/i386/tcg/fpu_helper.c | 33 +++++----- target/i386/tcg/int_helper.c | 1 + target/i386/tcg/mem_helper.c | 1 + target/i386/tcg/misc_helper.c | 1 + target/i386/tcg/mpx_helper.c | 1 + target/i386/tcg/seg_helper.c | 1 + target/i386/tcg/smm_helper.c | 2 + target/i386/tcg/svm_helper.c | 1 + target/i386/tcg/translate.c | 1 + 19 files changed, 244 insertions(+), 153 deletions(-) create mode 100644 target/i386/helper-tcg.h create mode 100644 target/i386/tcg-cpu.c create mode 100644 target/i386/tcg-cpu.h diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b9bd249c8f..3462d0143f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -24,6 +24,8 @@ #include "qemu/qemu-print.h" =20 #include "cpu.h" +#include "tcg-cpu.h" +#include "helper-tcg.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" @@ -1495,7 +1497,8 @@ static inline uint64_t x86_cpu_xsave_components(X86CP= U *cpu) cpu->env.features[FEAT_XSAVE_COMP_LO]; } =20 -const char *get_register_name_32(unsigned int reg) +/* Return name of 32-bit register, from a R_* constant */ +static const char *get_register_name_32(unsigned int reg) { if (reg >=3D CPU_NB_REGS32) { return NULL; @@ -7012,13 +7015,6 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.eip =3D value; } =20 -static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) -{ - X86CPU *cpu =3D X86_CPU(cs); - - cpu->env.eip =3D tb->pc - tb->cs_base; -} - int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu =3D X86_CPU(cs); @@ -7252,17 +7248,18 @@ static void x86_cpu_common_class_init(ObjectClass *= oc, void *data) cc->class_by_name =3D x86_cpu_class_by_name; cc->parse_features =3D x86_cpu_parse_featurestr; cc->has_work =3D x86_cpu_has_work; + #ifdef CONFIG_TCG - cc->do_interrupt =3D x86_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; -#endif + tcg_cpu_common_class_init(cc); +#endif /* CONFIG_TCG */ + cc->dump_state =3D x86_cpu_dump_state; cc->set_pc =3D x86_cpu_set_pc; - cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; cc->gdb_read_register =3D x86_cpu_gdb_read_register; cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; + #ifndef CONFIG_USER_ONLY cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; @@ -7273,7 +7270,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->vmsd =3D &vmstate_x86_cpu; -#endif +#endif /* !CONFIG_USER_ONLY */ + cc->gdb_arch_name =3D x86_gdb_arch_name; #ifdef TARGET_X86_64 cc->gdb_core_xml_file =3D "i386-64bit.xml"; @@ -7281,15 +7279,6 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) #else cc->gdb_core_xml_file =3D "i386-32bit.xml"; cc->gdb_num_core_regs =3D 50; -#endif -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - cc->debug_excp_handler =3D breakpoint_handler; -#endif - cc->cpu_exec_enter =3D x86_cpu_exec_enter; - cc->cpu_exec_exit =3D x86_cpu_exec_exit; -#ifdef CONFIG_TCG - cc->tcg_initialize =3D tcg_x86_init; - cc->tlb_fill =3D x86_cpu_tlb_fill; #endif cc->disas_set_info =3D x86_disas_set_info; =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d6ed45c5d7..a0d64613dc 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -31,9 +31,6 @@ =20 #define KVM_HAVE_MCE_INJECTION 1 =20 -/* Maximum instruction code size */ -#define TARGET_MAX_INSN_SIZE 16 - /* support for self modifying code even if the modified instruction is close to the modifying instruction */ #define TARGET_HAS_PRECISE_SMC @@ -1037,6 +1034,12 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; * using this information. Condition codes are not generated if they * are only needed for conditional branches. */ + +#define CC_DST (env->cc_dst) +#define CC_SRC (env->cc_src) +#define CC_SRC2 (env->cc_src2) +#define CC_OP (env->cc_op) + typedef enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC =3D flags */ @@ -1765,12 +1768,6 @@ struct X86CPU { extern VMStateDescription vmstate_x86_cpu; #endif =20 -/** - * x86_cpu_do_interrupt: - * @cpu: vCPU the interrupt is to be handled by. - */ -void x86_cpu_do_interrupt(CPUState *cpu); -bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); =20 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -1793,9 +1790,6 @@ hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cp= u, vaddr addr, int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 -void x86_cpu_exec_enter(CPUState *cpu); -void x86_cpu_exec_exit(CPUState *cpu); - void x86_cpu_list(void); int cpu_x86_support_mca_broadcast(CPUX86State *env); =20 @@ -1920,9 +1914,6 @@ void host_cpuid(uint32_t function, uint32_t count, void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); =20 /* helper.c */ -bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void x86_cpu_set_a20(X86CPU *cpu, int a20_state); =20 #ifndef CONFIG_USER_ONLY @@ -1947,8 +1938,6 @@ void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t= val); void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); #endif =20 -void breakpoint_handler(CPUState *cs); - /* will be suppressed */ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); @@ -1958,16 +1947,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t n= ew_dr7); /* hw/pc.c */ uint64_t cpu_get_tsc(CPUX86State *env); =20 -/* XXX: This value should match the one returned by CPUID - * and in exec.c */ -# if defined(TARGET_X86_64) -# define TCG_PHYS_ADDR_BITS 40 -# else -# define TCG_PHYS_ADDR_BITS 36 -# endif - -#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) - #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_X86_CPU @@ -1999,30 +1978,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *= env) ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; } =20 -#define CC_DST (env->cc_dst) -#define CC_SRC (env->cc_src) -#define CC_SRC2 (env->cc_src2) -#define CC_OP (env->cc_op) - -/* n must be a constant to be efficient */ -static inline target_long lshift(target_long x, int n) -{ - if (n >=3D 0) { - return x << n; - } else { - return x >> (-n); - } -} - -/* float macros */ -#define FT0 (env->ft0) -#define ST0 (env->fpregs[env->fpstt].d) -#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) -#define ST1 ST(1) - -/* translate.c */ -void tcg_x86_init(void); - typedef CPUX86State CPUArchState; typedef X86CPU ArchCPU; =20 @@ -2052,19 +2007,6 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, i= nt bank, uint64_t status, uint64_t mcg_status, uint64_t add= r, uint64_t misc, int flags); =20 -/* excp_helper.c */ -void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); -void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_inde= x, - uintptr_t retaddr); -void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_ind= ex, - int error_code); -void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_= index, - int error_code, uintptr_t retadd= r); -void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_in= t, - int error_code, int next_eip_addend); - -/* cc_helper.c */ -extern const uint8_t parity_table[256]; uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); =20 static inline uint32_t cpu_compute_eflags(CPUX86State *env) @@ -2076,18 +2018,6 @@ static inline uint32_t cpu_compute_eflags(CPUX86Stat= e *env) return eflags; } =20 -/* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS - * after generating a call to a helper that uses this. - */ -static inline void cpu_load_eflags(CPUX86State *env, int eflags, - int update_mask) -{ - CC_SRC =3D eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - CC_OP =3D CC_OP_EFLAGS; - env->df =3D 1 - (2 * ((eflags >> 10) & 1)); - env->eflags =3D (env->eflags & ~update_mask) | - (eflags & update_mask) | 0x2; -} =20 /* load efer and update the corresponding hflags. XXX: do consistency checks with cpuid bits? */ @@ -2176,16 +2106,6 @@ void helper_lock_init(void); /* svm_helper.c */ void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, uint64_t param, uintptr_t retaddr); -void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, - uint64_t exit_info_1, uintptr_t retaddr); -void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); - -/* seg_helper.c */ -void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); - -/* smm_helper.c */ -void do_smm_enter(X86CPU *cpu); - /* apic.c */ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, @@ -2224,11 +2144,6 @@ typedef int X86CPUVersion; */ void x86_cpu_set_default_version(X86CPUVersion version); =20 -/* Return name of 32-bit register, from a R_* constant */ -const char *get_register_name_32(unsigned int reg); - -void enable_compat_apic_id_mode(void); - #define APIC_DEFAULT_ADDRESS 0xfee00000 #define APIC_SPACE_SIZE 0x100000 =20 diff --git a/target/i386/helper-tcg.h b/target/i386/helper-tcg.h new file mode 100644 index 0000000000..57b4391a7d --- /dev/null +++ b/target/i386/helper-tcg.h @@ -0,0 +1,112 @@ +/* + * TCG specific prototypes for helpers + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef I386_HELPER_TCG_H +#define I386_HELPER_TCG_H + +#include "exec/exec-all.h" + +/* Maximum instruction code size */ +#define TARGET_MAX_INSN_SIZE 16 + +/* + * XXX: This value should match the one returned by CPUID + * and in exec.c + */ +# if defined(TARGET_X86_64) +# define TCG_PHYS_ADDR_BITS 40 +# else +# define TCG_PHYS_ADDR_BITS 36 +# endif + +#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) + +/** + * x86_cpu_do_interrupt: + * @cpu: vCPU the interrupt is to be handled by. + */ +void x86_cpu_do_interrupt(CPUState *cpu); +bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); + +/* helper.c */ +bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +void breakpoint_handler(CPUState *cs); + +/* n must be a constant to be efficient */ +static inline target_long lshift(target_long x, int n) +{ + if (n >=3D 0) { + return x << n; + } else { + return x >> (-n); + } +} + +/* float macros */ +#define FT0 (env->ft0) +#define ST0 (env->fpregs[env->fpstt].d) +#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) +#define ST1 ST(1) + +/* translate.c */ +void tcg_x86_init(void); + +/* excp_helper.c */ +void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); +void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_inde= x, + uintptr_t retaddr); +void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_ind= ex, + int error_code); +void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_= index, + int error_code, uintptr_t retadd= r); +void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_in= t, + int error_code, int next_eip_addend); + +/* cc_helper.c */ +extern const uint8_t parity_table[256]; + +/* + * NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS + * after generating a call to a helper that uses this. + */ +static inline void cpu_load_eflags(CPUX86State *env, int eflags, + int update_mask) +{ + CC_SRC =3D eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + CC_OP =3D CC_OP_EFLAGS; + env->df =3D 1 - (2 * ((eflags >> 10) & 1)); + env->eflags =3D (env->eflags & ~update_mask) | + (eflags & update_mask) | 0x2; +} + +/* svm_helper.c */ +void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, + uint64_t exit_info_1, uintptr_t retaddr); +void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); + +/* seg_helper.c */ +void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); + +/* smm_helper.c */ +void do_smm_enter(X86CPU *cpu); + +#endif /* I386_HELPER_TCG_H */ diff --git a/target/i386/helper.c b/target/i386/helper.c index 6e7e0f507c..6bb0c53182 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -24,10 +24,8 @@ #include "sysemu/runstate.h" #include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY -#include "sysemu/tcg.h" #include "sysemu/hw_accel.h" #include "monitor/monitor.h" -#include "hw/i386/apic_internal.h" #endif =20 void cpu_sync_bndcs_hflags(CPUX86State *env) @@ -572,27 +570,6 @@ void do_cpu_sipi(X86CPU *cpu) } #endif =20 -/* Frob eflags into and out of the CPU temporary format. */ - -void x86_cpu_exec_enter(CPUState *cs) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - - CC_SRC =3D env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - env->df =3D 1 - (2 * ((env->eflags >> 10) & 1)); - CC_OP =3D CC_OP_EFLAGS; - env->eflags &=3D ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); -} - -void x86_cpu_exec_exit(CPUState *cs) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - - env->eflags =3D cpu_compute_eflags(env); -} - #ifndef CONFIG_USER_ONLY uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr) { diff --git a/target/i386/meson.build b/target/i386/meson.build index c4bf20b319..9c20208e5a 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -6,6 +6,7 @@ i386_ss.add(files( 'xsave_helper.c', 'cpu-dump.c', )) +i386_ss.add(when: 'CONFIG_TCG', if_true: files('tcg-cpu.c')) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) =20 i386_softmmu_ss =3D ss.source_set() diff --git a/target/i386/tcg-cpu.c b/target/i386/tcg-cpu.c new file mode 100644 index 0000000000..628dd29fe7 --- /dev/null +++ b/target/i386/tcg-cpu.c @@ -0,0 +1,71 @@ +/* + * i386 TCG cpu class initialization + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "tcg-cpu.h" +#include "exec/exec-all.h" +#include "sysemu/runstate.h" +#include "helper-tcg.h" + +#if !defined(CONFIG_USER_ONLY) +#include "hw/i386/apic.h" +#endif + +/* Frob eflags into and out of the CPU temporary format. */ + +static void x86_cpu_exec_enter(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + CC_SRC =3D env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + env->df =3D 1 - (2 * ((env->eflags >> 10) & 1)); + CC_OP =3D CC_OP_EFLAGS; + env->eflags &=3D ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); +} + +static void x86_cpu_exec_exit(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + env->eflags =3D cpu_compute_eflags(env); +} + +static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + X86CPU *cpu =3D X86_CPU(cs); + + cpu->env.eip =3D tb->pc - tb->cs_base; +} + +void tcg_cpu_common_class_init(CPUClass *cc) +{ + cc->do_interrupt =3D x86_cpu_do_interrupt; + cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; + cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; + cc->cpu_exec_enter =3D x86_cpu_exec_enter; + cc->cpu_exec_exit =3D x86_cpu_exec_exit; + cc->tcg_initialize =3D tcg_x86_init; + cc->tlb_fill =3D x86_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY + cc->debug_excp_handler =3D breakpoint_handler; +#endif +} diff --git a/target/i386/tcg-cpu.h b/target/i386/tcg-cpu.h new file mode 100644 index 0000000000..81f02e562e --- /dev/null +++ b/target/i386/tcg-cpu.h @@ -0,0 +1,15 @@ +/* + * i386 TCG CPU class initialization + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPU_H +#define TCG_CPU_H + +void tcg_cpu_common_class_init(CPUClass *cc); + +#endif /* TCG_CPU_H */ diff --git a/target/i386/tcg/bpt_helper.c b/target/i386/tcg/bpt_helper.c index e6cc2921e2..979230ac12 100644 --- a/target/i386/tcg/bpt_helper.c +++ b/target/i386/tcg/bpt_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" =20 =20 #ifndef CONFIG_USER_ONLY diff --git a/target/i386/tcg/cc_helper.c b/target/i386/tcg/cc_helper.c index 924dd3cd57..cc7ea9e8b9 100644 --- a/target/i386/tcg/cc_helper.c +++ b/target/i386/tcg/cc_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" =20 const uint8_t parity_table[256] =3D { CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index 191471749f..a0f44431fe 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -23,6 +23,7 @@ #include "qemu/log.h" #include "sysemu/runstate.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" =20 void helper_raise_interrupt(CPUX86State *env, int intno, int next_eip_adde= nd) { diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 03b35443a6..13f31b6ac7 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -26,6 +26,7 @@ #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" #include "fpu/softfloat-macros.h" +#include "helper-tcg.h" =20 #ifdef CONFIG_SOFTMMU #include "hw/irq.h" @@ -2986,23 +2987,21 @@ void update_mxcsr_status(CPUX86State *env) =20 void update_mxcsr_from_sse_status(CPUX86State *env) { - if (tcg_enabled()) { - uint8_t flags =3D get_float_exception_flags(&env->sse_status); - /* - * The MXCSR denormal flag has opposite semantics to - * float_flag_input_denormal (the softfloat code sets that flag - * only when flushing input denormals to zero, but SSE sets it - * only when not flushing them to zero), so is not converted - * here. - */ - env->mxcsr |=3D ((flags & float_flag_invalid ? FPUS_IE : 0) | - (flags & float_flag_divbyzero ? FPUS_ZE : 0) | - (flags & float_flag_overflow ? FPUS_OE : 0) | - (flags & float_flag_underflow ? FPUS_UE : 0) | - (flags & float_flag_inexact ? FPUS_PE : 0) | - (flags & float_flag_output_denormal ? FPUS_UE | FPU= S_PE : - 0)); - } + uint8_t flags =3D get_float_exception_flags(&env->sse_status); + /* + * The MXCSR denormal flag has opposite semantics to + * float_flag_input_denormal (the softfloat code sets that flag + * only when flushing input denormals to zero, but SSE sets it + * only when not flushing them to zero), so is not converted + * here. + */ + env->mxcsr |=3D ((flags & float_flag_invalid ? FPUS_IE : 0) | + (flags & float_flag_divbyzero ? FPUS_ZE : 0) | + (flags & float_flag_overflow ? FPUS_OE : 0) | + (flags & float_flag_underflow ? FPUS_UE : 0) | + (flags & float_flag_inexact ? FPUS_PE : 0) | + (flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE= : + 0)); } =20 void helper_update_mxcsr(CPUX86State *env) diff --git a/target/i386/tcg/int_helper.c b/target/i386/tcg/int_helper.c index 4f89436b53..87fa7280ee 100644 --- a/target/i386/tcg/int_helper.c +++ b/target/i386/tcg/int_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "qapi/error.h" #include "qemu/guest-random.h" +#include "helper-tcg.h" =20 //#define DEBUG_MULDIV =20 diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 21ca3e3e88..e5cd2de1bf 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -25,6 +25,7 @@ #include "qemu/int128.h" #include "qemu/atomic128.h" #include "tcg/tcg.h" +#include "helper-tcg.h" =20 void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0) { diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index ae259d9145..c99370e5e3 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" +#include "helper-tcg.h" =20 void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) { diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c index fd966174b4..22423eedcd 100644 --- a/target/i386/tcg/mpx_helper.c +++ b/target/i386/tcg/mpx_helper.c @@ -22,6 +22,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" +#include "helper-tcg.h" =20 =20 void helper_bndck(CPUX86State *env, uint32_t fail) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 09b6554660..ed3e04a187 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -25,6 +25,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/log.h" +#include "helper-tcg.h" =20 //#define DEBUG_PCALL =20 diff --git a/target/i386/tcg/smm_helper.c b/target/i386/tcg/smm_helper.c index d20e8edfdf..62d027abd3 100644 --- a/target/i386/tcg/smm_helper.c +++ b/target/i386/tcg/smm_helper.c @@ -22,6 +22,8 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/log.h" +#include "helper-tcg.h" + =20 /* SMM support */ =20 diff --git a/target/i386/tcg/svm_helper.c b/target/i386/tcg/svm_helper.c index 38931586e5..097bb9b83d 100644 --- a/target/i386/tcg/svm_helper.c +++ b/target/i386/tcg/svm_helper.c @@ -22,6 +22,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "helper-tcg.h" =20 /* Secure Virtual Machine helpers */ =20 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 4c57307e42..5988ea0289 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -28,6 +28,7 @@ =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" +#include "helper-tcg.h" =20 #include "trace-tcg.h" #include "exec/log.h" --=20 2.26.2 From nobody Mon May 6 20:54:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1606430086; cv=none; d=zohomail.com; s=zohoarc; b=UBrP0XqMQI1hJkskyCAo3sDV3slftFqzTDdpQlyei3RVNNdFMYjH/xRBvdvFUNwL0BRGtB82zEM6AZEZuKcxdvw6/Xa94HqONrhyHV0TVDiuzg9sFDfV3UlGVtxmcI5tt8kLvUVtAybw9ICXQmp/DlDeya2m/q+GJQoCDS5tdKo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606430086; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HK/pmHw96Ie0pXdigSsiRSCSSsMZFAgwyF+OW1Qjguo=; b=MLRG9Nu1lGCquOMAidY3WYCIOQOupFb6RbwE9AfMDhaTtoBOEN3CEgTnDxyr7OHLZVfhL9GqetZZlzQblZwqY7vVIfmosus1C461oDzhm3DQiTS/EXZ4V6ilhKDeTmIpQod2F6WoiU521OJQsrA7TmpuBCvFMY+z0Iw1IgWgqsQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606430086148681.296658707124; Thu, 26 Nov 2020 14:34:46 -0800 (PST) Received: from localhost ([::1]:58750 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kiPqe-0003DZ-UT for importer@patchew.org; Thu, 26 Nov 2020 17:34:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44060) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoc-0001TI-Tu for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:38 -0500 Received: from mx2.suse.de ([195.135.220.15]:44640) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoW-0003HW-UH for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:38 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id B41DBAF40; Thu, 26 Nov 2020 22:32:29 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC v6 08/11] accel: extend AccelState and AccelClass to user-mode Date: Thu, 26 Nov 2020 23:32:15 +0100 Message-Id: <20201126223218.31480-9-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201126223218.31480-1-cfontana@suse.de> References: <20201126223218.31480-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana --- MAINTAINERS | 2 +- accel/accel-common.c | 50 ++++++++++++++++++++++++++++++ accel/{accel.c =3D> accel-softmmu.c} | 27 ++-------------- accel/accel-user.c | 24 ++++++++++++++ accel/meson.build | 4 ++- accel/qtest/qtest.c | 2 +- accel/tcg/meson.build | 2 +- accel/tcg/tcg-all.c | 7 ++++- accel/xen/xen-all.c | 2 +- bsd-user/main.c | 7 +++-- include/hw/boards.h | 2 +- include/{sysemu =3D> qemu}/accel.h | 14 +++++---- include/sysemu/hvf.h | 2 +- include/sysemu/kvm.h | 2 +- include/sysemu/kvm_int.h | 2 +- linux-user/main.c | 7 +++-- softmmu/memory.c | 2 +- softmmu/qtest.c | 2 +- softmmu/vl.c | 2 +- target/i386/hax/hax-all.c | 2 +- target/i386/hvf/hvf-i386.h | 2 +- target/i386/hvf/hvf.c | 2 +- target/i386/hvf/x86_task.c | 2 +- target/i386/whpx/whpx-all.c | 2 +- 24 files changed, 119 insertions(+), 53 deletions(-) create mode 100644 accel/accel-common.c rename accel/{accel.c =3D> accel-softmmu.c} (75%) create mode 100644 accel/accel-user.c rename include/{sysemu =3D> qemu}/accel.h (95%) diff --git a/MAINTAINERS b/MAINTAINERS index e892dd2220..d7c212843c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -433,7 +433,7 @@ Overall M: Richard Henderson R: Paolo Bonzini S: Maintained -F: include/sysemu/accel.h +F: include/qemu/accel.h F: accel/accel.c F: accel/Makefile.objs F: accel/stubs/Makefile.objs diff --git a/accel/accel-common.c b/accel/accel-common.c new file mode 100644 index 0000000000..ddec8cb5ae --- /dev/null +++ b/accel/accel-common.c @@ -0,0 +1,50 @@ +/* + * QEMU accel class, components common to system emulation and user mode + * + * Copyright (c) 2003-2008 Fabrice Bellard + * Copyright (c) 2014 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/accel.h" + +static const TypeInfo accel_type =3D { + .name =3D TYPE_ACCEL, + .parent =3D TYPE_OBJECT, + .class_size =3D sizeof(AccelClass), + .instance_size =3D sizeof(AccelState), +}; + +/* Lookup AccelClass from opt_name. Returns NULL if not found */ +AccelClass *accel_find(const char *opt_name) +{ + char *class_name =3D g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name); + AccelClass *ac =3D ACCEL_CLASS(object_class_by_name(class_name)); + g_free(class_name); + return ac; +} + +static void register_accel_types(void) +{ + type_register_static(&accel_type); +} + +type_init(register_accel_types); diff --git a/accel/accel.c b/accel/accel-softmmu.c similarity index 75% rename from accel/accel.c rename to accel/accel-softmmu.c index cb555e3b06..f89da8f9d1 100644 --- a/accel/accel.c +++ b/accel/accel-softmmu.c @@ -1,5 +1,5 @@ /* - * QEMU System Emulator, accelerator interfaces + * QEMU accel class, system emulation components * * Copyright (c) 2003-2008 Fabrice Bellard * Copyright (c) 2014 Red Hat Inc. @@ -24,28 +24,12 @@ */ =20 #include "qemu/osdep.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "hw/boards.h" #include "sysemu/arch_init.h" #include "sysemu/sysemu.h" #include "qom/object.h" =20 -static const TypeInfo accel_type =3D { - .name =3D TYPE_ACCEL, - .parent =3D TYPE_OBJECT, - .class_size =3D sizeof(AccelClass), - .instance_size =3D sizeof(AccelState), -}; - -/* Lookup AccelClass from opt_name. Returns NULL if not found */ -AccelClass *accel_find(const char *opt_name) -{ - char *class_name =3D g_strdup_printf(ACCEL_CLASS_NAME("%s"), opt_name); - AccelClass *ac =3D ACCEL_CLASS(object_class_by_name(class_name)); - g_free(class_name); - return ac; -} - int accel_init_machine(AccelState *accel, MachineState *ms) { AccelClass *acc =3D ACCEL_GET_CLASS(accel); @@ -76,10 +60,3 @@ void accel_setup_post(MachineState *ms) acc->setup_post(ms, accel); } } - -static void register_accel_types(void) -{ - type_register_static(&accel_type); -} - -type_init(register_accel_types); diff --git a/accel/accel-user.c b/accel/accel-user.c new file mode 100644 index 0000000000..26bdda6236 --- /dev/null +++ b/accel/accel-user.c @@ -0,0 +1,24 @@ +/* + * QEMU accel class, user-mode components + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qemu/accel.h" + +AccelState *current_accel(void) +{ + static AccelState *accel; + + if (!accel) { + AccelClass *ac =3D accel_find("tcg"); + + g_assert(ac !=3D NULL); + accel =3D ACCEL(object_new_with_class(OBJECT_CLASS(ac))); + } + return accel; +} diff --git a/accel/meson.build b/accel/meson.build index b26cca227a..b44ba30c86 100644 --- a/accel/meson.build +++ b/accel/meson.build @@ -1,4 +1,6 @@ -softmmu_ss.add(files('accel.c')) +specific_ss.add(files('accel-common.c')) +softmmu_ss.add(files('accel-softmmu.c')) +user_ss.add(files('accel-user.c')) =20 subdir('qtest') subdir('kvm') diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c index b282cea5cf..b4e731cb2b 100644 --- a/accel/qtest/qtest.c +++ b/accel/qtest/qtest.c @@ -17,7 +17,7 @@ #include "qemu/module.h" #include "qemu/option.h" #include "qemu/config-file.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/qtest.h" #include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index f39aab0a0c..424d9bb1fc 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,5 +1,6 @@ tcg_ss =3D ss.source_set() tcg_ss.add(files( + 'tcg-all.c', 'cpu-exec-common.c', 'cpu-exec.c', 'tcg-runtime-gvec.c', @@ -13,7 +14,6 @@ tcg_ss.add(when: 'CONFIG_PLUGIN', if_true: [files('plugin= -gen.c'), libdl]) specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) =20 specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: files( - 'tcg-all.c', 'cputlb.c', 'tcg-cpus.c', 'tcg-cpus-mttcg.c', diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index 1ac0b76515..dcbc6970da 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -30,9 +30,12 @@ #include "tcg/tcg.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "hw/boards.h" +#include "qemu/accel.h" #include "qapi/qapi-builtin-visit.h" + +#ifndef CONFIG_USER_ONLY #include "tcg-cpus.h" +#endif /* CONFIG_USER_ONLY */ =20 struct TCGState { AccelState parent_obj; @@ -110,6 +113,7 @@ static int tcg_init(MachineState *ms) */ tcg_region_init(); =20 +#ifndef CONFIG_USER_ONLY if (mttcg_enabled) { cpus_register_accel(&tcg_cpus_mttcg); } else if (icount_enabled()) { @@ -117,6 +121,7 @@ static int tcg_init(MachineState *ms) } else { cpus_register_accel(&tcg_cpus_rr); } +#endif /* CONFIG_USER_ONLY */ return 0; } =20 diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c index 878a4089d9..594aaf6b49 100644 --- a/accel/xen/xen-all.c +++ b/accel/xen/xen-all.c @@ -15,7 +15,7 @@ #include "hw/xen/xen-legacy-backend.h" #include "hw/xen/xen_pt.h" #include "chardev/char.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/cpus.h" #include "sysemu/xen.h" #include "sysemu/runstate.h" diff --git a/bsd-user/main.c b/bsd-user/main.c index 0a918e8f74..ec1f9d80a4 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "qemu/units.h" +#include "qemu/accel.h" #include "sysemu/tcg.h" #include "qemu-version.h" #include @@ -908,8 +909,11 @@ int main(int argc, char **argv) } =20 /* init tcg before creating CPUs and to get qemu_host_page_size */ - tcg_exec_init(0); + { + AccelClass *ac =3D ACCEL_GET_CLASS(current_accel()); =20 + ac->init_machine(NULL); + } cpu_type =3D parse_cpu_option(cpu_model); cpu =3D cpu_create(cpu_type); env =3D cpu->env_ptr; @@ -988,7 +992,6 @@ int main(int argc, char **argv) generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ tcg_prologue_init(tcg_ctx); - tcg_region_init(); =20 /* build Task State */ memset(ts, 0, sizeof(TaskState)); diff --git a/include/hw/boards.h b/include/hw/boards.h index a49e3a6b44..b754504afe 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -6,7 +6,7 @@ #include "exec/memory.h" #include "sysemu/hostmem.h" #include "sysemu/blockdev.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "qapi/qapi-types-machine.h" #include "qemu/module.h" #include "qom/object.h" diff --git a/include/sysemu/accel.h b/include/qemu/accel.h similarity index 95% rename from include/sysemu/accel.h rename to include/qemu/accel.h index e08b8ab8fa..fac4a18703 100644 --- a/include/sysemu/accel.h +++ b/include/qemu/accel.h @@ -20,8 +20,8 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN * THE SOFTWARE. */ -#ifndef HW_ACCEL_H -#define HW_ACCEL_H +#ifndef QEMU_ACCEL_H +#define QEMU_ACCEL_H =20 #include "qom/object.h" #include "exec/hwaddr.h" @@ -37,8 +37,8 @@ typedef struct AccelClass { /*< public >*/ =20 const char *name; -#ifndef CONFIG_USER_ONLY int (*init_machine)(MachineState *ms); +#ifndef CONFIG_USER_ONLY void (*setup_post)(MachineState *ms, AccelState *accel); bool (*has_memory)(MachineState *ms, AddressSpace *as, hwaddr start_addr, hwaddr size); @@ -67,11 +67,13 @@ typedef struct AccelClass { OBJECT_GET_CLASS(AccelClass, (obj), TYPE_ACCEL) =20 AccelClass *accel_find(const char *opt_name); +AccelState *current_accel(void); + +#ifndef CONFIG_USER_ONLY int accel_init_machine(AccelState *accel, MachineState *ms); =20 /* Called just before os_setup_post (ie just before drop OS privs) */ void accel_setup_post(MachineState *ms); +#endif /* !CONFIG_USER_ONLY */ =20 -AccelState *current_accel(void); - -#endif +#endif /* QEMU_ACCEL_H */ diff --git a/include/sysemu/hvf.h b/include/sysemu/hvf.h index f893768df9..c98636bc81 100644 --- a/include/sysemu/hvf.h +++ b/include/sysemu/hvf.h @@ -13,7 +13,7 @@ #ifndef HVF_H #define HVF_H =20 -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "qom/object.h" =20 #ifdef CONFIG_HVF diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index bb5d5cf497..739682f3c3 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -17,7 +17,7 @@ #include "qemu/queue.h" #include "hw/core/cpu.h" #include "exec/memattrs.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "qom/object.h" =20 #ifdef NEED_CPU_H diff --git a/include/sysemu/kvm_int.h b/include/sysemu/kvm_int.h index 65740806da..ccb8869f01 100644 --- a/include/sysemu/kvm_int.h +++ b/include/sysemu/kvm_int.h @@ -10,7 +10,7 @@ #define QEMU_KVM_INT_H =20 #include "exec/memory.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/kvm.h" =20 typedef struct KVMSlot diff --git a/linux-user/main.c b/linux-user/main.c index 24d1eb73ad..1825d2b835 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "qemu/units.h" +#include "qemu/accel.h" #include "sysemu/tcg.h" #include "qemu-version.h" #include @@ -703,8 +704,11 @@ int main(int argc, char **argv, char **envp) cpu_type =3D parse_cpu_option(cpu_model); =20 /* init tcg before creating CPUs and to get qemu_host_page_size */ - tcg_exec_init(0); + { + AccelClass *ac =3D ACCEL_GET_CLASS(current_accel()); =20 + ac->init_machine(NULL); + } cpu =3D cpu_create(cpu_type); env =3D cpu->env_ptr; cpu_reset(cpu); @@ -846,7 +850,6 @@ int main(int argc, char **argv, char **envp) generating the prologue until now so that the prologue can take the real value of GUEST_BASE into account. */ tcg_prologue_init(tcg_ctx); - tcg_region_init(); =20 target_cpu_copy_regs(env, regs); =20 diff --git a/softmmu/memory.c b/softmmu/memory.c index aa393f1bb0..92c8b4fc1f 100644 --- a/softmmu/memory.c +++ b/softmmu/memory.c @@ -32,7 +32,7 @@ #include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "sysemu/tcg.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "hw/boards.h" #include "migration/vmstate.h" =20 diff --git a/softmmu/qtest.c b/softmmu/qtest.c index 7965dc9a16..130c366615 100644 --- a/softmmu/qtest.c +++ b/softmmu/qtest.c @@ -20,7 +20,7 @@ #include "exec/ioport.h" #include "exec/memory.h" #include "hw/irq.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/cpu-timers.h" #include "qemu/config-file.h" #include "qemu/option.h" diff --git a/softmmu/vl.c b/softmmu/vl.c index e6e0ad5a92..bc20c526d2 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -40,7 +40,7 @@ =20 #include "qemu/error-report.h" #include "qemu/sockets.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "hw/usb.h" #include "hw/isa/isa.h" #include "hw/scsi/scsi.h" diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index fecfe8cd6e..d7f4bb44a7 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -28,7 +28,7 @@ #include "exec/address-spaces.h" =20 #include "qemu-common.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" #include "hw/boards.h" diff --git a/target/i386/hvf/hvf-i386.h b/target/i386/hvf/hvf-i386.h index e0edffd077..50b914fd67 100644 --- a/target/i386/hvf/hvf-i386.h +++ b/target/i386/hvf/hvf-i386.h @@ -16,7 +16,7 @@ #ifndef HVF_I386_H #define HVF_I386_H =20 -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/hvf.h" #include "cpu.h" #include "x86.h" diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index ed9356565c..ffc9efa40f 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -69,7 +69,7 @@ #include "exec/address-spaces.h" #include "hw/i386/apic_internal.h" #include "qemu/main-loop.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "target/i386/cpu.h" =20 #include "hvf-cpus.h" diff --git a/target/i386/hvf/x86_task.c b/target/i386/hvf/x86_task.c index 6f04478b3a..d66dfd7669 100644 --- a/target/i386/hvf/x86_task.c +++ b/target/i386/hvf/x86_task.c @@ -28,7 +28,7 @@ =20 #include "hw/i386/apic_internal.h" #include "qemu/main-loop.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "target/i386/cpu.h" =20 // TODO: taskswitch handling diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index f4f3e33eac..ee6b606194 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -13,7 +13,7 @@ #include "exec/address-spaces.h" #include "exec/ioport.h" #include "qemu-common.h" -#include "sysemu/accel.h" +#include "qemu/accel.h" #include "sysemu/whpx.h" #include "sysemu/cpus.h" #include "sysemu/runstate.h" --=20 2.26.2 From nobody Mon May 6 20:54:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1606430704; cv=none; d=zohomail.com; s=zohoarc; b=kc62YzILvUczBgPUw10lLf2OsGY5iYohfjaQCccydhlxvUeIOmODQ/zwCzNKebvkX3aslsme0NotxhEsVtk8Ejl0jIeFmhbEpkAYDxmdSDXgjFgf1e9mXtRoPQ0kxavpNtHYX+7x3HdnRrL0GA0CMrglmRYQpIPUwtlLq6a2L1Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606430704; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qwIqxR4oKgX3Bwh9gdk9yTU6c5Z90o+DXBf7mcvW82Y=; b=dUHqZyHBgIFIVkeXY4OQQeRN26Gl5OOPpolyHcIbRHa0pWnntEst6idS1bH+ek/HfiP/qBoEBxNksepRaEM3IENPHL+9Adz3AMFJXpLULJtqK/NORmbue1R1k6/F+o7RRHRoLyHKMV5fo08dT886MiLHCroXCSUz3itT7DOS0/I= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606430704612841.6800138189237; Thu, 26 Nov 2020 14:45:04 -0800 (PST) Received: from localhost ([::1]:57266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kiQ0d-00062u-Ak for importer@patchew.org; Thu, 26 Nov 2020 17:45:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44148) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPon-0001kT-Us for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:54 -0500 Received: from mx2.suse.de ([195.135.220.15]:44684) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoi-0003Id-B4 for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:49 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 9BC15AE42; Thu, 26 Nov 2020 22:32:30 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC v6 09/11] accel: replace struct CpusAccel with AccelOpsClass Date: Thu, 26 Nov 2020 23:32:16 +0100 Message-Id: <20201126223218.31480-10-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201126223218.31480-1-cfontana@suse.de> References: <20201126223218.31480-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" centralize the registration of the cpus.c module accelerator operations in accel/accel-softmmu.c Signed-off-by: Claudio Fontana --- MAINTAINERS | 3 ++- accel/accel-common.c | 11 +++++++++ accel/accel-softmmu.c | 43 +++++++++++++++++++++++++++++++--- accel/accel-softmmu.h | 15 ++++++++++++ accel/kvm/kvm-all.c | 2 -- accel/kvm/kvm-cpus.c | 26 ++++++++++++++++----- accel/kvm/kvm-cpus.h | 2 -- accel/qtest/qtest.c | 23 +++++++++++++----- accel/tcg/tcg-all.c | 14 ----------- accel/tcg/tcg-cpus-icount.c | 11 +-------- accel/tcg/tcg-cpus-icount.h | 2 ++ accel/tcg/tcg-cpus-mttcg.c | 12 +++------- accel/tcg/tcg-cpus-mttcg.h | 19 +++++++++++++++ accel/tcg/tcg-cpus-rr.c | 7 ------ accel/tcg/tcg-cpus.c | 43 ++++++++++++++++++++++++++++++++++ accel/tcg/tcg-cpus.h | 4 ---- accel/xen/xen-all.c | 22 ++++++++++++------ bsd-user/main.c | 3 ++- include/qemu/accel.h | 2 ++ include/sysemu/accel-ops.h | 45 ++++++++++++++++++++++++++++++++++++ include/sysemu/cpus.h | 26 ++++----------------- linux-user/main.c | 1 + softmmu/cpus.c | 12 +++++----- softmmu/vl.c | 8 +++++-- target/i386/hax/hax-all.c | 3 --- target/i386/hax/hax-cpus.c | 29 +++++++++++++++++------ target/i386/hax/hax-cpus.h | 2 -- target/i386/hvf/hvf-cpus.c | 27 +++++++++++++++++----- target/i386/hvf/hvf-cpus.h | 2 -- target/i386/hvf/hvf.c | 1 - target/i386/whpx/whpx-all.c | 2 -- target/i386/whpx/whpx-cpus.c | 29 +++++++++++++++++------ target/i386/whpx/whpx-cpus.h | 2 -- 33 files changed, 320 insertions(+), 133 deletions(-) create mode 100644 accel/accel-softmmu.h create mode 100644 accel/tcg/tcg-cpus-mttcg.h create mode 100644 include/sysemu/accel-ops.h diff --git a/MAINTAINERS b/MAINTAINERS index d7c212843c..df64a0d190 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -434,7 +434,8 @@ M: Richard Henderson R: Paolo Bonzini S: Maintained F: include/qemu/accel.h -F: accel/accel.c +F: include/sysemu/accel-ops.h +F: accel/accel-*.c F: accel/Makefile.objs F: accel/stubs/Makefile.objs =20 diff --git a/accel/accel-common.c b/accel/accel-common.c index ddec8cb5ae..3910b7dbe0 100644 --- a/accel/accel-common.c +++ b/accel/accel-common.c @@ -26,6 +26,10 @@ #include "qemu/osdep.h" #include "qemu/accel.h" =20 +#ifndef CONFIG_USER_ONLY +#include "accel-softmmu.h" +#endif /* !CONFIG_USER_ONLY */ + static const TypeInfo accel_type =3D { .name =3D TYPE_ACCEL, .parent =3D TYPE_OBJECT, @@ -42,6 +46,13 @@ AccelClass *accel_find(const char *opt_name) return ac; } =20 +void accel_init_interfaces(AccelClass *ac, const char *cpu_type) +{ +#ifndef CONFIG_USER_ONLY + accel_init_ops_interfaces(ac); +#endif /* !CONFIG_USER_ONLY */ +} + static void register_accel_types(void) { type_register_static(&accel_type); diff --git a/accel/accel-softmmu.c b/accel/accel-softmmu.c index f89da8f9d1..2d15d3f2f4 100644 --- a/accel/accel-softmmu.c +++ b/accel/accel-softmmu.c @@ -26,9 +26,9 @@ #include "qemu/osdep.h" #include "qemu/accel.h" #include "hw/boards.h" -#include "sysemu/arch_init.h" -#include "sysemu/sysemu.h" -#include "qom/object.h" +#include "sysemu/cpus.h" + +#include "accel-softmmu.h" =20 int accel_init_machine(AccelState *accel, MachineState *ms) { @@ -60,3 +60,40 @@ void accel_setup_post(MachineState *ms) acc->setup_post(ms, accel); } } + +/* initialize the arch-independent accel operation interfaces */ +void accel_init_ops_interfaces(AccelClass *ac) +{ + const char *ac_name; + char *ops_name; + AccelOpsClass *ops; + + ac_name =3D object_class_get_name(OBJECT_CLASS(ac)); + g_assert(ac_name !=3D NULL); + + ops_name =3D g_strdup_printf("%s" ACCEL_OPS_SUFFIX, ac_name); + ops =3D ACCEL_OPS_CLASS(object_class_by_name(ops_name)); + g_free(ops_name); + + /* + * all accelerators need to define ops, providing at least a mandatory + * non-NULL create_vcpu_thread operation. + */ + g_assert(ops !=3D NULL); + if (ops->ops_init) { + ops->ops_init(ops); + } + cpus_register_accel(ops); +} + +static const TypeInfo accel_ops_type_info =3D { + .name =3D TYPE_ACCEL_OPS, + .parent =3D TYPE_OBJECT, + .abstract =3D true, + .class_size =3D sizeof(AccelOpsClass), +}; +static void accel_softmmu_register_types(void) +{ + type_register_static(&accel_ops_type_info); +} +type_init(accel_softmmu_register_types); diff --git a/accel/accel-softmmu.h b/accel/accel-softmmu.h new file mode 100644 index 0000000000..2877b5c234 --- /dev/null +++ b/accel/accel-softmmu.h @@ -0,0 +1,15 @@ +/* + * QEMU System Emulation accel internal functions + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ACCEL_SOFTMMU_H +#define ACCEL_SOFTMMU_H + +void accel_init_ops_interfaces(AccelClass *ac); + +#endif /* ACCEL_SOFTMMU_H */ diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 9ef5daf4c5..33156cc4c7 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -2251,8 +2251,6 @@ static int kvm_init(MachineState *ms) ret =3D ram_block_discard_disable(true); assert(!ret); } - - cpus_register_accel(&kvm_cpus); return 0; =20 err: diff --git a/accel/kvm/kvm-cpus.c b/accel/kvm/kvm-cpus.c index d809b1e74c..fc9dda46ae 100644 --- a/accel/kvm/kvm-cpus.c +++ b/accel/kvm/kvm-cpus.c @@ -74,11 +74,25 @@ static void kvm_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); } =20 -const CpusAccel kvm_cpus =3D { - .create_vcpu_thread =3D kvm_start_vcpu_thread, +static void kvm_cpus_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 - .synchronize_post_reset =3D kvm_cpu_synchronize_post_reset, - .synchronize_post_init =3D kvm_cpu_synchronize_post_init, - .synchronize_state =3D kvm_cpu_synchronize_state, - .synchronize_pre_loadvm =3D kvm_cpu_synchronize_pre_loadvm, + ops->create_vcpu_thread =3D kvm_start_vcpu_thread; + ops->synchronize_post_reset =3D kvm_cpu_synchronize_post_reset; + ops->synchronize_post_init =3D kvm_cpu_synchronize_post_init; + ops->synchronize_state =3D kvm_cpu_synchronize_state; + ops->synchronize_pre_loadvm =3D kvm_cpu_synchronize_pre_loadvm; }; +static const TypeInfo kvm_cpus_type_info =3D { + .name =3D ACCEL_OPS_NAME("kvm"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D kvm_cpus_class_init, + .abstract =3D true, +}; +static void kvm_cpus_register_types(void) +{ + type_register_static(&kvm_cpus_type_info); +} +type_init(kvm_cpus_register_types); diff --git a/accel/kvm/kvm-cpus.h b/accel/kvm/kvm-cpus.h index 3df732b816..bf0bd1bee4 100644 --- a/accel/kvm/kvm-cpus.h +++ b/accel/kvm/kvm-cpus.h @@ -12,8 +12,6 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel kvm_cpus; - int kvm_init_vcpu(CPUState *cpu, Error **errp); int kvm_cpu_exec(CPUState *cpu); void kvm_destroy_vcpu(CPUState *cpu); diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c index b4e731cb2b..68d86de30f 100644 --- a/accel/qtest/qtest.c +++ b/accel/qtest/qtest.c @@ -25,14 +25,8 @@ #include "qemu/main-loop.h" #include "hw/core/cpu.h" =20 -const CpusAccel qtest_cpus =3D { - .create_vcpu_thread =3D dummy_start_vcpu_thread, - .get_virtual_clock =3D qtest_get_virtual_clock, -}; - static int qtest_init_accel(MachineState *ms) { - cpus_register_accel(&qtest_cpus); return 0; } =20 @@ -52,9 +46,26 @@ static const TypeInfo qtest_accel_type =3D { .class_init =3D qtest_accel_class_init, }; =20 +static void qtest_cpus_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); + + ops->create_vcpu_thread =3D dummy_start_vcpu_thread; + ops->get_virtual_clock =3D qtest_get_virtual_clock; +}; + +static const TypeInfo qtest_cpus_type_info =3D { + .name =3D ACCEL_OPS_NAME("qtest"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D qtest_cpus_class_init, + .abstract =3D true, +}; + static void qtest_type_init(void) { type_register_static(&qtest_accel_type); + type_register_static(&qtest_cpus_type_info); } =20 type_init(qtest_type_init); diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index dcbc6970da..2b86df9ba0 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -33,10 +33,6 @@ #include "qemu/accel.h" #include "qapi/qapi-builtin-visit.h" =20 -#ifndef CONFIG_USER_ONLY -#include "tcg-cpus.h" -#endif /* CONFIG_USER_ONLY */ - struct TCGState { AccelState parent_obj; =20 @@ -112,16 +108,6 @@ static int tcg_init(MachineState *ms) * Initialize TCG regions */ tcg_region_init(); - -#ifndef CONFIG_USER_ONLY - if (mttcg_enabled) { - cpus_register_accel(&tcg_cpus_mttcg); - } else if (icount_enabled()) { - cpus_register_accel(&tcg_cpus_icount); - } else { - cpus_register_accel(&tcg_cpus_rr); - } -#endif /* CONFIG_USER_ONLY */ return 0; } =20 diff --git a/accel/tcg/tcg-cpus-icount.c b/accel/tcg/tcg-cpus-icount.c index 9f45432275..5445b4d545 100644 --- a/accel/tcg/tcg-cpus-icount.c +++ b/accel/tcg/tcg-cpus-icount.c @@ -125,7 +125,7 @@ void icount_process_data(CPUState *cpu) replay_mutex_unlock(); } =20 -static void icount_handle_interrupt(CPUState *cpu, int mask) +void icount_handle_interrupt(CPUState *cpu, int mask) { int old_mask =3D cpu->interrupt_request; =20 @@ -136,12 +136,3 @@ static void icount_handle_interrupt(CPUState *cpu, int= mask) cpu_abort(cpu, "Raised interrupt while not in I/O function"); } } - -const CpusAccel tcg_cpus_icount =3D { - .create_vcpu_thread =3D rr_start_vcpu_thread, - .kick_vcpu_thread =3D rr_kick_vcpu_thread, - - .handle_interrupt =3D icount_handle_interrupt, - .get_virtual_clock =3D icount_get, - .get_elapsed_ticks =3D icount_get, -}; diff --git a/accel/tcg/tcg-cpus-icount.h b/accel/tcg/tcg-cpus-icount.h index b695939dfa..d884aa2aaa 100644 --- a/accel/tcg/tcg-cpus-icount.h +++ b/accel/tcg/tcg-cpus-icount.h @@ -14,4 +14,6 @@ void icount_handle_deadline(void); void icount_prepare_for_run(CPUState *cpu); void icount_process_data(CPUState *cpu); =20 +void icount_handle_interrupt(CPUState *cpu, int mask); + #endif /* TCG_CPUS_ICOUNT_H */ diff --git a/accel/tcg/tcg-cpus-mttcg.c b/accel/tcg/tcg-cpus-mttcg.c index 9c3767d260..dabf5ed42e 100644 --- a/accel/tcg/tcg-cpus-mttcg.c +++ b/accel/tcg/tcg-cpus-mttcg.c @@ -33,6 +33,7 @@ #include "hw/boards.h" =20 #include "tcg-cpus.h" +#include "tcg-cpus-mttcg.h" =20 /* * In the multi-threaded case each vCPU has its own thread. The TLS @@ -103,12 +104,12 @@ static void *mttcg_cpu_thread_fn(void *arg) return NULL; } =20 -static void mttcg_kick_vcpu_thread(CPUState *cpu) +void mttcg_kick_vcpu_thread(CPUState *cpu) { cpu_exit(cpu); } =20 -static void mttcg_start_vcpu_thread(CPUState *cpu) +void mttcg_start_vcpu_thread(CPUState *cpu) { char thread_name[VCPU_THREAD_NAME_SIZE]; =20 @@ -131,10 +132,3 @@ static void mttcg_start_vcpu_thread(CPUState *cpu) cpu->hThread =3D qemu_thread_get_handle(cpu->thread); #endif } - -const CpusAccel tcg_cpus_mttcg =3D { - .create_vcpu_thread =3D mttcg_start_vcpu_thread, - .kick_vcpu_thread =3D mttcg_kick_vcpu_thread, - - .handle_interrupt =3D tcg_cpus_handle_interrupt, -}; diff --git a/accel/tcg/tcg-cpus-mttcg.h b/accel/tcg/tcg-cpus-mttcg.h new file mode 100644 index 0000000000..0af91dd3b3 --- /dev/null +++ b/accel/tcg/tcg-cpus-mttcg.h @@ -0,0 +1,19 @@ +/* + * QEMU TCG Multi Threaded vCPUs implementation + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPUS_MTTCG_H +#define TCG_CPUS_MTTCG_H + +/* kick MTTCG vCPU thread */ +void mttcg_kick_vcpu_thread(CPUState *cpu); + +/* start an mttcg vCPU thread */ +void mttcg_start_vcpu_thread(CPUState *cpu); + +#endif /* TCG_CPUS_MTTCG_H */ diff --git a/accel/tcg/tcg-cpus-rr.c b/accel/tcg/tcg-cpus-rr.c index 0181d2e4eb..802c57bb60 100644 --- a/accel/tcg/tcg-cpus-rr.c +++ b/accel/tcg/tcg-cpus-rr.c @@ -296,10 +296,3 @@ void rr_start_vcpu_thread(CPUState *cpu) cpu->created =3D true; } } - -const CpusAccel tcg_cpus_rr =3D { - .create_vcpu_thread =3D rr_start_vcpu_thread, - .kick_vcpu_thread =3D rr_kick_vcpu_thread, - - .handle_interrupt =3D tcg_cpus_handle_interrupt, -}; diff --git a/accel/tcg/tcg-cpus.c b/accel/tcg/tcg-cpus.c index e335f9f155..38a58ab271 100644 --- a/accel/tcg/tcg-cpus.c +++ b/accel/tcg/tcg-cpus.c @@ -35,6 +35,9 @@ #include "hw/boards.h" =20 #include "tcg-cpus.h" +#include "tcg-cpus-mttcg.h" +#include "tcg-cpus-rr.h" +#include "tcg-cpus-icount.h" =20 /* common functionality among all TCG variants */ =20 @@ -80,3 +83,43 @@ void tcg_cpus_handle_interrupt(CPUState *cpu, int mask) qatomic_set(&cpu_neg(cpu)->icount_decr.u16.high, -1); } } + +static void tcg_cpus_ops_init(AccelOpsClass *ops) +{ + if (qemu_tcg_mttcg_enabled()) { + ops->create_vcpu_thread =3D mttcg_start_vcpu_thread; + ops->kick_vcpu_thread =3D mttcg_kick_vcpu_thread; + ops->handle_interrupt =3D tcg_cpus_handle_interrupt; + + } else if (icount_enabled()) { + ops->create_vcpu_thread =3D rr_start_vcpu_thread; + ops->kick_vcpu_thread =3D rr_kick_vcpu_thread; + ops->handle_interrupt =3D icount_handle_interrupt; + ops->get_virtual_clock =3D icount_get; + ops->get_elapsed_ticks =3D icount_get; + + } else { + ops->create_vcpu_thread =3D rr_start_vcpu_thread; + ops->kick_vcpu_thread =3D rr_kick_vcpu_thread; + ops->handle_interrupt =3D tcg_cpus_handle_interrupt; + } +} + +static void tcg_cpus_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); + + ops->ops_init =3D tcg_cpus_ops_init; +}; +static const TypeInfo tcg_cpus_type_info =3D { + .name =3D ACCEL_OPS_NAME("tcg"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D tcg_cpus_class_init, + .abstract =3D true, +}; +static void tcg_cpus_register_types(void) +{ + type_register_static(&tcg_cpus_type_info); +} +type_init(tcg_cpus_register_types); diff --git a/accel/tcg/tcg-cpus.h b/accel/tcg/tcg-cpus.h index d6893a32f8..923cbace12 100644 --- a/accel/tcg/tcg-cpus.h +++ b/accel/tcg/tcg-cpus.h @@ -14,10 +14,6 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel tcg_cpus_mttcg; -extern const CpusAccel tcg_cpus_icount; -extern const CpusAccel tcg_cpus_rr; - void tcg_cpus_destroy(CPUState *cpu); int tcg_cpus_exec(CPUState *cpu); void tcg_cpus_handle_interrupt(CPUState *cpu, int mask); diff --git a/accel/xen/xen-all.c b/accel/xen/xen-all.c index 594aaf6b49..cd5aa2b96e 100644 --- a/accel/xen/xen-all.c +++ b/accel/xen/xen-all.c @@ -154,10 +154,6 @@ static void xen_setup_post(MachineState *ms, AccelStat= e *accel) } } =20 -const CpusAccel xen_cpus =3D { - .create_vcpu_thread =3D dummy_start_vcpu_thread, -}; - static int xen_init(MachineState *ms) { MachineClass *mc =3D MACHINE_GET_CLASS(ms); @@ -185,9 +181,6 @@ static int xen_init(MachineState *ms) * opt out of system RAM being allocated by generic code */ mc->default_ram_id =3D NULL; - - cpus_register_accel(&xen_cpus); - return 0; } =20 @@ -222,9 +215,24 @@ static const TypeInfo xen_accel_type =3D { .class_init =3D xen_accel_class_init, }; =20 +static void xen_cpus_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); + + ops->create_vcpu_thread =3D dummy_start_vcpu_thread; +}; +static const TypeInfo xen_cpus_type_info =3D { + .name =3D ACCEL_OPS_NAME("xen"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D xen_cpus_class_init, + .abstract =3D true, +}; + static void xen_type_init(void) { type_register_static(&xen_accel_type); + type_register_static(&xen_cpus_type_info); } =20 type_init(xen_type_init); diff --git a/bsd-user/main.c b/bsd-user/main.c index ec1f9d80a4..25a757c746 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -908,13 +908,14 @@ int main(int argc, char **argv) #endif } =20 + cpu_type =3D parse_cpu_option(cpu_model); /* init tcg before creating CPUs and to get qemu_host_page_size */ { AccelClass *ac =3D ACCEL_GET_CLASS(current_accel()); =20 ac->init_machine(NULL); + accel_init_interfaces(ac, cpu_type); } - cpu_type =3D parse_cpu_option(cpu_model); cpu =3D cpu_create(cpu_type); env =3D cpu->env_ptr; #if defined(TARGET_SPARC) || defined(TARGET_PPC) diff --git a/include/qemu/accel.h b/include/qemu/accel.h index fac4a18703..68a57e040f 100644 --- a/include/qemu/accel.h +++ b/include/qemu/accel.h @@ -69,6 +69,8 @@ typedef struct AccelClass { AccelClass *accel_find(const char *opt_name); AccelState *current_accel(void); =20 +void accel_init_interfaces(AccelClass *ac, const char *cpu_type); + #ifndef CONFIG_USER_ONLY int accel_init_machine(AccelState *accel, MachineState *ms); =20 diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h new file mode 100644 index 0000000000..6102d2f80d --- /dev/null +++ b/include/sysemu/accel-ops.h @@ -0,0 +1,45 @@ +/* + * Accelerator OPS, used for cpus.c module + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ACCEL_OPS_H +#define ACCEL_OPS_H + +#include "qom/object.h" + +#define ACCEL_OPS_SUFFIX "-ops" +#define TYPE_ACCEL_OPS "accel" ACCEL_OPS_SUFFIX +#define ACCEL_OPS_NAME(name) (name "-" TYPE_ACCEL_OPS) + +typedef struct AccelOpsClass AccelOpsClass; +DECLARE_CLASS_CHECKERS(AccelOpsClass, ACCEL_OPS, TYPE_ACCEL_OPS) + +/* cpus.c operations interface */ +struct AccelOpsClass { + /*< private >*/ + ObjectClass parent_class; + /*< public >*/ + + /* initialization function called when accel is chosen */ + void (*ops_init)(AccelOpsClass *ops); + + void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */ + void (*kick_vcpu_thread)(CPUState *cpu); + + void (*synchronize_post_reset)(CPUState *cpu); + void (*synchronize_post_init)(CPUState *cpu); + void (*synchronize_state)(CPUState *cpu); + void (*synchronize_pre_loadvm)(CPUState *cpu); + + void (*handle_interrupt)(CPUState *cpu, int mask); + + int64_t (*get_virtual_clock)(void); + int64_t (*get_elapsed_ticks)(void); +}; + +#endif /* ACCEL_OPS_H */ diff --git a/include/sysemu/cpus.h b/include/sysemu/cpus.h index e8156728c6..2cd74392e0 100644 --- a/include/sysemu/cpus.h +++ b/include/sysemu/cpus.h @@ -2,30 +2,14 @@ #define QEMU_CPUS_H =20 #include "qemu/timer.h" +#include "sysemu/accel-ops.h" =20 -/* cpus.c */ +/* register accel-specific operations */ +void cpus_register_accel(const AccelOpsClass *i); =20 -/* CPU execution threads */ +/* accel/dummy-cpus.c */ =20 -typedef struct CpusAccel { - void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY */ - void (*kick_vcpu_thread)(CPUState *cpu); - - void (*synchronize_post_reset)(CPUState *cpu); - void (*synchronize_post_init)(CPUState *cpu); - void (*synchronize_state)(CPUState *cpu); - void (*synchronize_pre_loadvm)(CPUState *cpu); - - void (*handle_interrupt)(CPUState *cpu, int mask); - - int64_t (*get_virtual_clock)(void); - int64_t (*get_elapsed_ticks)(void); -} CpusAccel; - -/* register accel-specific cpus interface implementation */ -void cpus_register_accel(const CpusAccel *i); - -/* Create a dummy vcpu for CpusAccel->create_vcpu_thread */ +/* Create a dummy vcpu for AccelOpsClass->create_vcpu_thread */ void dummy_start_vcpu_thread(CPUState *); =20 /* interface available for cpus accelerator threads */ diff --git a/linux-user/main.c b/linux-user/main.c index 1825d2b835..54e59fce3a 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -708,6 +708,7 @@ int main(int argc, char **argv, char **envp) AccelClass *ac =3D ACCEL_GET_CLASS(current_accel()); =20 ac->init_machine(NULL); + accel_init_interfaces(ac, cpu_type); } cpu =3D cpu_create(cpu_type); env =3D cpu->env_ptr; diff --git a/softmmu/cpus.c b/softmmu/cpus.c index e46ac68ad0..659617e7ef 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -127,7 +127,7 @@ void hw_error(const char *fmt, ...) /* * The chosen accelerator is supposed to register this. */ -static const CpusAccel *cpus_accel; +static const AccelOpsClass *cpus_accel; =20 void cpu_synchronize_all_states(void) { @@ -593,11 +593,11 @@ void cpu_remove_sync(CPUState *cpu) qemu_mutex_lock_iothread(); } =20 -void cpus_register_accel(const CpusAccel *ca) +void cpus_register_accel(const AccelOpsClass *ops) { - assert(ca !=3D NULL); - assert(ca->create_vcpu_thread !=3D NULL); /* mandatory */ - cpus_accel =3D ca; + assert(ops !=3D NULL); + assert(ops->create_vcpu_thread !=3D NULL); /* mandatory */ + cpus_accel =3D ops; } =20 void qemu_init_vcpu(CPUState *cpu) @@ -617,7 +617,7 @@ void qemu_init_vcpu(CPUState *cpu) cpu_address_space_init(cpu, 0, "cpu-memory", cpu->memory); } =20 - /* accelerators all implement the CpusAccel interface */ + /* accelerators all implement the AccelOpsClass */ g_assert(cpus_accel !=3D NULL && cpus_accel->create_vcpu_thread !=3D N= ULL); cpus_accel->create_vcpu_thread(cpu); =20 diff --git a/softmmu/vl.c b/softmmu/vl.c index bc20c526d2..8d65058ef1 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -2558,7 +2558,7 @@ static bool object_create_initial(const char *type, Q= emuOpts *opts) } =20 /* Memory allocation by backends needs to be done - * after configure_accelerator() (due to the tcg_enabled() + * after do_configure_accelerator() (due to the tcg_enabled() * checks at memory_region_init_*()). * * Also, allocation of large amounts of memory may delay @@ -4186,7 +4186,7 @@ void qemu_init(int argc, char **argv, char **envp) * * Machine compat properties: object_set_machine_compat_props(). * Accelerator compat props: object_set_accelerator_compat_props(), - * called from configure_accelerator(). + * called from do_configure_accelerator(). */ =20 if (!qtest_enabled() && machine_class->deprecation_reason) { @@ -4322,6 +4322,10 @@ void qemu_init(int argc, char **argv, char **envp) current_machine->cpu_type =3D parse_cpu_option(cpu_option); } =20 + /* cpu has been chosen, initialize the accel interfaces */ + accel_init_interfaces(ACCEL_GET_CLASS(current_machine->accelerator), + current_machine->cpu_type); + if (current_machine->ram_memdev_id) { Object *backend; ram_addr_t backend_size; diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index d7f4bb44a7..ec3c426223 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -364,9 +364,6 @@ static int hax_accel_init(MachineState *ms) !ret ? "working" : "not working", !ret ? "fast virt" : "emulation"); } - if (ret =3D=3D 0) { - cpus_register_accel(&hax_cpus); - } return ret; } =20 diff --git a/target/i386/hax/hax-cpus.c b/target/i386/hax/hax-cpus.c index f72c85bd49..2f8424388d 100644 --- a/target/i386/hax/hax-cpus.c +++ b/target/i386/hax/hax-cpus.c @@ -74,12 +74,27 @@ static void hax_start_vcpu_thread(CPUState *cpu) #endif } =20 -const CpusAccel hax_cpus =3D { - .create_vcpu_thread =3D hax_start_vcpu_thread, - .kick_vcpu_thread =3D hax_kick_vcpu_thread, +static void hax_cpus_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 - .synchronize_post_reset =3D hax_cpu_synchronize_post_reset, - .synchronize_post_init =3D hax_cpu_synchronize_post_init, - .synchronize_state =3D hax_cpu_synchronize_state, - .synchronize_pre_loadvm =3D hax_cpu_synchronize_pre_loadvm, + ops->create_vcpu_thread =3D hax_start_vcpu_thread; + ops->kick_vcpu_thread =3D hax_kick_vcpu_thread; + + ops->synchronize_post_reset =3D hax_cpu_synchronize_post_reset; + ops->synchronize_post_init =3D hax_cpu_synchronize_post_init; + ops->synchronize_state =3D hax_cpu_synchronize_state; + ops->synchronize_pre_loadvm =3D hax_cpu_synchronize_pre_loadvm; +}; +static const TypeInfo hax_cpus_type_info =3D { + .name =3D ACCEL_OPS_NAME("hax"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D hax_cpus_class_init, + .abstract =3D true, }; +static void hax_cpus_register_types(void) +{ + type_register_static(&hax_cpus_type_info); +} +type_init(hax_cpus_register_types); diff --git a/target/i386/hax/hax-cpus.h b/target/i386/hax/hax-cpus.h index ee8ab7a631..c7698519cd 100644 --- a/target/i386/hax/hax-cpus.h +++ b/target/i386/hax/hax-cpus.h @@ -12,8 +12,6 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel hax_cpus; - #include "hax-interface.h" #include "hax-i386.h" =20 diff --git a/target/i386/hvf/hvf-cpus.c b/target/i386/hvf/hvf-cpus.c index 817b3d7452..dd022a84c4 100644 --- a/target/i386/hvf/hvf-cpus.c +++ b/target/i386/hvf/hvf-cpus.c @@ -121,11 +121,26 @@ static void hvf_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); } =20 -const CpusAccel hvf_cpus =3D { - .create_vcpu_thread =3D hvf_start_vcpu_thread, +static void hvf_cpus_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 - .synchronize_post_reset =3D hvf_cpu_synchronize_post_reset, - .synchronize_post_init =3D hvf_cpu_synchronize_post_init, - .synchronize_state =3D hvf_cpu_synchronize_state, - .synchronize_pre_loadvm =3D hvf_cpu_synchronize_pre_loadvm, + ops->create_vcpu_thread =3D hvf_start_vcpu_thread; + + ops->synchronize_post_reset =3D hvf_cpu_synchronize_post_reset; + ops->synchronize_post_init =3D hvf_cpu_synchronize_post_init; + ops->synchronize_state =3D hvf_cpu_synchronize_state; + ops->synchronize_pre_loadvm =3D hvf_cpu_synchronize_pre_loadvm; +}; +static const TypeInfo hvf_cpus_type_info =3D { + .name =3D ACCEL_OPS_NAME("hvf"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D hvf_cpus_class_init, + .abstract =3D true, }; +static void hvf_cpus_register_types(void) +{ + type_register_static(&hvf_cpus_type_info); +} +type_init(hvf_cpus_register_types); diff --git a/target/i386/hvf/hvf-cpus.h b/target/i386/hvf/hvf-cpus.h index ced31b82c0..8f992da168 100644 --- a/target/i386/hvf/hvf-cpus.h +++ b/target/i386/hvf/hvf-cpus.h @@ -12,8 +12,6 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel hvf_cpus; - int hvf_init_vcpu(CPUState *); int hvf_vcpu_exec(CPUState *); void hvf_cpu_synchronize_state(CPUState *); diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index ffc9efa40f..bd94bb5243 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -887,7 +887,6 @@ static int hvf_accel_init(MachineState *ms) =20 hvf_state =3D s; memory_listener_register(&hvf_memory_listener, &address_space_memory); - cpus_register_accel(&hvf_cpus); return 0; } =20 diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index ee6b606194..90adae9af7 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -1642,8 +1642,6 @@ static int whpx_accel_init(MachineState *ms) =20 whpx_memory_init(); =20 - cpus_register_accel(&whpx_cpus); - printf("Windows Hypervisor Platform accelerator is operational\n"); return 0; =20 diff --git a/target/i386/whpx/whpx-cpus.c b/target/i386/whpx/whpx-cpus.c index d9bd5a2d36..8e82974de7 100644 --- a/target/i386/whpx/whpx-cpus.c +++ b/target/i386/whpx/whpx-cpus.c @@ -85,12 +85,27 @@ static void whpx_kick_vcpu_thread(CPUState *cpu) } } =20 -const CpusAccel whpx_cpus =3D { - .create_vcpu_thread =3D whpx_start_vcpu_thread, - .kick_vcpu_thread =3D whpx_kick_vcpu_thread, +static void whpx_cpus_class_init(ObjectClass *oc, void *data) +{ + AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 - .synchronize_post_reset =3D whpx_cpu_synchronize_post_reset, - .synchronize_post_init =3D whpx_cpu_synchronize_post_init, - .synchronize_state =3D whpx_cpu_synchronize_state, - .synchronize_pre_loadvm =3D whpx_cpu_synchronize_pre_loadvm, + ops->create_vcpu_thread =3D whpx_start_vcpu_thread; + ops->kick_vcpu_thread =3D whpx_kick_vcpu_thread; + + ops->synchronize_post_reset =3D whpx_cpu_synchronize_post_reset; + ops->synchronize_post_init =3D whpx_cpu_synchronize_post_init; + ops->synchronize_state =3D whpx_cpu_synchronize_state; + ops->synchronize_pre_loadvm =3D whpx_cpu_synchronize_pre_loadvm; +}; +static const TypeInfo whpx_cpus_type_info =3D { + .name =3D ACCEL_OPS_NAME("whpx"), + + .parent =3D TYPE_ACCEL_OPS, + .class_init =3D whpx_cpus_class_init, + .abstract =3D true, }; +static void whpx_cpus_register_types(void) +{ + type_register_static(&whpx_cpus_type_info); +} +type_init(whpx_cpus_register_types); diff --git a/target/i386/whpx/whpx-cpus.h b/target/i386/whpx/whpx-cpus.h index bdb367d1d0..2dee6d61ea 100644 --- a/target/i386/whpx/whpx-cpus.h +++ b/target/i386/whpx/whpx-cpus.h @@ -12,8 +12,6 @@ =20 #include "sysemu/cpus.h" =20 -extern const CpusAccel whpx_cpus; - int whpx_init_vcpu(CPUState *cpu); int whpx_vcpu_exec(CPUState *cpu); void whpx_destroy_vcpu(CPUState *cpu); --=20 2.26.2 From nobody Mon May 6 20:54:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1606430624; cv=none; d=zohomail.com; s=zohoarc; b=UXHPfGLCL7Tu916LF691tASnOLjW2VafAm7KejZDQ7oOpJSuPBGxzDZWjv6Y/zn72bOqn9cebRe7s3pp4n9t663uC6E5eyfMHmB7NZN6ii5JdK0+I/BLSBYBCpBctTmxjmkvr1qHPtsWkTV0GU5TZdoUS1p7Qs6iq/Bk1MkMYfQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606430624; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uQcUR64YfOBuFaNCN/RWOKvNagB63zKtuErbkVBASWM=; b=Ww1bSsXQhYSLuZ+H3GVLGanZTZh9Duav06s5ZwAGyDihw5AP70u8ljUnnuyzpmrjnxz1jG+houm9wOPV2Uv0lK8abGCsfCqTAhu7Jp5EszNbLtHQFT8lNGDVGOh/VkiYrFsLsqOngEjm+yl7ogG7ZtQq2oZoeKdkBiW4Q9ojPiE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606430624185510.58719458218013; Thu, 26 Nov 2020 14:43:44 -0800 (PST) Received: from localhost ([::1]:55148 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kiPzL-00058S-6o for importer@patchew.org; Thu, 26 Nov 2020 17:43:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44084) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoe-0001Wr-IA for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:40 -0500 Received: from mx2.suse.de ([195.135.220.15]:44686) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPoY-0003Ie-6x for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:40 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 8049EAF43; Thu, 26 Nov 2020 22:32:31 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC v6 10/11] accel: introduce AccelCPUClass extending CPUClass Date: Thu, 26 Nov 2020 23:32:17 +0100 Message-Id: <20201126223218.31480-11-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201126223218.31480-1-cfontana@suse.de> References: <20201126223218.31480-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" add a new optional interface to CPUClass, which allows accelerators to extend the CPUClass with additional accelerator-specific initializations. Signed-off-by: Claudio Fontana --- MAINTAINERS | 1 + accel/accel-common.c | 43 +++++++++++++++++++++++++++++++++++++ include/hw/core/accel-cpu.h | 28 ++++++++++++++++++++++++ include/hw/core/cpu.h | 4 ++++ 4 files changed, 76 insertions(+) create mode 100644 include/hw/core/accel-cpu.h diff --git a/MAINTAINERS b/MAINTAINERS index df64a0d190..b99526e491 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -435,6 +435,7 @@ R: Paolo Bonzini S: Maintained F: include/qemu/accel.h F: include/sysemu/accel-ops.h +F: include/hw/core/accel-cpu.h F: accel/accel-*.c F: accel/Makefile.objs F: accel/stubs/Makefile.objs diff --git a/accel/accel-common.c b/accel/accel-common.c index 3910b7dbe0..06afee982e 100644 --- a/accel/accel-common.c +++ b/accel/accel-common.c @@ -26,6 +26,9 @@ #include "qemu/osdep.h" #include "qemu/accel.h" =20 +#include "cpu.h" +#include "hw/core/accel-cpu.h" + #ifndef CONFIG_USER_ONLY #include "accel-softmmu.h" #endif /* !CONFIG_USER_ONLY */ @@ -46,16 +49,56 @@ AccelClass *accel_find(const char *opt_name) return ac; } =20 +static void accel_init_cpu_int_aux(ObjectClass *klass, void *opaque) +{ + CPUClass *cc =3D CPU_CLASS(klass); + AccelCPUClass *accel_cpu_interface =3D opaque; + + cc->accel_cpu_interface =3D accel_cpu_interface; + if (accel_cpu_interface->cpu_class_init) { + accel_cpu_interface->cpu_class_init(cc); + } +} + +/* initialize the arch-specific accel CpuClass interfaces */ +static void accel_init_cpu_interfaces(AccelClass *ac, const char *cpu_type) +{ + const char *ac_name; /* AccelClass name */ + char *acc_name; /* AccelCPUClass name */ + ObjectClass *acc; /* AccelCPUClass */ + + ac_name =3D object_class_get_name(OBJECT_CLASS(ac)); + g_assert(ac_name !=3D NULL); + + acc_name =3D g_strdup_printf("%s-%s", ac_name, CPU_RESOLVING_TYPE); + acc =3D object_class_by_name(acc_name); + g_free(acc_name); + + if (acc) { + object_class_foreach(accel_init_cpu_int_aux, cpu_type, false, acc); + } +} + void accel_init_interfaces(AccelClass *ac, const char *cpu_type) { #ifndef CONFIG_USER_ONLY accel_init_ops_interfaces(ac); #endif /* !CONFIG_USER_ONLY */ + + accel_init_cpu_interfaces(ac, cpu_type); } =20 +static const TypeInfo accel_cpu_type =3D { + .name =3D TYPE_ACCEL_CPU, + .parent =3D TYPE_OBJECT, + .abstract =3D true, + .class_size =3D sizeof(AccelCPUClass), +}; + static void register_accel_types(void) { type_register_static(&accel_type); + type_register_static(&accel_cpu_type); } =20 type_init(register_accel_types); diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h new file mode 100644 index 0000000000..380e1c7436 --- /dev/null +++ b/include/hw/core/accel-cpu.h @@ -0,0 +1,28 @@ +/* + * Accelerator interface, specializes CPUClass + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef ACCEL_CPU_H +#define ACCEL_CPU_H + +struct AccelCPUClass { + /*< private >*/ + ObjectClass parent_class; + /*< public >*/ + + void (*cpu_class_init)(CPUClass *cc); + void (*cpu_instance_init)(CPUState *cpu); + void (*cpu_realizefn)(CPUState *cpu, Error **errp); +}; + +#define TYPE_ACCEL_CPU "accel-" CPU_RESOLVING_TYPE +#define ACCEL_CPU_NAME(name) (name "-" TYPE_ACCEL_CPU) +typedef struct AccelCPUClass AccelCPUClass; +DECLARE_CLASS_CHECKERS(AccelCPUClass, ACCEL_CPU, TYPE_ACCEL_CPU) + +#endif /* ACCEL_CPU_H */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 3d92c967ff..75eb1d8199 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -76,6 +76,8 @@ typedef struct CPUWatchpoint CPUWatchpoint; =20 struct TranslationBlock; =20 +struct AccelCPUClass; + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an @@ -227,6 +229,8 @@ struct CPUClass { /* Keep non-pointer data at the end to minimize holes. */ int gdb_num_core_regs; bool gdb_stop_before_watchpoint; + + struct AccelCPUClass *accel_cpu_interface; }; =20 /* --=20 2.26.2 From nobody Mon May 6 20:54:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1606430500; cv=none; d=zohomail.com; s=zohoarc; b=QkaQPufjnT0Huvtypf0tLDnf79d99304aN8Z0oIAPanRUgnU0dXKvWFM4mKYQQjBc9uRZvzBqvvLOT025QXsBfzo9Zh36C7QPjaJMgOtLdjlF54FQ57NOw6mEMGtJiUJHOfYDNBSQxmt+lNSDdw81ooFEw4jWvPj1XpO7DQnvwk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606430500; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VgYLPumOywz+514IWsYrJ/xxhsqYRaQHnP20dw86Kd4=; b=dt1p7SiU0ssj7A2QSW4QUolwacBnRElTlNByDmIYVfqVHsjn1+Qa+Pphk1d47SjzjC5ilah7uVZ8Ki7inBvB1iR4ZaAC/7ihpmPTi65RC9AiURhzUiWIgILtkvubXYh5VkpUhpBwngDSmj56m4eX22tjig0gjLWnUSego1TSB9U= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160643050001654.09964134294137; Thu, 26 Nov 2020 14:41:40 -0800 (PST) Received: from localhost ([::1]:50900 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kiPxK-0003Lk-L5 for importer@patchew.org; Thu, 26 Nov 2020 17:41:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:44184) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPou-0001mj-JY for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:57 -0500 Received: from mx2.suse.de ([195.135.220.15]:44688) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kiPom-0003J9-59 for qemu-devel@nongnu.org; Thu, 26 Nov 2020 17:32:56 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 6C617ADE1; Thu, 26 Nov 2020 22:32:32 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC v6 11/11] i386: split cpu accelerators from cpu.c, using AccelCPUClass Date: Thu, 26 Nov 2020 23:32:18 +0100 Message-Id: <20201126223218.31480-12-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201126223218.31480-1-cfontana@suse.de> References: <20201126223218.31480-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Olaf Hering , "Emilio G . Cota" , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" i386 is the first user of AccelCPUClass, allowing to split cpu.c into: cpu.c cpuid and common x86 cpu functionality host-cpu.c host x86 cpu functions and "host" cpu type kvm/cpu.c KVM x86 AccelCPUClass hvf/cpu.c HVF x86 AccelCPUClass tcg/cpu.c TCG x86 AccelCPUClass Signed-off-by: Claudio Fontana --- MAINTAINERS | 2 +- hw/i386/pc_piix.c | 1 + target/i386/cpu.c | 386 ++++-------------------------------- target/i386/cpu.h | 20 +- target/i386/host-cpu.c | 198 ++++++++++++++++++ target/i386/host-cpu.h | 19 ++ target/i386/hvf/cpu.c | 65 ++++++ target/i386/hvf/meson.build | 1 + target/i386/kvm/cpu.c | 148 ++++++++++++++ target/i386/kvm/kvm-cpu.h | 41 ++++ target/i386/kvm/kvm.c | 3 +- target/i386/kvm/meson.build | 7 +- target/i386/meson.build | 8 +- target/i386/tcg-cpu.c | 71 ------- target/i386/tcg-cpu.h | 15 -- target/i386/tcg/cpu.c | 173 ++++++++++++++++ target/i386/tcg/meson.build | 3 +- 17 files changed, 711 insertions(+), 450 deletions(-) create mode 100644 target/i386/host-cpu.c create mode 100644 target/i386/host-cpu.h create mode 100644 target/i386/hvf/cpu.c create mode 100644 target/i386/kvm/cpu.c create mode 100644 target/i386/kvm/kvm-cpu.h delete mode 100644 target/i386/tcg-cpu.c delete mode 100644 target/i386/tcg-cpu.h create mode 100644 target/i386/tcg/cpu.c diff --git a/MAINTAINERS b/MAINTAINERS index b99526e491..c7fff31888 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -336,7 +336,7 @@ M: Paolo Bonzini M: Richard Henderson M: Eduardo Habkost S: Maintained -F: target/i386/ +F: target/i386/tcg/ F: tests/tcg/i386/ F: tests/tcg/x86_64/ F: hw/i386/ diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 13d1628f13..d3f013f3a1 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -64,6 +64,7 @@ #include "hw/hyperv/vmbus-bridge.h" #include "hw/mem/nvdimm.h" #include "hw/i386/acpi-build.h" +#include "kvm/kvm-cpu.h" =20 #define MAX_IDE_BUS 2 =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3462d0143f..27fba3b003 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -22,37 +22,24 @@ #include "qemu/cutils.h" #include "qemu/bitops.h" #include "qemu/qemu-print.h" - #include "cpu.h" -#include "tcg-cpu.h" #include "helper-tcg.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" #include "sysemu/hvf.h" -#include "sysemu/cpus.h" +#include "hw/core/accel-cpu.h" #include "sysemu/xen.h" #include "kvm/kvm_i386.h" #include "sev_i386.h" - -#include "qemu/error-report.h" #include "qemu/module.h" -#include "qemu/option.h" -#include "qemu/config-file.h" -#include "qapi/error.h" #include "qapi/qapi-visit-machine.h" #include "qapi/qapi-visit-run-state.h" #include "qapi/qmp/qdict.h" #include "qapi/qmp/qerror.h" -#include "qapi/visitor.h" #include "qom/qom-qobject.h" -#include "sysemu/arch_init.h" #include "qapi/qapi-commands-machine-target.h" - #include "standard-headers/asm-x86/kvm_para.h" - -#include "sysemu/sysemu.h" -#include "sysemu/tcg.h" #include "hw/qdev-properties.h" #include "hw/i386/topology.h" #ifndef CONFIG_USER_ONLY @@ -594,8 +581,8 @@ static CPUCacheInfo legacy_l3_cache =3D { #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32= K,64K */ =20 -static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, - uint32_t vendor2, uint32_t vendor3) +void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, + uint32_t vendor2, uint32_t vendor3) { int i; for (i =3D 0; i < 4; i++) { @@ -1563,25 +1550,6 @@ void host_cpuid(uint32_t function, uint32_t count, *edx =3D vec[3]; } =20 -void host_vendor_fms(char *vendor, int *family, int *model, int *stepping) -{ - uint32_t eax, ebx, ecx, edx; - - host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); - x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); - - host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); - if (family) { - *family =3D ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); - } - if (model) { - *model =3D ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); - } - if (stepping) { - *stepping =3D eax & 0x0F; - } -} - /* CPU class name definitions: */ =20 /* Return type name for a given CPU model name @@ -1606,10 +1574,6 @@ static char *x86_cpu_class_get_model_name(X86CPUClas= s *cc) strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); } =20 -typedef struct PropValue { - const char *prop, *value; -} PropValue; - typedef struct X86CPUVersionDefinition { X86CPUVersion version; const char *alias; @@ -4106,31 +4070,6 @@ static X86CPUDefinition builtin_x86_defs[] =3D { }, }; =20 -/* KVM-specific features that are automatically added/removed - * from all CPU models when KVM is enabled. - */ -static PropValue kvm_default_props[] =3D { - { "kvmclock", "on" }, - { "kvm-nopiodelay", "on" }, - { "kvm-asyncpf", "on" }, - { "kvm-steal-time", "on" }, - { "kvm-pv-eoi", "on" }, - { "kvmclock-stable-bit", "on" }, - { "x2apic", "on" }, - { "acpi", "off" }, - { "monitor", "off" }, - { "svm", "off" }, - { NULL, NULL }, -}; - -/* TCG-specific defaults that override all CPU models when using TCG - */ -static PropValue tcg_default_props[] =3D { - { "vme", "off" }, - { NULL, NULL }, -}; - - /* * We resolve CPU model aliases using -v1 when using "-machine * none", but this is just for compatibility while libvirt isn't @@ -4172,61 +4111,6 @@ static X86CPUVersion x86_cpu_model_resolve_version(c= onst X86CPUModel *model) return v; } =20 -void x86_cpu_change_kvm_default(const char *prop, const char *value) -{ - PropValue *pv; - for (pv =3D kvm_default_props; pv->prop; pv++) { - if (!strcmp(pv->prop, prop)) { - pv->value =3D value; - break; - } - } - - /* It is valid to call this function only for properties that - * are already present in the kvm_default_props table. - */ - assert(pv->prop); -} - -static bool lmce_supported(void) -{ - uint64_t mce_cap =3D 0; - -#ifdef CONFIG_KVM - if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0)= { - return false; - } -#endif - - return !!(mce_cap & MCG_LMCE_P); -} - -#define CPUID_MODEL_ID_SZ 48 - -/** - * cpu_x86_fill_model_id: - * Get CPUID model ID string from host CPU. - * - * @str should have at least CPUID_MODEL_ID_SZ bytes - * - * The function does NOT add a null terminator to the string - * automatically. - */ -static int cpu_x86_fill_model_id(char *str) -{ - uint32_t eax =3D 0, ebx =3D 0, ecx =3D 0, edx =3D 0; - int i; - - for (i =3D 0; i < 3; i++) { - host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); - memcpy(str + i * 16 + 0, &eax, 4); - memcpy(str + i * 16 + 4, &ebx, 4); - memcpy(str + i * 16 + 8, &ecx, 4); - memcpy(str + i * 16 + 12, &edx, 4); - } - return 0; -} - static Property max_x86_cpu_properties[] =3D { DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, fa= lse), @@ -4249,61 +4133,25 @@ static void max_x86_cpu_class_init(ObjectClass *oc,= void *data) static void max_x86_cpu_initfn(Object *obj) { X86CPU *cpu =3D X86_CPU(obj); - CPUX86State *env =3D &cpu->env; - KVMState *s =3D kvm_state; =20 /* We can't fill the features array here because we don't know yet if * "migratable" is true or false. */ cpu->max_features =3D true; - - if (accel_uses_host_cpuid()) { - char vendor[CPUID_VENDOR_SZ + 1] =3D { 0 }; - char model_id[CPUID_MODEL_ID_SZ + 1] =3D { 0 }; - int family, model, stepping; - - host_vendor_fms(vendor, &family, &model, &stepping); - cpu_x86_fill_model_id(model_id); - - object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abor= t); - object_property_set_int(OBJECT(cpu), "family", family, &error_abor= t); - object_property_set_int(OBJECT(cpu), "model", model, &error_abort); - object_property_set_int(OBJECT(cpu), "stepping", stepping, - &error_abort); - object_property_set_str(OBJECT(cpu), "model-id", model_id, - &error_abort); - - if (kvm_enabled()) { - env->cpuid_min_level =3D - kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); - env->cpuid_min_xlevel =3D - kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); - env->cpuid_min_xlevel2 =3D - kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); - } else { - env->cpuid_min_level =3D - hvf_get_supported_cpuid(0x0, 0, R_EAX); - env->cpuid_min_xlevel =3D - hvf_get_supported_cpuid(0x80000000, 0, R_EAX); - env->cpuid_min_xlevel2 =3D - hvf_get_supported_cpuid(0xC0000000, 0, R_EAX); - } - - if (lmce_supported()) { - object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abo= rt); - } - } else { - object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, - &error_abort); - object_property_set_int(OBJECT(cpu), "family", 6, &error_abort); - object_property_set_int(OBJECT(cpu), "model", 6, &error_abort); - object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort); - object_property_set_str(OBJECT(cpu), "model-id", - "QEMU TCG CPU version " QEMU_HW_VERSION, - &error_abort); - } - object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); + + /* + * these defaults are used for TCG and all other accelerators + * besides KVM and HVF, which overwrite these values + */ + object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, + &error_abort); + object_property_set_int(OBJECT(cpu), "family", 6, &error_abort); + object_property_set_int(OBJECT(cpu), "model", 6, &error_abort); + object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort); + object_property_set_str(OBJECT(cpu), "model-id", + "QEMU TCG CPU version " QEMU_HW_VERSION, + &error_abort); } =20 static const TypeInfo max_x86_cpu_type_info =3D { @@ -4313,31 +4161,6 @@ static const TypeInfo max_x86_cpu_type_info =3D { .class_init =3D max_x86_cpu_class_init, }; =20 -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) -static void host_x86_cpu_class_init(ObjectClass *oc, void *data) -{ - X86CPUClass *xcc =3D X86_CPU_CLASS(oc); - - xcc->host_cpuid_required =3D true; - xcc->ordering =3D 8; - -#if defined(CONFIG_KVM) - xcc->model_description =3D - "KVM processor with all supported host features "; -#elif defined(CONFIG_HVF) - xcc->model_description =3D - "HVF processor with all supported host features "; -#endif -} - -static const TypeInfo host_x86_cpu_type_info =3D { - .name =3D X86_CPU_TYPE_NAME("host"), - .parent =3D X86_CPU_TYPE_NAME("max"), - .class_init =3D host_x86_cpu_class_init, -}; - -#endif - static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) { assert(f->type =3D=3D CPUID_FEATURE_WORD || f->type =3D=3D MSR_FEATURE= _WORD); @@ -5063,7 +4886,7 @@ static uint64_t x86_cpu_get_supported_feature_word(Fe= atureWord w, return r; } =20 -static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) +void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) { PropValue *pv; for (pv =3D props; pv->prop; pv++) { @@ -5110,8 +4933,6 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUMod= el *model) { X86CPUDefinition *def =3D model->cpudef; CPUX86State *env =3D &cpu->env; - const char *vendor; - char host_vendor[CPUID_VENDOR_SZ + 1]; FeatureWord w; =20 /*NOTE: any property set by this function should be returned by @@ -5138,18 +4959,6 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUMo= del *model) /* legacy-cache defaults to 'off' if CPU model provides cache info */ cpu->legacy_cache =3D !def->cache_info; =20 - /* Special cases not set in the X86CPUDefinition structs: */ - /* TODO: in-kernel irqchip for hvf */ - if (kvm_enabled()) { - if (!kvm_irqchip_in_kernel()) { - x86_cpu_change_kvm_default("x2apic", "off"); - } - - x86_cpu_apply_props(cpu, kvm_default_props); - } else if (tcg_enabled()) { - x86_cpu_apply_props(cpu, tcg_default_props); - } - env->features[FEAT_1_ECX] |=3D CPUID_EXT_HYPERVISOR; =20 /* sysenter isn't supported in compatibility mode on AMD, @@ -5159,15 +4968,12 @@ static void x86_cpu_load_model(X86CPU *cpu, X86CPUM= odel *model) * KVM's sysenter/syscall emulation in compatibility mode and * when doing cross vendor migration */ - vendor =3D def->vendor; - if (accel_uses_host_cpuid()) { - uint32_t ebx =3D 0, ecx =3D 0, edx =3D 0; - host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); - x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx); - vendor =3D host_vendor; - } =20 - object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); + /* + * vendor property is set here but then overloaded with the + * host cpu vendor for KVM and HVF. + */ + object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abo= rt); =20 x86_cpu_apply_version_props(cpu, model); =20 @@ -6192,53 +5998,12 @@ static void x86_cpu_apic_realize(X86CPU *cpu, Error= **errp) apic_mmio_map_once =3D true; } } - -static void x86_cpu_machine_done(Notifier *n, void *unused) -{ - X86CPU *cpu =3D container_of(n, X86CPU, machine_done); - MemoryRegion *smram =3D - (MemoryRegion *) object_resolve_path("/machine/smram", NULL); - - if (smram) { - cpu->smram =3D g_new(MemoryRegion, 1); - memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram", - smram, 0, 4 * GiB); - memory_region_set_enabled(cpu->smram, true); - memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smra= m, 1); - } -} #else static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp) { } #endif =20 -/* Note: Only safe for use on x86(-64) hosts */ -static uint32_t x86_host_phys_bits(void) -{ - uint32_t eax; - uint32_t host_phys_bits; - - host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); - if (eax >=3D 0x80000008) { - host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); - /* Note: According to AMD doc 25481 rev 2.34 they have a field - * at 23:16 that can specify a maximum physical address bits for - * the guest that can override this value; but I've not seen - * anything with that set. - */ - host_phys_bits =3D eax & 0xff; - } else { - /* It's an odd 64 bit machine that doesn't have the leaf for - * physical address bits; fall back to 36 that's most older - * Intel. - */ - host_phys_bits =3D 36; - } - - return host_phys_bits; -} - static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t valu= e) { if (*min < value) { @@ -6515,33 +6280,22 @@ static void x86_cpu_filter_features(X86CPU *cpu, bo= ol verbose) static void x86_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); + CPUClass *cc =3D CPU_GET_CLASS(cs); X86CPU *cpu =3D X86_CPU(dev); X86CPUClass *xcc =3D X86_CPU_GET_CLASS(dev); CPUX86State *env =3D &cpu->env; Error *local_err =3D NULL; static bool ht_warned; =20 - if (xcc->host_cpuid_required) { - if (!accel_uses_host_cpuid()) { - g_autofree char *name =3D x86_cpu_class_get_model_name(xcc); - error_setg(&local_err, "CPU model '%s' requires KVM", name); - goto out; - } + /* The accelerator realizefn needs to be called first. */ + if (cc->accel_cpu_interface) { + cc->accel_cpu_interface->cpu_realizefn(cs, errp); } =20 - if (cpu->max_features && accel_uses_host_cpuid()) { - if (enable_cpu_pm) { - host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, - &cpu->mwait.ecx, &cpu->mwait.edx); - env->features[FEAT_1_ECX] |=3D CPUID_EXT_MONITOR; - if (kvm_enabled() && kvm_has_waitpkg()) { - env->features[FEAT_7_0_ECX] |=3D CPUID_7_0_ECX_WAITPKG; - } - } - if (kvm_enabled() && cpu->ucode_rev =3D=3D 0) { - cpu->ucode_rev =3D kvm_arch_get_supported_msr_feature(kvm_stat= e, - MSR_IA32_U= CODE_REV); - } + if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { + g_autofree char *name =3D x86_cpu_class_get_model_name(xcc); + error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); + goto out; } =20 if (cpu->ucode_rev =3D=3D 0) { @@ -6593,39 +6347,7 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) * consumer AMD devices but nothing else. */ if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { - if (accel_uses_host_cpuid()) { - uint32_t host_phys_bits =3D x86_host_phys_bits(); - static bool warned; - - /* Print a warning if the user set it to a value that's not the - * host value. - */ - if (cpu->phys_bits !=3D host_phys_bits && cpu->phys_bits !=3D = 0 && - !warned) { - warn_report("Host physical bits (%u)" - " does not match phys-bits property (%u)", - host_phys_bits, cpu->phys_bits); - warned =3D true; - } - - if (cpu->host_phys_bits) { - /* The user asked for us to use the host physical bits */ - cpu->phys_bits =3D host_phys_bits; - if (cpu->host_phys_bits_limit && - cpu->phys_bits > cpu->host_phys_bits_limit) { - cpu->phys_bits =3D cpu->host_phys_bits_limit; - } - } - - if (cpu->phys_bits && - (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || - cpu->phys_bits < 32)) { - error_setg(errp, "phys-bits should be between 32 and %u " - " (but is %u)", - TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bi= ts); - return; - } - } else { + if (!accel_uses_host_cpuid()) { if (cpu->phys_bits && cpu->phys_bits !=3D TCG_PHYS_ADDR_BITS) { error_setg(errp, "TCG only supports phys-bits=3D%u", TCG_PHYS_ADDR_BITS); @@ -6633,8 +6355,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error= **errp) } } /* 0 means it was not explicitly set by the user (or by machine - * compat_props or by the host code above). In this case, the defa= ult - * is the value used by TCG (40). + * compat_props or by the host code in host-cpu.c). + * In this case, the default is the value used by TCG (40). */ if (cpu->phys_bits =3D=3D 0) { cpu->phys_bits =3D TCG_PHYS_ADDR_BITS; @@ -6704,33 +6426,6 @@ static void x86_cpu_realizefn(DeviceState *dev, Erro= r **errp) =20 mce_init(cpu); =20 -#ifndef CONFIG_USER_ONLY - if (tcg_enabled()) { - cpu->cpu_as_mem =3D g_new(MemoryRegion, 1); - cpu->cpu_as_root =3D g_new(MemoryRegion, 1); - - /* Outer container... */ - memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull); - memory_region_set_enabled(cpu->cpu_as_root, true); - - /* ... with two regions inside: normal system memory with low - * priority, and... - */ - memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory", - get_system_memory(), 0, ~0ull); - memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_= as_mem, 0); - memory_region_set_enabled(cpu->cpu_as_mem, true); - - cs->num_ases =3D 2; - cpu_address_space_init(cs, 0, "cpu-memory", cs->memory); - cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root); - - /* ... SMRAM with higher priority, linked from /machine/smram. */ - cpu->machine_done.notify =3D x86_cpu_machine_done; - qemu_add_machine_init_done_notifier(&cpu->machine_done); - } -#endif - qemu_init_vcpu(cs); =20 /* @@ -6936,6 +6631,8 @@ static void x86_cpu_initfn(Object *obj) { X86CPU *cpu =3D X86_CPU(obj); X86CPUClass *xcc =3D X86_CPU_GET_CLASS(obj); + CPUClass *cc =3D CPU_CLASS(xcc); + CPUX86State *env =3D &cpu->env; FeatureWord w; =20 @@ -6992,6 +6689,11 @@ static void x86_cpu_initfn(Object *obj) if (xcc->model) { x86_cpu_load_model(cpu, xcc->model); } + + /* if required, do the accelerator-specific cpu initialization */ + if (cc->accel_cpu_interface) { + cc->accel_cpu_interface->cpu_instance_init(CPU(obj)); + } } =20 static int64_t x86_cpu_get_arch_id(CPUState *cs) @@ -7248,11 +6950,6 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) cc->class_by_name =3D x86_cpu_class_by_name; cc->parse_features =3D x86_cpu_parse_featurestr; cc->has_work =3D x86_cpu_has_work; - -#ifdef CONFIG_TCG - tcg_cpu_common_class_init(cc); -#endif /* CONFIG_TCG */ - cc->dump_state =3D x86_cpu_dump_state; cc->set_pc =3D x86_cpu_set_pc; cc->gdb_read_register =3D x86_cpu_gdb_read_register; @@ -7357,9 +7054,6 @@ static void x86_cpu_register_types(void) } type_register_static(&max_x86_cpu_type_info); type_register_static(&x86_base_cpu_type_info); -#if defined(CONFIG_KVM) || defined(CONFIG_HVF) - type_register_static(&host_x86_cpu_type_info); -#endif } =20 type_init(x86_cpu_register_types) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a0d64613dc..b3e39fc631 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1905,13 +1905,20 @@ int cpu_x86_signal_handler(int host_signum, void *p= info, void *puc); =20 /* cpu.c */ +void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, + uint32_t vendor2, uint32_t vendor3); +typedef struct PropValue { + const char *prop, *value; +} PropValue; +void x86_cpu_apply_props(X86CPU *cpu, PropValue *props); + +/* cpu.c other functions (cpuid) */ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx); void cpu_clear_apic_feature(CPUX86State *env); void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx= ); -void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); =20 /* helper.c */ void x86_cpu_set_a20(X86CPU *cpu, int a20_state); @@ -2111,17 +2118,6 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAcce= ss access); void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, TPRAccess access); =20 - -/* Change the value of a KVM-specific default - * - * If value is NULL, no default will be set and the original - * value from the CPU model table will be kept. - * - * It is valid to call this function only for properties that - * are already present in the kvm_default_props table. - */ -void x86_cpu_change_kvm_default(const char *prop, const char *value); - /* Special values for X86CPUVersion: */ =20 /* Resolve to latest CPU version */ diff --git a/target/i386/host-cpu.c b/target/i386/host-cpu.c new file mode 100644 index 0000000000..3ce2bc9a84 --- /dev/null +++ b/target/i386/host-cpu.c @@ -0,0 +1,198 @@ +/* + * x86 host CPU functions, and "host" cpu type initialization + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "host-cpu.h" +#include "qapi/error.h" +#include "sysemu/sysemu.h" + +/* Note: Only safe for use on x86(-64) hosts */ +static uint32_t host_cpu_phys_bits(void) +{ + uint32_t eax; + uint32_t host_phys_bits; + + host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL); + if (eax >=3D 0x80000008) { + host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL); + /* + * Note: According to AMD doc 25481 rev 2.34 they have a field + * at 23:16 that can specify a maximum physical address bits for + * the guest that can override this value; but I've not seen + * anything with that set. + */ + host_phys_bits =3D eax & 0xff; + } else { + /* + * It's an odd 64 bit machine that doesn't have the leaf for + * physical address bits; fall back to 36 that's most older + * Intel. + */ + host_phys_bits =3D 36; + } + + return host_phys_bits; +} + +static void host_cpu_enable_cpu_pm(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + + host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx, + &cpu->mwait.ecx, &cpu->mwait.edx); + env->features[FEAT_1_ECX] |=3D CPUID_EXT_MONITOR; +} + +static uint32_t host_cpu_adjust_phys_bits(X86CPU *cpu, Error **errp) +{ + uint32_t host_phys_bits =3D host_cpu_phys_bits(); + uint32_t phys_bits =3D cpu->phys_bits; + static bool warned; + + /* + * Print a warning if the user set it to a value that's not the + * host value. + */ + if (phys_bits !=3D host_phys_bits && phys_bits !=3D 0 && + !warned) { + warn_report("Host physical bits (%u)" + " does not match phys-bits property (%u)", + host_phys_bits, phys_bits); + warned =3D true; + } + + if (cpu->host_phys_bits) { + /* The user asked for us to use the host physical bits */ + phys_bits =3D host_phys_bits; + if (cpu->host_phys_bits_limit && + phys_bits > cpu->host_phys_bits_limit) { + phys_bits =3D cpu->host_phys_bits_limit; + } + } + + if (phys_bits && + (phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || + phys_bits < 32)) { + error_setg(errp, "phys-bits should be between 32 and %u " + " (but is %u)", + TARGET_PHYS_ADDR_SPACE_BITS, phys_bits); + } + + return phys_bits; +} + +void host_cpu_realizefn(CPUState *cs, Error **errp) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + if (cpu->max_features && enable_cpu_pm) { + host_cpu_enable_cpu_pm(cpu); + } + if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { + cpu->phys_bits =3D host_cpu_adjust_phys_bits(cpu, errp); + } +} + +#define CPUID_MODEL_ID_SZ 48 +/** + * cpu_x86_fill_model_id: + * Get CPUID model ID string from host CPU. + * + * @str should have at least CPUID_MODEL_ID_SZ bytes + * + * The function does NOT add a null terminator to the string + * automatically. + */ +static int host_cpu_fill_model_id(char *str) +{ + uint32_t eax =3D 0, ebx =3D 0, ecx =3D 0, edx =3D 0; + int i; + + for (i =3D 0; i < 3; i++) { + host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); + memcpy(str + i * 16 + 0, &eax, 4); + memcpy(str + i * 16 + 4, &ebx, 4); + memcpy(str + i * 16 + 8, &ecx, 4); + memcpy(str + i * 16 + 12, &edx, 4); + } + return 0; +} + +void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepp= ing) +{ + uint32_t eax, ebx, ecx, edx; + + host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); + x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); + + host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); + if (family) { + *family =3D ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); + } + if (model) { + *model =3D ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); + } + if (stepping) { + *stepping =3D eax & 0x0F; + } +} + +void host_cpu_instance_init(X86CPU *cpu) +{ + uint32_t ebx =3D 0, ecx =3D 0, edx =3D 0; + char vendor[CPUID_VENDOR_SZ + 1]; + + host_cpuid(0, 0, NULL, &ebx, &ecx, &edx); + x86_cpu_vendor_words2str(vendor, ebx, edx, ecx); + + object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); +} + +void host_cpu_max_instance_init(X86CPU *cpu) +{ + char vendor[CPUID_VENDOR_SZ + 1] =3D { 0 }; + char model_id[CPUID_MODEL_ID_SZ + 1] =3D { 0 }; + int family, model, stepping; + + host_cpu_vendor_fms(vendor, &family, &model, &stepping); + host_cpu_fill_model_id(model_id); + + object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort); + object_property_set_int(OBJECT(cpu), "family", family, &error_abort); + object_property_set_int(OBJECT(cpu), "model", model, &error_abort); + object_property_set_int(OBJECT(cpu), "stepping", stepping, + &error_abort); + object_property_set_str(OBJECT(cpu), "model-id", model_id, + &error_abort); +} + +static void host_cpu_class_init(ObjectClass *oc, void *data) +{ + X86CPUClass *xcc =3D X86_CPU_CLASS(oc); + + xcc->host_cpuid_required =3D true; + xcc->ordering =3D 8; + xcc->model_description =3D + g_strdup_printf("processor with all supported host features "); +} + +static const TypeInfo host_cpu_type_info =3D { + .name =3D X86_CPU_TYPE_NAME("host"), + .parent =3D X86_CPU_TYPE_NAME("max"), + .class_init =3D host_cpu_class_init, +}; + +static void host_cpu_type_init(void) +{ + type_register_static(&host_cpu_type_info); +} + +type_init(host_cpu_type_init); diff --git a/target/i386/host-cpu.h b/target/i386/host-cpu.h new file mode 100644 index 0000000000..d1f2644422 --- /dev/null +++ b/target/i386/host-cpu.h @@ -0,0 +1,19 @@ +/* + * x86 host CPU type initialization and host CPU functions + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef HOST_CPU_H +#define HOST_CPU_H + +void host_cpu_instance_init(X86CPU *cpu); +void host_cpu_max_instance_init(X86CPU *cpu); +void host_cpu_realizefn(CPUState *cs, Error **errp); + +void host_cpu_vendor_fms(char *vendor, int *family, int *model, int *stepp= ing); + +#endif /* HOST_CPU_H */ diff --git a/target/i386/hvf/cpu.c b/target/i386/hvf/cpu.c new file mode 100644 index 0000000000..d6579571f1 --- /dev/null +++ b/target/i386/hvf/cpu.c @@ -0,0 +1,65 @@ +/* + * x86 HVF CPU type initialization + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "host-cpu.h" +#include "qapi/error.h" +#include "sysemu/sysemu.h" +#include "hw/boards.h" +#include "sysemu/hvf.h" +#include "hw/core/accel-cpu.h" + +static void hvf_cpu_max_instance_init(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + + host_cpu_max_instance_init(cpu); + + env->cpuid_min_level =3D + hvf_get_supported_cpuid(0x0, 0, R_EAX); + env->cpuid_min_xlevel =3D + hvf_get_supported_cpuid(0x80000000, 0, R_EAX); + env->cpuid_min_xlevel2 =3D + hvf_get_supported_cpuid(0xC0000000, 0, R_EAX); +} + +static void hvf_cpu_instance_init(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + + host_cpu_instance_init(cpu); + + /* Special cases not set in the X86CPUDefinition structs: */ + /* TODO: in-kernel irqchip for hvf */ + + if (cpu->max_features) { + hvf_cpu_max_instance_init(cpu); + } +} + +static void hvf_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_realizefn =3D host_cpu_realizefn; + acc->cpu_instance_init =3D hvf_cpu_instance_init; +}; +static const TypeInfo hvf_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("hvf"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D hvf_cpu_accel_class_init, + .abstract =3D true, +}; +static void hvf_cpu_accel_register_types(void) +{ + type_register_static(&hvf_cpu_accel_type_info); +} +type_init(hvf_cpu_accel_register_types); diff --git a/target/i386/hvf/meson.build b/target/i386/hvf/meson.build index 409c9a3f14..a7fba5724c 100644 --- a/target/i386/hvf/meson.build +++ b/target/i386/hvf/meson.build @@ -10,4 +10,5 @@ i386_softmmu_ss.add(when: [hvf, 'CONFIG_HVF'], if_true: f= iles( 'x86_mmu.c', 'x86_task.c', 'x86hvf.c', + 'cpu.c', )) diff --git a/target/i386/kvm/cpu.c b/target/i386/kvm/cpu.c new file mode 100644 index 0000000000..adc5120cf6 --- /dev/null +++ b/target/i386/kvm/cpu.c @@ -0,0 +1,148 @@ +/* + * x86 KVM CPU type initialization + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "host-cpu.h" +#include "kvm-cpu.h" +#include "qapi/error.h" +#include "sysemu/sysemu.h" +#include "hw/boards.h" + +#include "kvm_i386.h" +#include "hw/core/accel-cpu.h" + +static void kvm_cpu_realizefn(CPUState *cs, Error **errp) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + /* + * The realize order is important, since x86_cpu_realize() checks if + * nothing else has been set by the user (or by accelerators) in + * cpu->ucode_rev and cpu->phys_bits. + * + * realize order: + * kvm_cpu -> host_cpu -> x86_cpu + */ + if (cpu->max_features) { + if (enable_cpu_pm && kvm_has_waitpkg()) { + env->features[FEAT_7_0_ECX] |=3D CPUID_7_0_ECX_WAITPKG; + } + if (cpu->ucode_rev =3D=3D 0) { + cpu->ucode_rev =3D + kvm_arch_get_supported_msr_feature(kvm_state, + MSR_IA32_UCODE_REV); + } + } + host_cpu_realizefn(cs, errp); +} + +/* + * KVM-specific features that are automatically added/removed + * from all CPU models when KVM is enabled. + */ +static PropValue kvm_default_props[] =3D { + { "kvmclock", "on" }, + { "kvm-nopiodelay", "on" }, + { "kvm-asyncpf", "on" }, + { "kvm-steal-time", "on" }, + { "kvm-pv-eoi", "on" }, + { "kvmclock-stable-bit", "on" }, + { "x2apic", "on" }, + { "acpi", "off" }, + { "monitor", "off" }, + { "svm", "off" }, + { NULL, NULL }, +}; + +void x86_cpu_change_kvm_default(const char *prop, const char *value) +{ + PropValue *pv; + for (pv =3D kvm_default_props; pv->prop; pv++) { + if (!strcmp(pv->prop, prop)) { + pv->value =3D value; + break; + } + } + + /* + * It is valid to call this function only for properties that + * are already present in the kvm_default_props table. + */ + assert(pv->prop); +} + +static bool lmce_supported(void) +{ + uint64_t mce_cap =3D 0; + + if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0)= { + return false; + } + return !!(mce_cap & MCG_LMCE_P); +} + +static void kvm_cpu_max_instance_init(X86CPU *cpu) +{ + CPUX86State *env =3D &cpu->env; + KVMState *s =3D kvm_state; + + host_cpu_max_instance_init(cpu); + + if (lmce_supported()) { + object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort); + } + + env->cpuid_min_level =3D + kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); + env->cpuid_min_xlevel =3D + kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); + env->cpuid_min_xlevel2 =3D + kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); +} + +static void kvm_cpu_instance_init(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + + host_cpu_instance_init(cpu); + + if (!kvm_irqchip_in_kernel()) { + x86_cpu_change_kvm_default("x2apic", "off"); + } + + /* Special cases not set in the X86CPUDefinition structs: */ + + x86_cpu_apply_props(cpu, kvm_default_props); + + if (cpu->max_features) { + kvm_cpu_max_instance_init(cpu); + } +} + +static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_realizefn =3D kvm_cpu_realizefn; + acc->cpu_instance_init =3D kvm_cpu_instance_init; +} +static const TypeInfo kvm_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("kvm"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D kvm_cpu_accel_class_init, + .abstract =3D true, +}; +static void kvm_cpu_accel_register_types(void) +{ + type_register_static(&kvm_cpu_accel_type_info); +} +type_init(kvm_cpu_accel_register_types); diff --git a/target/i386/kvm/kvm-cpu.h b/target/i386/kvm/kvm-cpu.h new file mode 100644 index 0000000000..e858ca21e5 --- /dev/null +++ b/target/i386/kvm/kvm-cpu.h @@ -0,0 +1,41 @@ +/* + * i386 KVM CPU type and functions + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef KVM_CPU_H +#define KVM_CPU_H + +#ifdef CONFIG_KVM +/* + * Change the value of a KVM-specific default + * + * If value is NULL, no default will be set and the original + * value from the CPU model table will be kept. + * + * It is valid to call this function only for properties that + * are already present in the kvm_default_props table. + */ +void x86_cpu_change_kvm_default(const char *prop, const char *value); + +#else /* !CONFIG_KVM */ + +#define x86_cpu_change_kvm_default(a, b) + +#endif /* CONFIG_KVM */ + +#endif /* KVM_CPU_H */ diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index a2934dda02..35c86fdba6 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -22,6 +22,7 @@ #include "standard-headers/asm-x86/kvm_para.h" =20 #include "cpu.h" +#include "host-cpu.h" #include "sysemu/sysemu.h" #include "sysemu/hw_accel.h" #include "sysemu/kvm_int.h" @@ -285,7 +286,7 @@ static bool host_tsx_broken(void) int family, model, stepping;\ char vendor[CPUID_VENDOR_SZ + 1]; =20 - host_vendor_fms(vendor, &family, &model, &stepping); + host_cpu_vendor_fms(vendor, &family, &model, &stepping); =20 /* Check if we are running on a Haswell host known to have broken TSX = */ return !strcmp(vendor, CPUID_VENDOR_INTEL) && diff --git a/target/i386/kvm/meson.build b/target/i386/kvm/meson.build index 1d66559187..0bc3724eb3 100644 --- a/target/i386/kvm/meson.build +++ b/target/i386/kvm/meson.build @@ -1,3 +1,8 @@ i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) -i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) + +i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files( + 'kvm.c', + 'cpu.c', +)) + i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_= false: files('hyperv-stub.c')) diff --git a/target/i386/meson.build b/target/i386/meson.build index 9c20208e5a..4e6e915e7f 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -6,8 +6,12 @@ i386_ss.add(files( 'xsave_helper.c', 'cpu-dump.c', )) -i386_ss.add(when: 'CONFIG_TCG', if_true: files('tcg-cpu.c')) -i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) + +i386_ss.add(when: 'CONFIG_SEV', if_true: files('host-cpu.c', 'sev.c'), if_= false: files('sev-stub.c')) + +# x86 cpu type +i386_ss.add(when: 'CONFIG_KVM', if_true: files('host-cpu.c')) +i386_ss.add(when: 'CONFIG_HVF', if_true: files('host-cpu.c')) =20 i386_softmmu_ss =3D ss.source_set() i386_softmmu_ss.add(files( diff --git a/target/i386/tcg-cpu.c b/target/i386/tcg-cpu.c deleted file mode 100644 index 628dd29fe7..0000000000 --- a/target/i386/tcg-cpu.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * i386 TCG cpu class initialization - * - * Copyright (c) 2003 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "tcg-cpu.h" -#include "exec/exec-all.h" -#include "sysemu/runstate.h" -#include "helper-tcg.h" - -#if !defined(CONFIG_USER_ONLY) -#include "hw/i386/apic.h" -#endif - -/* Frob eflags into and out of the CPU temporary format. */ - -static void x86_cpu_exec_enter(CPUState *cs) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - - CC_SRC =3D env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - env->df =3D 1 - (2 * ((env->eflags >> 10) & 1)); - CC_OP =3D CC_OP_EFLAGS; - env->eflags &=3D ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); -} - -static void x86_cpu_exec_exit(CPUState *cs) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - - env->eflags =3D cpu_compute_eflags(env); -} - -static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) -{ - X86CPU *cpu =3D X86_CPU(cs); - - cpu->env.eip =3D tb->pc - tb->cs_base; -} - -void tcg_cpu_common_class_init(CPUClass *cc) -{ - cc->do_interrupt =3D x86_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; - cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; - cc->cpu_exec_enter =3D x86_cpu_exec_enter; - cc->cpu_exec_exit =3D x86_cpu_exec_exit; - cc->tcg_initialize =3D tcg_x86_init; - cc->tlb_fill =3D x86_cpu_tlb_fill; -#ifndef CONFIG_USER_ONLY - cc->debug_excp_handler =3D breakpoint_handler; -#endif -} diff --git a/target/i386/tcg-cpu.h b/target/i386/tcg-cpu.h deleted file mode 100644 index 81f02e562e..0000000000 --- a/target/i386/tcg-cpu.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * i386 TCG CPU class initialization - * - * Copyright 2020 SUSE LLC - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#ifndef TCG_CPU_H -#define TCG_CPU_H - -void tcg_cpu_common_class_init(CPUClass *cc); - -#endif /* TCG_CPU_H */ diff --git a/target/i386/tcg/cpu.c b/target/i386/tcg/cpu.c new file mode 100644 index 0000000000..bdb4971ba9 --- /dev/null +++ b/target/i386/tcg/cpu.c @@ -0,0 +1,173 @@ +/* + * i386 TCG cpu class initialization + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "helper-tcg.h" +#include "qemu/accel.h" +#include "hw/core/accel-cpu.h" + +#ifndef CONFIG_USER_ONLY +#include "sysemu/sysemu.h" +#include "qemu/units.h" +#include "exec/address-spaces.h" +#endif + +/* Frob eflags into and out of the CPU temporary format. */ + +static void x86_cpu_exec_enter(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + CC_SRC =3D env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + env->df =3D 1 - (2 * ((env->eflags >> 10) & 1)); + CC_OP =3D CC_OP_EFLAGS; + env->eflags &=3D ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); +} + +static void x86_cpu_exec_exit(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + env->eflags =3D cpu_compute_eflags(env); +} + +static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + X86CPU *cpu =3D X86_CPU(cs); + + cpu->env.eip =3D tb->pc - tb->cs_base; +} + +#ifndef CONFIG_USER_ONLY + +static void x86_cpu_machine_done(Notifier *n, void *unused) +{ + X86CPU *cpu =3D container_of(n, X86CPU, machine_done); + MemoryRegion *smram =3D + (MemoryRegion *) object_resolve_path("/machine/smram", NULL); + + if (smram) { + cpu->smram =3D g_new(MemoryRegion, 1); + memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram", + smram, 0, 4 * GiB); + memory_region_set_enabled(cpu->smram, true); + memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, + cpu->smram, 1); + } +} + +static void tcg_cpu_realizefn(CPUState *cs, Error **errp) +{ + X86CPU *cpu =3D X86_CPU(cs); + + /* + * The realize order is important, since x86_cpu_realize() checks if + * nothing else has been set by the user (or by accelerators) in + * cpu->ucode_rev and cpu->phys_bits, and the memory regions + * initialized here are needed for the vcpu initialization. + * + * realize order: + * tcg_cpu -> host_cpu -> x86_cpu + */ + cpu->cpu_as_mem =3D g_new(MemoryRegion, 1); + cpu->cpu_as_root =3D g_new(MemoryRegion, 1); + + /* Outer container... */ + memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull); + memory_region_set_enabled(cpu->cpu_as_root, true); + + /* + * ... with two regions inside: normal system memory with low + * priority, and... + */ + memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory", + get_system_memory(), 0, ~0ull); + memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_m= em, 0); + memory_region_set_enabled(cpu->cpu_as_mem, true); + + cs->num_ases =3D 2; + cpu_address_space_init(cs, 0, "cpu-memory", cs->memory); + cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root); + + /* ... SMRAM with higher priority, linked from /machine/smram. */ + cpu->machine_done.notify =3D x86_cpu_machine_done; + qemu_add_machine_init_done_notifier(&cpu->machine_done); +} + +#else /* CONFIG_USER_ONLY */ + +static void tcg_cpu_realizefn(CPUState *cs, Error **errp) +{ +} + +#endif /* !CONFIG_USER_ONLY */ + + +static void tcg_cpu_class_init(CPUClass *cc) +{ + cc->do_interrupt =3D x86_cpu_do_interrupt; + cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; + cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; + cc->cpu_exec_enter =3D x86_cpu_exec_enter; + cc->cpu_exec_exit =3D x86_cpu_exec_exit; + cc->tcg_initialize =3D tcg_x86_init; + cc->tlb_fill =3D x86_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY + cc->debug_excp_handler =3D breakpoint_handler; +#endif /* !CONFIG_USER_ONLY */ +} + +/* + * TCG-specific defaults that override all CPU models when using TCG + */ +static PropValue tcg_default_props[] =3D { + { "vme", "off" }, + { NULL, NULL }, +}; + +static void tcg_cpu_instance_init(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + /* Special cases not set in the X86CPUDefinition structs: */ + x86_cpu_apply_props(cpu, tcg_default_props); +} + +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_realizefn =3D tcg_cpu_realizefn; + acc->cpu_class_init =3D tcg_cpu_class_init; + acc->cpu_instance_init =3D tcg_cpu_instance_init; +} +static const TypeInfo tcg_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("tcg"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D tcg_cpu_accel_class_init, + .abstract =3D true, +}; +static void tcg_cpu_accel_register_types(void) +{ + type_register_static(&tcg_cpu_accel_type_info); +} +type_init(tcg_cpu_accel_register_types); diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build index 02794226c2..9e439df9c7 100644 --- a/target/i386/tcg/meson.build +++ b/target/i386/tcg/meson.build @@ -10,4 +10,5 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files( 'seg_helper.c', 'smm_helper.c', 'svm_helper.c', - 'translate.c'), if_false: files('tcg-stub.c')) + 'translate.c', + 'cpu.c'), if_false: files('tcg-stub.c')) --=20 2.26.2