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[88.21.205.111]) by smtp.gmail.com with ESMTPSA id 6sm25327322wrn.72.2020.11.23.12.46.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Nov 2020 12:46:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y0Js5XRdc4mHW1GhozQJ/l2GsYmBgybFSQVaSoieEFs=; b=Zkp360kAzVxCaILcK5NTzwIBhwhjkhLcnJOzSAEsnwxgdJAuoWTz8kSYE1F/2hL5rY uT97vpd2vQ3PZRJ3gQmmKsBy7ObVp7sR7RcO36p4Nih6P3YgqfSIrw30tm4eaR/sGnti Z5KzCazlbAJhvYCT64v0Mn1oh9TvYYKfLhxcjXBnAeHryUXSiy7j2YYiqft+MmWNVYZT W6fOx7xSY0S4ujsNsjQD1sYIQNQ04s4RL32YPb3Og6MMMY/r3ghPPjLFheTonqHwCgI8 ncYHIfKGl0eFtC48WBV+gwYY1VIE3Y/cQ0BSjDOEWDGKh3pM8S+YWNr/bnyGPRbxMKZW e5Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=y0Js5XRdc4mHW1GhozQJ/l2GsYmBgybFSQVaSoieEFs=; b=QlsAjSOUpzYDmL1IibPFU9AKaBK1vCF0l/UL1lMmhRo/jpZc7P6aAdxtqSjck6b071 eM8U+cyK6Mz8FBdZ8vM8PZvi+mMY7sz6SP5qYqo2YKj8hfsuh7YQQ066b7vN5F9QPwaC 7vWPT7vNfDDbhZTqLVy25px0GD2RUIUkoXWLSS0lzinGGdt+RQ2svUED6nwGVvHr4HXL xwPdvTlyPDxPW44TfkGDRy2+1jKO+mfjxUop75YpnvOEs7DyzmbiSYohW7Wa8MBh8QQy BLLA+eZ2W1sAcAr2Wku/vRZ8L+TcNTXvqvlk/8Fyp0akwERCbEo8E+lJLKGv8iX64iTM Trpw== X-Gm-Message-State: AOAM531UzRLnLHn30WmZJJ6ObTb0NEb0VYoh/qWaMbiBSIiipysIfIqL ymVPfLwMPZWNMVQ2tRQ4X0P3nTwu3bk= X-Google-Smtp-Source: ABdhPJzwh0LYi3yyJti3EVYoaFYO8OfnSVFc0c4FwWGFF1CBk1g6Riu8TMA7GhokvLeAqPYSkAzndw== X-Received: by 2002:a1c:4006:: with SMTP id n6mr677685wma.135.1606164375204; Mon, 23 Nov 2020 12:46:15 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 17/28] target/mips: Extract NEC Vr54xx translation routines Date: Mon, 23 Nov 2020 21:44:37 +0100 Message-Id: <20201123204448.3260804-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201123204448.3260804-1-f4bug@amsat.org> References: <20201123204448.3260804-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Extract the NEC Vr54xx translation routines to 'vendor-vr54xx_translate.c.inc'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201120210844.2625602-16-f4bug@amsat.org> --- target/mips/translate.c | 86 +-------------------- target/mips/vendor-vr54xx_translate.c.inc | 93 +++++++++++++++++++++++ 2 files changed, 95 insertions(+), 84 deletions(-) create mode 100644 target/mips/vendor-vr54xx_translate.c.inc diff --git a/target/mips/translate.c b/target/mips/translate.c index d6133bd7de7..ca2e79d955a 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -295,26 +295,6 @@ enum { OPC_DLSA =3D 0x15 | OPC_SPECIAL, }; =20 -/* Multiplication variants of the vr54xx. */ -#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6))) - -enum { - OPC_VR54XX_MULS =3D (0x03 << 6) | OPC_MULT, - OPC_VR54XX_MULSU =3D (0x03 << 6) | OPC_MULTU, - OPC_VR54XX_MACC =3D (0x05 << 6) | OPC_MULT, - OPC_VR54XX_MACCU =3D (0x05 << 6) | OPC_MULTU, - OPC_VR54XX_MSAC =3D (0x07 << 6) | OPC_MULT, - OPC_VR54XX_MSACU =3D (0x07 << 6) | OPC_MULTU, - OPC_VR54XX_MULHI =3D (0x09 << 6) | OPC_MULT, - OPC_VR54XX_MULHIU =3D (0x09 << 6) | OPC_MULTU, - OPC_VR54XX_MULSHI =3D (0x0B << 6) | OPC_MULT, - OPC_VR54XX_MULSHIU =3D (0x0B << 6) | OPC_MULTU, - OPC_VR54XX_MACCHI =3D (0x0D << 6) | OPC_MULT, - OPC_VR54XX_MACCHIU =3D (0x0D << 6) | OPC_MULTU, - OPC_VR54XX_MSACHI =3D (0x0F << 6) | OPC_MULT, - OPC_VR54XX_MSACHIU =3D (0x0F << 6) | OPC_MULTU, -}; - /* REGIMM (rt field) opcodes */ #define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16= ))) =20 @@ -4546,70 +4526,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t= opc, tcg_temp_free(t1); } =20 -static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, - int rd, int rs, int rt) -{ - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - gen_load_gpr(t0, rs); - gen_load_gpr(t1, rt); - - switch (opc) { - case OPC_VR54XX_MULS: - gen_helper_muls(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSU: - gen_helper_mulsu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACC: - gen_helper_macc(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCU: - gen_helper_maccu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSAC: - gen_helper_msac(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACU: - gen_helper_msacu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULHI: - gen_helper_mulhi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULHIU: - gen_helper_mulhiu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSHI: - gen_helper_mulshi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSHIU: - gen_helper_mulshiu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCHI: - gen_helper_macchi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCHIU: - gen_helper_macchiu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACHI: - gen_helper_msachi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACHIU: - gen_helper_msachiu(t0, cpu_env, t0, t1); - break; - default: - MIPS_INVAL("mul vr54xx"); - generate_exception_end(ctx, EXCP_RI); - goto out; - } - gen_store_gpr(t0, rd); - - out: - tcg_temp_free(t0); - tcg_temp_free(t1); -} - static void gen_cl(DisasContext *ctx, uint32_t opc, int rd, int rs) { @@ -13022,6 +12938,8 @@ out: =20 #include "mod-dsp_translate.c.inc" =20 +#include "vendor-vr54xx_translate.c.inc" + static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) { int rs, rt, rd, sa; diff --git a/target/mips/vendor-vr54xx_translate.c.inc b/target/mips/vendor= -vr54xx_translate.c.inc new file mode 100644 index 00000000000..8c952a98ebc --- /dev/null +++ b/target/mips/vendor-vr54xx_translate.c.inc @@ -0,0 +1,93 @@ +/* + * MIPS NEC Vr54xx translation routines. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +/* Multiplication variants of the vr54xx. */ +#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6))) + +enum { + OPC_VR54XX_MULS =3D (0x03 << 6) | OPC_MULT, + OPC_VR54XX_MULSU =3D (0x03 << 6) | OPC_MULTU, + OPC_VR54XX_MACC =3D (0x05 << 6) | OPC_MULT, + OPC_VR54XX_MACCU =3D (0x05 << 6) | OPC_MULTU, + OPC_VR54XX_MSAC =3D (0x07 << 6) | OPC_MULT, + OPC_VR54XX_MSACU =3D (0x07 << 6) | OPC_MULTU, + OPC_VR54XX_MULHI =3D (0x09 << 6) | OPC_MULT, + OPC_VR54XX_MULHIU =3D (0x09 << 6) | OPC_MULTU, + OPC_VR54XX_MULSHI =3D (0x0B << 6) | OPC_MULT, + OPC_VR54XX_MULSHIU =3D (0x0B << 6) | OPC_MULTU, + OPC_VR54XX_MACCHI =3D (0x0D << 6) | OPC_MULT, + OPC_VR54XX_MACCHIU =3D (0x0D << 6) | OPC_MULTU, + OPC_VR54XX_MSACHI =3D (0x0F << 6) | OPC_MULT, + OPC_VR54XX_MSACHIU =3D (0x0F << 6) | OPC_MULTU, +}; + +static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) +{ + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + switch (opc) { + case OPC_VR54XX_MULS: + gen_helper_muls(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MULSU: + gen_helper_mulsu(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MACC: + gen_helper_macc(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MACCU: + gen_helper_maccu(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MSAC: + gen_helper_msac(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MSACU: + gen_helper_msacu(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MULHI: + gen_helper_mulhi(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MULHIU: + gen_helper_mulhiu(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MULSHI: + gen_helper_mulshi(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MULSHIU: + gen_helper_mulshiu(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MACCHI: + gen_helper_macchi(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MACCHIU: + gen_helper_macchiu(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MSACHI: + gen_helper_msachi(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MSACHIU: + gen_helper_msachiu(t0, cpu_env, t0, t1); + break; + default: + MIPS_INVAL("mul vr54xx"); + generate_exception_end(ctx, EXCP_RI); + goto out; + } + gen_store_gpr(t0, rd); + + out: + tcg_temp_free(t0); + tcg_temp_free(t1); +} --=20 2.26.2