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[83.42.66.234]) by smtp.gmail.com with ESMTPSA id g131sm5857149wma.35.2020.11.20.13.10.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Nov 2020 13:10:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rm8hYLTL5cania5VITZzWfQieMs0D23dPfzaoPosV3I=; b=aoIfLHmArPUFlfb8IQyDQfmyvkvM7vjFtHFV6CC3bDthy6ZCgN561wVaGoPsX27VTZ u6ySV/6fNwFgbDFl4El5WgDd80YxWwhdCiYc38gKdLBRnw/VlGnHpPLBMrw5XTNLQOZa hwyUV3OGAAm016e7l5T2lcuLM6f7eQrJPUpmYtghGZ8XwwCSq+pebi12cy33Jd+q5zHr 0OBzkGmfySbrGzFfo4+NlOpUN3x62n6qHPQwI2hQmSZcVkHUdsDDiKE1fmKysa7m6P61 h2U8MorLmrN58f8ITmjO3+s8fzUla5PWVBpEjsCaD1P91zincUyNZAQFnpAvM59YmUBy +QmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Rm8hYLTL5cania5VITZzWfQieMs0D23dPfzaoPosV3I=; b=WDbbwYmLAOgQhn6crk7rmfSAVbe06IfIxrIkdtvX0GB/G2NUZzteokp+P6VbyQ3dBY Z01QDAvp9nJrzIhpm3wSL/m35KGnyQyjh76vvRsRNeNT7idUIcBgMmcInettL0qd5u2C +DQiWEfZcxfafOuE6jJSSDoSQjF7v+dhSdWybN5Oh1nphI6wCxeAU06/VTmfXQdcKWd3 c8oukpQYkRJYsFL2avJMlmkkMROLGBpNlHWX+r9xr+epi9GAtUY3vx65gJ9Fy43PGvwm OmCN54bwAU1/Oyf5IcB+IxXfji9ADSTV3pDdx+ESl40Vz0NlHYC3PGc2Uu9vMxQ2sGG6 Nc4A== X-Gm-Message-State: AOAM533A964ewqiCqmxJ0sBCWHdwNHDbBVMjKrjDDJ/ny43dVekFPJpd clcQfc5aaWh9E2CAWA0UzAI= X-Google-Smtp-Source: ABdhPJxTKACMefaqiPzdHIy+zYI1qEKZk1BrAvic6PRNwPiMFWrFztjZSrix7u7NnFO0kqMIMmk2/w== X-Received: by 2002:a7b:ce0e:: with SMTP id m14mr11632954wmc.111.1605906637583; Fri, 20 Nov 2020 13:10:37 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Craig Janeczek , Jiaxun Yang , Aurelien Jarno , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Huacai Chen , Paolo Bonzini Subject: [PATCH 21/26] target/mips: Make pipeline 1 multiply opcodes generic Date: Fri, 20 Nov 2020 22:08:39 +0100 Message-Id: <20201120210844.2625602-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201120210844.2625602-1-f4bug@amsat.org> References: <20201120210844.2625602-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Special2 multiply opcodes are not specific to Toshiba TX79, and are not part of its multimedia extension. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 75 +++++++++++++++++++++-------------------- 1 file changed, 38 insertions(+), 37 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 0914b89eae6..6b35498dd3d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -330,6 +330,19 @@ enum { OPC_MUL =3D 0x02 | OPC_SPECIAL2, OPC_MSUB =3D 0x04 | OPC_SPECIAL2, OPC_MSUBU =3D 0x05 | OPC_SPECIAL2, + + /* Multiply Instructions for Pipeline 1 */ + OPC_MFHI1 =3D 0x10 | OPC_SPECIAL2, + OPC_MTHI1 =3D 0x11 | OPC_SPECIAL2, + OPC_MFLO1 =3D 0x12 | OPC_SPECIAL2, + OPC_MTLO1 =3D 0x13 | OPC_SPECIAL2, + OPC_MULT1 =3D 0x18 | OPC_SPECIAL2, + OPC_MULTU1 =3D 0x19 | OPC_SPECIAL2, + OPC_DIV1 =3D 0x1A | OPC_SPECIAL2, + OPC_DIVU1 =3D 0x1B | OPC_SPECIAL2, + OPC_MADD1 =3D 0x20 | OPC_SPECIAL2, + OPC_MADDU1 =3D 0x21 | OPC_SPECIAL2, + /* Misc */ OPC_CLZ =3D 0x20 | OPC_SPECIAL2, OPC_CLO =3D 0x21 | OPC_SPECIAL2, @@ -933,21 +946,9 @@ enum { =20 #define MASK_MMI(op) (MASK_OP_MAJOR(op) | ((op) & 0x3F)) enum { - MMI_OPC_MADD =3D 0x00 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADD */ - MMI_OPC_MADDU =3D 0x01 | MMI_OPC_CLASS_MMI, /* Same as OPC_MADDU = */ MMI_OPC_PLZCW =3D 0x04 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI0 =3D 0x08 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI2 =3D 0x09 | MMI_OPC_CLASS_MMI, - MMI_OPC_MFHI1 =3D 0x10 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MFHI */ - MMI_OPC_MTHI1 =3D 0x11 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MTHI */ - MMI_OPC_MFLO1 =3D 0x12 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MFLO */ - MMI_OPC_MTLO1 =3D 0x13 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MTLO */ - MMI_OPC_MULT1 =3D 0x18 | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= MULT */ - MMI_OPC_MULTU1 =3D 0x19 | MMI_OPC_CLASS_MMI, /* Same min. as OPC_M= ULTU */ - MMI_OPC_DIV1 =3D 0x1A | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= DIV */ - MMI_OPC_DIVU1 =3D 0x1B | MMI_OPC_CLASS_MMI, /* Same minor as OPC_= DIVU */ - MMI_OPC_MADD1 =3D 0x20 | MMI_OPC_CLASS_MMI, - MMI_OPC_MADDU1 =3D 0x21 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI1 =3D 0x28 | MMI_OPC_CLASS_MMI, MMI_OPC_CLASS_MMI3 =3D 0x29 | MMI_OPC_CLASS_MMI, MMI_OPC_PMFHL =3D 0x30 | MMI_OPC_CLASS_MMI, @@ -3049,26 +3050,26 @@ static void gen_shift(DisasContext *ctx, uint32_t o= pc, /* Copy GPR to and from TX79 HI1/LO1 register. */ static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg) { - if (reg =3D=3D 0 && (opc =3D=3D MMI_OPC_MFHI1 || opc =3D=3D MMI_OPC_MF= LO1)) { + if (reg =3D=3D 0 && (opc =3D=3D OPC_MFHI1 || opc =3D=3D OPC_MFLO1)) { /* Treat as NOP. */ return; } =20 switch (opc) { - case MMI_OPC_MFHI1: + case OPC_MFHI1: tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[1]); break; - case MMI_OPC_MFLO1: + case OPC_MFLO1: tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[1]); break; - case MMI_OPC_MTHI1: + case OPC_MTHI1: if (reg !=3D 0) { tcg_gen_mov_tl(cpu_HI[1], cpu_gpr[reg]); } else { tcg_gen_movi_tl(cpu_HI[1], 0); } break; - case MMI_OPC_MTLO1: + case OPC_MTLO1: if (reg !=3D 0) { tcg_gen_mov_tl(cpu_LO[1], cpu_gpr[reg]); } else { @@ -3443,7 +3444,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t= opc, int rs, int rt) gen_load_gpr(t1, rt); =20 switch (opc) { - case MMI_OPC_DIV1: + case OPC_DIV1: { TCGv t2 =3D tcg_temp_new(); TCGv t3 =3D tcg_temp_new(); @@ -3464,7 +3465,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t= opc, int rs, int rt) tcg_temp_free(t2); } break; - case MMI_OPC_DIVU1: + case OPC_DIVU1: { TCGv t2 =3D tcg_const_tl(0); TCGv t3 =3D tcg_const_tl(1); @@ -3719,7 +3720,7 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t = opc, gen_load_gpr(t1, rt); =20 switch (opc) { - case MMI_OPC_MULT1: + case OPC_MULT1: acc =3D 1; /* Fall through */ case OPC_MULT: @@ -3738,7 +3739,7 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t = opc, tcg_temp_free_i32(t3); } break; - case MMI_OPC_MULTU1: + case OPC_MULTU1: acc =3D 1; /* Fall through */ case OPC_MULTU: @@ -3757,10 +3758,10 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_= t opc, tcg_temp_free_i32(t3); } break; - case MMI_OPC_MADD1: + case OPC_MADD1: acc =3D 1; /* Fall through */ - case MMI_OPC_MADD: + case OPC_MADD: { TCGv_i64 t2 =3D tcg_temp_new_i64(); TCGv_i64 t3 =3D tcg_temp_new_i64(); @@ -3779,10 +3780,10 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_= t opc, tcg_temp_free_i64(t2); } break; - case MMI_OPC_MADDU1: + case OPC_MADDU1: acc =3D 1; /* Fall through */ - case MMI_OPC_MADDU: + case OPC_MADDU: { TCGv_i64 t2 =3D tcg_temp_new_i64(); TCGv_i64 t3 =3D tcg_temp_new_i64(); @@ -12741,24 +12742,24 @@ static void decode_mmi(CPUMIPSState *env, DisasCo= ntext *ctx) case MMI_OPC_CLASS_MMI3: decode_mmi3(env, ctx); break; - case MMI_OPC_MULT1: - case MMI_OPC_MULTU1: - case MMI_OPC_MADD: - case MMI_OPC_MADDU: - case MMI_OPC_MADD1: - case MMI_OPC_MADDU1: + case OPC_MULT1: + case OPC_MULTU1: + case OPC_MADD: + case OPC_MADDU: + case OPC_MADD1: + case OPC_MADDU1: gen_mul_txx9(ctx, opc, rd, rs, rt); break; - case MMI_OPC_DIV1: - case MMI_OPC_DIVU1: + case OPC_DIV1: + case OPC_DIVU1: gen_div1_tx79(ctx, opc, rs, rt); break; - case MMI_OPC_MTLO1: - case MMI_OPC_MTHI1: + case OPC_MTLO1: + case OPC_MTHI1: gen_HILO1_tx79(ctx, opc, rs); break; - case MMI_OPC_MFLO1: - case MMI_OPC_MFHI1: + case OPC_MFLO1: + case OPC_MFHI1: gen_HILO1_tx79(ctx, opc, rd); break; case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */ --=20 2.26.2