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[83.42.66.234]) by smtp.gmail.com with ESMTPSA id w186sm5417507wmb.26.2020.11.20.13.10.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Nov 2020 13:10:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yEPTreAcbmYuWQ/wNZf45C6fc4wRRcv0srLw4kg+KsE=; b=RVbt5BO3aY2rd/K4BEnZA/k7HLmYBwURaXB0YTkE0eeoX39OnNnehbCsKe6wWh/Ma2 p5w4nLyABYEW4nnWmKn2UjRe/RLQNdGW4sDIMsaGkhqypIn8ehQYu4HYYTRZpeHJVFR9 mCV5voyNHrFSNVabIhz6JgWTKkKYXbIWF2GpfPYBnK3ea2Y01DyuwtLMDbDgVpoPtgeC RR4cP6X7UZsqurcBCOYX5MkSaBF+ZJS3HI+vIPHuIuiPeHlpif02AMdFmJYmDvd4l1QB PiQ+5mvNqFKWwbJ8WAlZOfg7WbrWnW3ecQ9Mx09UERWBf6EGC5AF2s9DChSm+SpFlM8r Zqtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yEPTreAcbmYuWQ/wNZf45C6fc4wRRcv0srLw4kg+KsE=; b=npBxlB00vaWfdcK5sTVPyIMVn+mImrlE1UurgmR54K2Y5/YLQ8071FKhvDk40A56i9 XX/hyMn82uJEfihXueMx3npZ7JFmtbbkqvkEaPrqyJE658yPyyJxWfBenSQBVQczDivQ O9wx13CAbN9tS6BGuMBscXEwQoLQa/eJ6WCoGZQdf1SwYw/Iv/1cDc12fI2DNSH08nuF Q+FeGqzsQwQjya9quFl35ksYGM9ak2UvI86MtDSq7ht9aHi2v/5sIH9UZ/7oUCNO2Tlw RmR0cMWYBFxyYEw+utwPC+qIoQn6fcA53uirdgmOTsBV9r/bttNzZ77s7IfouGztuTfa UHWg== X-Gm-Message-State: AOAM530x8j5o5DvxdtX5jL9eE8UArKfWo7xX7oRJjVPJX0JLC5YOKlEw yJWVl9TJVkkYYvugNbjtqEo= X-Google-Smtp-Source: ABdhPJxqkJB7aYRijiVJL7s5nyKRmLXfIBurxYsRZI1v+TtDEAkMJ9UtR7xj+Rp9luiEnca1qPS2hw== X-Received: by 2002:a5d:5222:: with SMTP id i2mr19165213wra.247.1605906605979; Fri, 20 Nov 2020 13:10:05 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Craig Janeczek , Jiaxun Yang , Aurelien Jarno , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fredrik Noring , Aleksandar Rikalo , Richard Henderson , Huacai Chen , Paolo Bonzini Subject: [PATCH 15/26] target/mips: Extract NEC Vr54xx translation routines Date: Fri, 20 Nov 2020 22:08:33 +0100 Message-Id: <20201120210844.2625602-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201120210844.2625602-1-f4bug@amsat.org> References: <20201120210844.2625602-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Extract the NEC Vr54xx translation routines to 'vendor-vr54xx_translate.c.inc'. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 86 +-------------------- target/mips/vendor-vr54xx_translate.c.inc | 93 +++++++++++++++++++++++ 2 files changed, 95 insertions(+), 84 deletions(-) create mode 100644 target/mips/vendor-vr54xx_translate.c.inc diff --git a/target/mips/translate.c b/target/mips/translate.c index 095ee31ab5f..b01a16e9da4 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -295,26 +295,6 @@ enum { OPC_DLSA =3D 0x15 | OPC_SPECIAL, }; =20 -/* Multiplication variants of the vr54xx. */ -#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6))) - -enum { - OPC_VR54XX_MULS =3D (0x03 << 6) | OPC_MULT, - OPC_VR54XX_MULSU =3D (0x03 << 6) | OPC_MULTU, - OPC_VR54XX_MACC =3D (0x05 << 6) | OPC_MULT, - OPC_VR54XX_MACCU =3D (0x05 << 6) | OPC_MULTU, - OPC_VR54XX_MSAC =3D (0x07 << 6) | OPC_MULT, - OPC_VR54XX_MSACU =3D (0x07 << 6) | OPC_MULTU, - OPC_VR54XX_MULHI =3D (0x09 << 6) | OPC_MULT, - OPC_VR54XX_MULHIU =3D (0x09 << 6) | OPC_MULTU, - OPC_VR54XX_MULSHI =3D (0x0B << 6) | OPC_MULT, - OPC_VR54XX_MULSHIU =3D (0x0B << 6) | OPC_MULTU, - OPC_VR54XX_MACCHI =3D (0x0D << 6) | OPC_MULT, - OPC_VR54XX_MACCHIU =3D (0x0D << 6) | OPC_MULTU, - OPC_VR54XX_MSACHI =3D (0x0F << 6) | OPC_MULT, - OPC_VR54XX_MSACHIU =3D (0x0F << 6) | OPC_MULTU, -}; - /* REGIMM (rt field) opcodes */ #define MASK_REGIMM(op) (MASK_OP_MAJOR(op) | (op & (0x1F << 16= ))) =20 @@ -4546,70 +4526,6 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t= opc, tcg_temp_free(t1); } =20 -static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, - int rd, int rs, int rt) -{ - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - - gen_load_gpr(t0, rs); - gen_load_gpr(t1, rt); - - switch (opc) { - case OPC_VR54XX_MULS: - gen_helper_muls(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSU: - gen_helper_mulsu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACC: - gen_helper_macc(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCU: - gen_helper_maccu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSAC: - gen_helper_msac(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACU: - gen_helper_msacu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULHI: - gen_helper_mulhi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULHIU: - gen_helper_mulhiu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSHI: - gen_helper_mulshi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MULSHIU: - gen_helper_mulshiu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCHI: - gen_helper_macchi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MACCHIU: - gen_helper_macchiu(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACHI: - gen_helper_msachi(t0, cpu_env, t0, t1); - break; - case OPC_VR54XX_MSACHIU: - gen_helper_msachiu(t0, cpu_env, t0, t1); - break; - default: - MIPS_INVAL("mul vr54xx"); - generate_exception_end(ctx, EXCP_RI); - goto out; - } - gen_store_gpr(t0, rd); - - out: - tcg_temp_free(t0); - tcg_temp_free(t1); -} - static void gen_cl(DisasContext *ctx, uint32_t opc, int rd, int rs) { @@ -13022,6 +12938,8 @@ out: =20 #include "mod-mips-dsp_translate.c.inc" =20 +#include "vendor-vr54xx_translate.c.inc" + static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) { int rs, rt, rd, sa; diff --git a/target/mips/vendor-vr54xx_translate.c.inc b/target/mips/vendor= -vr54xx_translate.c.inc new file mode 100644 index 00000000000..8c952a98ebc --- /dev/null +++ b/target/mips/vendor-vr54xx_translate.c.inc @@ -0,0 +1,93 @@ +/* + * MIPS NEC Vr54xx translation routines. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +/* Multiplication variants of the vr54xx. */ +#define MASK_MUL_VR54XX(op) (MASK_SPECIAL(op) | (op & (0x1F << 6))) + +enum { + OPC_VR54XX_MULS =3D (0x03 << 6) | OPC_MULT, + OPC_VR54XX_MULSU =3D (0x03 << 6) | OPC_MULTU, + OPC_VR54XX_MACC =3D (0x05 << 6) | OPC_MULT, + OPC_VR54XX_MACCU =3D (0x05 << 6) | OPC_MULTU, + OPC_VR54XX_MSAC =3D (0x07 << 6) | OPC_MULT, + OPC_VR54XX_MSACU =3D (0x07 << 6) | OPC_MULTU, + OPC_VR54XX_MULHI =3D (0x09 << 6) | OPC_MULT, + OPC_VR54XX_MULHIU =3D (0x09 << 6) | OPC_MULTU, + OPC_VR54XX_MULSHI =3D (0x0B << 6) | OPC_MULT, + OPC_VR54XX_MULSHIU =3D (0x0B << 6) | OPC_MULTU, + OPC_VR54XX_MACCHI =3D (0x0D << 6) | OPC_MULT, + OPC_VR54XX_MACCHIU =3D (0x0D << 6) | OPC_MULTU, + OPC_VR54XX_MSACHI =3D (0x0F << 6) | OPC_MULT, + OPC_VR54XX_MSACHIU =3D (0x0F << 6) | OPC_MULTU, +}; + +static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) +{ + TCGv t0 =3D tcg_temp_new(); + TCGv t1 =3D tcg_temp_new(); + + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); + + switch (opc) { + case OPC_VR54XX_MULS: + gen_helper_muls(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MULSU: + gen_helper_mulsu(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MACC: + gen_helper_macc(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MACCU: + gen_helper_maccu(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MSAC: + gen_helper_msac(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MSACU: + gen_helper_msacu(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MULHI: + gen_helper_mulhi(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MULHIU: + gen_helper_mulhiu(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MULSHI: + gen_helper_mulshi(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MULSHIU: + gen_helper_mulshiu(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MACCHI: + gen_helper_macchi(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MACCHIU: + gen_helper_macchiu(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MSACHI: + gen_helper_msachi(t0, cpu_env, t0, t1); + break; + case OPC_VR54XX_MSACHIU: + gen_helper_msachiu(t0, cpu_env, t0, t1); + break; + default: + MIPS_INVAL("mul vr54xx"); + generate_exception_end(ctx, EXCP_RI); + goto out; + } + gen_store_gpr(t0, rd); + + out: + tcg_temp_free(t0); + tcg_temp_free(t1); +} --=20 2.26.2