From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823129; cv=none; d=zohomail.com; s=zohoarc; b=HYLC3gDBIkI1Igt/cPnBTA5kD3RBB0mpLCT4E2aM1wKQ3/C4QuQebAY1/osUYro90mEanq3ykBwlNt2fO+zv4w71Kg2O4V/C0kDodr3tUy/XbXJDeXtBodWPWMtc5HfpDIJpBOrPaPdD1Gey9EwtdDLMbdrouGqV+SEcnB8hOnc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823129; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=P266bvaGi96rutzNGlfxheYGOykPj3yPIMwI917NjaA=; b=FF9xshbDvMxkNMmHjFCQIrJvnGXUx6ZJ13yt66V+elv43aEM5eG+Av0OxIqCrwpZaGdEpnbcC0SMs0JPo74v9iT95lUkYkDpu37SCi385tSja9/wZnghZ+qXCflGUlNziRRWb8c6wH7VKCFgRKaEKDB20C+zU1JfTCX7SfIuMoo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605823129122555.3929244294579; Thu, 19 Nov 2020 13:58:49 -0800 (PST) Received: from localhost ([::1]:46194 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfrx1-0002Xq-SB for importer@patchew.org; Thu, 19 Nov 2020 16:58:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51036) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfruk-0000YV-Vb for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:26 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:38745) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrug-00046W-PF for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:26 -0500 Received: by mail-wr1-x441.google.com with SMTP id p8so8018506wrx.5 for ; Thu, 19 Nov 2020 13:56:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=P266bvaGi96rutzNGlfxheYGOykPj3yPIMwI917NjaA=; b=hH9Qz3ruGDIfenEeYQLCM9sjHr8J8uYHz3NowDo8CRZz0SN0GmIGIgJwQ1juTjpytY cQqa/vOT3Ft5E0Mont2VumTix/d0KfpkV+YaOjypJvEXRcQ6o1FHf4ll/B1jFOGSplGY 8VjGz1bx/k2nzfiXNKJGoc+YMrnRC0C/1s1DPt8ROEXsSEDeF3VsNDfaU8njKbUw4T7P KO5O7a3ZP1IyGEl51dWFx3fZTynkqhuDa08fuc3mRKAkGg/uOHt+8dXnZ6zbCCR3VxN+ NwLDxcORI/Otfqn7P4XgwThzfiKa2bh5SFPPb2aoR4LKjKanKhxV5uY7g2xLJaZ6I2wi NcHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P266bvaGi96rutzNGlfxheYGOykPj3yPIMwI917NjaA=; b=HTWaIKimyGsIRnZlXcFs4OTTtAFtxLrU4e2ydIB95vneNUt4WvKc3nmw9eIbu6Ecvr q4+YDtunJV0T0mgqAIyWYyHaxCufu7tF77yUOXY+c8HzxgRXJKalKv2z36rwOjgVbDVa 2AV8SUh1iUZuPPp1jCs0xgIPiJz1yTS2CoFbwsVw47YjTb36XPpashPsFDRKs8ZBozlJ zpWZbN8dr1zV8R35mH39mOsLrqn3HJbE3pYMotNzLjDpCEKced3y3/8KUTbnTr+6R/hB 0zJOZcbjgQSbCZJ1vR2s2QjtDNF1MDiqBBEvDEu1IDlZ71LpRxg5g5cwCRV9o9qSoYdo qz6A== X-Gm-Message-State: AOAM532JHe3RK7oOeWHFqCDs7CHIp0BqB0vZ0kTBKRkDL1eBmIZSgBXj S1Mii+krZ6kAFgzk01tbiOqnRTLF79K7QA== X-Google-Smtp-Source: ABdhPJzDsyKDllHcM760vqgQcIFvw/YCXxUdm4abOVA/wU0N7ZrR3qiJpB5djG3TDYr6X3AN+g4hCA== X-Received: by 2002:adf:9407:: with SMTP id 7mr13167458wrq.182.1605822981210; Thu, 19 Nov 2020 13:56:21 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 01/28] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault Date: Thu, 19 Nov 2020 21:55:50 +0000 Message-Id: <20201119215617.29887-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For M-profile CPUs, the range from 0xe0000000 to 0xe00fffff is the Private Peripheral Bus range, which includes all of the memory mapped devices and registers that are part of the CPU itself, including the NVIC, systick timer, and debug and trace components like the Data Watchpoint and Trace unit (DWT). Within this large region, the range 0xe000e000 to 0xe000efff is the System Control Space (NVIC, system registers, systick) and 0xe002e000 to 0exe002efff is its Non-secure alias. The architecture is clear that within the SCS unimplemented registers should be RES0 for privileged accesses and generate BusFault for unprivileged accesses, and we currently implement this. It is less clear about how to handle accesses to unimplemented regions of the wider PPB. Unprivileged accesses should definitely cause BusFaults (R_DQQS), but the behaviour of privileged accesses is not given as a general rule. However, the register definitions of individual registers for components like the DWT all state that they are RES0 if the relevant component is not implemented, so the simplest way to provide that is to provide RAZ/WI for the whole range for privileged accesses. (The v7M Arm ARM does say that reserved registers should be UNK/SBZP.) Expand the container MemoryRegion that the NVIC exposes so that it covers the whole PPB space. This means: * moving the address that the ARMV7M device maps it to down by 0xe000 bytes * moving the off and the offsets within the container of all the subregions forward by 0xe000 bytes * adding a new default MemoryRegion that covers the whole container at a lower priority than anything else and which provides the RAZWI/BusFault behaviour Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/intc/armv7m_nvic.h | 1 + hw/arm/armv7m.c | 2 +- hw/intc/armv7m_nvic.c | 78 ++++++++++++++++++++++++++++++----- 3 files changed, 69 insertions(+), 12 deletions(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index bb087b23c35..33b6d8810c7 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -84,6 +84,7 @@ struct NVICState { MemoryRegion systickmem; MemoryRegion systick_ns_mem; MemoryRegion container; + MemoryRegion defaultmem; =20 uint32_t num_irq; qemu_irq excpout; diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 8113b29f1fd..944f261dd05 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -225,7 +225,7 @@ static void armv7m_realize(DeviceState *dev, Error **er= rp) sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); =20 - memory_region_add_subregion(&s->container, 0xe000e000, + memory_region_add_subregion(&s->container, 0xe0000000, sysbus_mmio_get_region(sbd, 0)); =20 for (i =3D 0; i < ARRAY_SIZE(s->bitband); i++) { diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 42b1ad59e65..9628ce876e0 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2479,6 +2479,43 @@ static const MemoryRegionOps nvic_systick_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +/* + * Unassigned portions of the PPB space are RAZ/WI for privileged + * accesses, and fault for non-privileged accesses. + */ +static MemTxResult ppb_default_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\= n", + (uint32_t)addr); + if (attrs.user) { + return MEMTX_ERROR; + } + *data =3D 0; + return MEMTX_OK; +} + +static MemTxResult ppb_default_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x= \n", + (uint32_t)addr); + if (attrs.user) { + return MEMTX_ERROR; + } + return MEMTX_OK; +} + +static const MemoryRegionOps ppb_default_ops =3D { + .read_with_attrs =3D ppb_default_read, + .write_with_attrs =3D ppb_default_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 8, +}; + static int nvic_post_load(void *opaque, int version_id) { NVICState *s =3D opaque; @@ -2675,7 +2712,6 @@ static void nvic_systick_trigger(void *opaque, int n,= int level) static void armv7m_nvic_realize(DeviceState *dev, Error **errp) { NVICState *s =3D NVIC(dev); - int regionlen; =20 /* The armv7m container object will have set our CPU pointer */ if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) { @@ -2718,7 +2754,20 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) M_REG_S)); } =20 - /* The NVIC and System Control Space (SCS) starts at 0xe000e000 + /* + * This device provides a single sysbus memory region which + * represents the whole of the "System PPB" space. This is the + * range from 0xe0000000 to 0xe00fffff and includes the NVIC, + * the System Control Space (system registers), the systick timer, + * and for CPUs with the Security extension an NS banked version + * of all of these. + * + * The default behaviour for unimplemented registers/ranges + * (for instance the Data Watchpoint and Trace unit at 0xe0001000) + * is to RAZ/WI for privileged access and BusFault for non-privileged + * access. + * + * The NVIC and System Control Space (SCS) starts at 0xe000e000 * and looks like this: * 0x004 - ICTR * 0x010 - 0xff - systick @@ -2741,32 +2790,39 @@ static void armv7m_nvic_realize(DeviceState *dev, E= rror **errp) * generally code determining which banked register to use should * use attrs.secure; code determining actual behaviour of the system * should use env->v7m.secure. + * + * The container covers the whole PPB space. Within it the priority + * of overlapping regions is: + * - default region (for RAZ/WI and BusFault) : -1 + * - system register regions : 0 + * - systick : 1 + * This is because the systick device is a small block of registers + * in the middle of the other system control registers. */ - regionlen =3D arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x= 1000; - memory_region_init(&s->container, OBJECT(s), "nvic", regionlen); - /* The system register region goes at the bottom of the priority - * stack as it covers the whole page. - */ + memory_region_init(&s->container, OBJECT(s), "nvic", 0x100000); + memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s, + "nvic-default", 0x100000); + memory_region_add_subregion_overlap(&s->container, 0, &s->defaultmem, = -1); memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s, "nvic_sysregs", 0x1000); - memory_region_add_subregion(&s->container, 0, &s->sysregmem); + memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem); =20 memory_region_init_io(&s->systickmem, OBJECT(s), &nvic_systick_ops, s, "nvic_systick", 0xe0); =20 - memory_region_add_subregion_overlap(&s->container, 0x10, + memory_region_add_subregion_overlap(&s->container, 0xe010, &s->systickmem, 1); =20 if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), &nvic_sysreg_ns_ops, &s->sysregmem, "nvic_sysregs_ns", 0x1000); - memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_= mem); + memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_= mem); memory_region_init_io(&s->systick_ns_mem, OBJECT(s), &nvic_sysreg_ns_ops, &s->systickmem, "nvic_systick_ns", 0xe0); - memory_region_add_subregion_overlap(&s->container, 0x20010, + memory_region_add_subregion_overlap(&s->container, 0x2e010, &s->systick_ns_mem, 1); } =20 --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823126; cv=none; d=zohomail.com; s=zohoarc; b=lfF4ILk/cZoZ8g1vnqD5cDoii2gpNLleVsxqR7iia1Ol55w9PTN16QNFu4R62N54kl7L/2UAKFl7MyIzAUhVK1w6z2YNquZuLXJxR1lDFrL8a+/3r/XkPa5g+1wgq0xynY9VTmXBLyPTGXkcs1caVz1m9WXl9pm1xEZB3PWfcI4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823126; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZiwH0dK+VVu6UtQJw9p4MqrlmBuqaVE13BH2luYxZGk=; b=T3y2zy/MV6CjYv4sL1XsdxPPeG1fyZpGBrxV6Kkj9tiUKNTIDJf85O0yL5DXPp061SGliIuCH331eQWQwxkgxFuc+ak3fnkAWTE6JBsMHd6hePGHhjfzFX9lWZViiunyxXyYR4Z/z/yaOsivyRbi4kJapS35jocW9I7HF0mHqwQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605823126773817.1389263967412; Thu, 19 Nov 2020 13:58:46 -0800 (PST) Received: from localhost ([::1]:46056 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfrwy-0002UQ-9f for importer@patchew.org; Thu, 19 Nov 2020 16:58:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfruj-0000X5-Fd for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:25 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:42540) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfruh-00046i-Rb for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:25 -0500 Received: by mail-wr1-x441.google.com with SMTP id l1so7973129wrb.9 for ; Thu, 19 Nov 2020 13:56:23 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZiwH0dK+VVu6UtQJw9p4MqrlmBuqaVE13BH2luYxZGk=; b=jN0O4zfSV09LrhoUHY2/AcM5y09yCegdaR5fy5I2uyf/2rHTksoyaSLAEOOQs+W8Zq BeltieDBmjmoRIjf47RoiCAtT2SWgSrWv4PYiZoZ7EoaWz60GuwIBF/8pCqy5eHcqzTY EN+ScJc2qXVe8VDpuGA6+bLaFcx6ilIl0Nhu452DG87g+sEJEtMWhHuiqCIHGw+Yy0ci wQ28INoPPZfIvYz5CdQu1ajlsdTexWdlCfZb+rjGGmmt74PBCCc9OLRcj+svSWVCv/T6 ADaudts52w5ri7rCndZanw8bAKzfORRGg4t4EBik8thVb6WLk51DH0b8Hfb1QBYXZSlk nNeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZiwH0dK+VVu6UtQJw9p4MqrlmBuqaVE13BH2luYxZGk=; b=jp2HEEY9dlX/yq2d3Te8InB5Yur90W6gEnoX1aANdNoCyZ1OIwrIL1BPT0rsxIQDdb MgawuA9Dci9S/x/KoBbAwXHHsZP9VZ8v8g/Ebt3uiRHDbKYbw+SEWMm4LYFHTEvF3wqE vTdzgtRzOOkDaRnx1caOHlp0eX9d3jnN9U+hLIockstiz3j5Kptjt2rFtDAFu1SFzfUR lWhXisROHPvJ3+HneC/I19Tg5jD4rw/xj5DxoJA2WpFDwUzAlV2GCnZWp6YhNzZNKEIh pt4/c+C4Ssh6ETHcYcxwDMW7deOSlpi+ehaZNCoDFDOftLiw3nAIPhUFy4WFxwZvh2b6 Rq3g== X-Gm-Message-State: AOAM533HsnYrQs8ryRYpKQXZB2Zcr1iH5kN+AH/mm7ImqoGTkIyVG810 nXVmS5oYwC8VuyKvNw+Qpns2KQ== X-Google-Smtp-Source: ABdhPJxTc3yQgatgZPYYHQ80jT3c+9LAJdlB0U0Q9HQ4koAxyOdBq6nR9vNUjWZb0RTDyZ1ulvm7TA== X-Received: by 2002:a5d:5689:: with SMTP id f9mr11959050wrv.181.1605822982568; Thu, 19 Nov 2020 13:56:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 02/28] target/arm: Implement v8.1M PXN extension Date: Thu, 19 Nov 2020 21:55:51 +0000 Message-Id: <20201119215617.29887-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In v8.1M the PXN architecture extension adds a new PXN bit to the MPU_RLAR registers, which forbids execution of code in the region from a privileged mode. This is another feature which is just in the generic "in v8.1M" set and has no ID register field indicating its presence. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 11b0803df72..abc470d9f17 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11754,6 +11754,11 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t = address, } else { uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); + bool pxn =3D false; + + if (arm_feature(env, ARM_FEATURE_V8_1M)) { + pxn =3D extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); + } =20 if (m_is_system_region(env, address)) { /* System space is always execute never */ @@ -11761,7 +11766,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, } =20 *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); - if (*prot && !xn) { + if (*prot && !xn && !(pxn && !is_user)) { *prot |=3D PAGE_EXEC; } /* We don't need to look the attribute up in the MAIR0/MAIR1 --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823265; cv=none; d=zohomail.com; s=zohoarc; b=LMRQRf33EWWM14uYoNcUeqog6Uj/ADTQHc3KlC4TVGIkm+NuG7Ox/WjHgK6O9sF0gSO5NsAz90hHx4EtagaX8UWHAhwCp8XtCswEFEXuVIIoMHqNIyF+bW1RydU66bhOVY/nn9bbzJH6Oc8moGmaszO8hPl/5iWB4JcgBx+6KnY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823265; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IjiHnjxng4qMR4/+51zXvM9fbADFjqwqCwPbseLYFWc=; b=Uh7IMRf2k38GAuPqtIoBDpEDt0Sl3CjcXU7PKMCTt3y20o67wN8kftRWU0hSo+4/G27jUWNtpJGbVBV+qAeihsDLmmcNSdiqlarIOTl09DqCMiATzi1xdkKHGGhlLJPVcsp+dnxzHXsvLEDDkS10MCA+GmNM21MZldwcLpqp7Oc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16058232652111020.9577406741054; Thu, 19 Nov 2020 14:01:05 -0800 (PST) Received: from localhost ([::1]:54600 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfrzD-00063G-SC for importer@patchew.org; Thu, 19 Nov 2020 17:01:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51062) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrul-0000Zq-Vm for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:28 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:37518) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfruj-00047g-3K for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:27 -0500 Received: by mail-wr1-x429.google.com with SMTP id b6so8026496wrt.4 for ; Thu, 19 Nov 2020 13:56:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=IjiHnjxng4qMR4/+51zXvM9fbADFjqwqCwPbseLYFWc=; b=eYFPt3srek3zQ8w4Om5FwGBb4agU4HegOwCQderXl5I+EtXCcTNYKmId19umWYYk+n 207mp0fmYsARpgPGu6AGLS7T8b76vbwX0i74LwRUcV4jGbwr71RfOfkZbEuvmElrDqD1 iJtcfspdh+y6MBhqF9axptE/9bqtDWE668WhtOaJdr5BaYJ7Jdc0CfT2IrslPNNn5tZK W5xOX3Q3vdmowewCNUvCTcnU+s+g6blYmWugi+C6k0ktRMCum3WTjY2T1A4bCHOBASH/ R/qflPc96a95knU3yB2zPxxAho5foLYz8OjRde3ch+cqYKYHwONvooZrPN1fjwU9BWsP pyYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IjiHnjxng4qMR4/+51zXvM9fbADFjqwqCwPbseLYFWc=; b=HKkC8/2XxwoX/x61VyQBhJ6qHKOPgDLxMIWYdz/k4h0KwM7f90AYU0tYVWdvjcnt00 uNb0BmZBFYe433Rf9siBM+iBmLviDOz6gGRuk98k5jRKlPyifRarle0jxRdbgeBKD64a 8rdPhF6R5vbZm1caL0VoGaSgo8XrAvKfdv/Vum28YHNMXhff7BnPmwyceGGwEmqG3UAA Cnvfc81MqgbNtNhr/zhSvq4d7CuhSQE2s/efzm3UDpZCyfvJE9rOXej9xWXZdfT9rsSv V9QfPifsHGehMQAtGIRiohz6661reD1Bc/NJ07PEkMcj0ij7FgJSJdVcI4qOBVLOqnFH mj0A== X-Gm-Message-State: AOAM531Ks8Bg6wq3H9Jkbkt8JhvnwoXeUDzatKVS0VI25iLANWDgDBxA 5XoGBcYxmFKrp5QKJZqcxndl3Q== X-Google-Smtp-Source: ABdhPJyYnPU5D4csu7D0UDvEMH17K8t8n65qVkaRe3Xq2mnsO0M+5KBHNiYqgYX99s+0R0OAjHQV4w== X-Received: by 2002:adf:a549:: with SMTP id j9mr12399249wrb.199.1605822983760; Thu, 19 Nov 2020 13:56:23 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 03/28] target/arm: Don't clobber ID_PFR1.Security on M-profile cores Date: Thu, 19 Nov 2020 21:55:52 +0000 Message-Id: <20201119215617.29887-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In arm_cpu_realizefn() we check whether the board code disabled EL3 via the has_el3 CPU object property, which we create if the CPU starts with the ARM_FEATURE_EL3 feature bit. If it is disabled, then we turn off ARM_FEATURE_EL3 and also zero out the relevant fields in the ID_PFR1 and ID_AA64PFR0 registers. This codepath was incorrectly being taken for M-profile CPUs, which do not have an EL3 and don't set ARM_FEATURE_EL3, but which may have the M-profile Security extension and so should have non-zero values in the ID_PFR1.Security field. Restrict the handling of the feature flag to A/R-profile cores. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 07492e9f9a4..40f3f798b2b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1674,7 +1674,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } } =20 - if (!cpu->has_el3) { + if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) { /* If the has_el3 CPU property is disabled then we need to disable= the * feature. */ --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823499; cv=none; d=zohomail.com; s=zohoarc; b=FKEQSUy1WjOJPSU98zX1+TjCO4KfHCOKpP0EwfUna9yoHcQJ3b/1OraJqVG7+VroSfG9fzsCkrnDtoMT1SjpfgQQL8I2YpAq5PxUEfiGgClEfDx7QW8mHmIQRxrjKQuNKyp0pMXUAw9Oulrp8Ot0RTYryaGausGwfTnbYW06Tig= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823499; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6ZUEsNLnkcWrUFTIwzA/F8jefuZJiQAaCiyi3H4CQDk=; b=N7s2oXZGid9cpQVlWHLe0ZxCYArf7/EHXx3j+gedQHt8Z921YZGhA7ssj+jrefQd2tBOXVix4n+UD7JHoiZ2l8CXw+m7sF835sBDxMoIxds345UZqO6S4rtYHWBqSnUgOZZgHY3Ljr9AfHoyMpnIP78CmMGmWGcwBh2dvsIAV6g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605823499872889.2020350565265; Thu, 19 Nov 2020 14:04:59 -0800 (PST) Received: from localhost ([::1]:36006 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfs30-0001cY-Jd for importer@patchew.org; Thu, 19 Nov 2020 17:04:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51070) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrum-0000an-9j for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:28 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:34281) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfruk-00047v-5j for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:28 -0500 Received: by mail-wr1-x42d.google.com with SMTP id r17so8059430wrw.1 for ; Thu, 19 Nov 2020 13:56:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6ZUEsNLnkcWrUFTIwzA/F8jefuZJiQAaCiyi3H4CQDk=; b=OXGhp5s//6VwqHwYzKZD0fmVFg2mZv7f4BtWyVhhd/IzqjvbOeZNiAWIuaCqjHtZ5U H9PriM6SC3nmucTaskw7YlrKBNKwHGO5ht/mgd9OMmDK7wa3QscxvWAVon06DTJbG5Zv gq5AreQ70jaYPaFvTvB3AlKOLAB8p42RuN6jNZsqdV9M3zD5mnLowLjQePMrhIhu3+68 pJKaErh++gOc1yvl1PaE8JDZ7d4v+BhVXkR2g51QY8r6TJyqX45XHuDw6a+kLMRFZRh4 NfqvbTzv1DakET1pfw1zm7hMLq9y6foexbd64GhA84A3SwWNhBZUk9trr1AHTLz0JiTX OtEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6ZUEsNLnkcWrUFTIwzA/F8jefuZJiQAaCiyi3H4CQDk=; b=bVzng6x0fOnxGgnQvjaEfbxuIUxnU5nv023J6z6cx/o8h9oGzRcaKIm5k4DzNSFpxN DSJD173IfJEQQ8vwME08clRM/fvbrcgDQY0ypBvLxLnHnUBRd2mMRVDdY08FrE9c9lBe ymJX1mZPgHGg3T2XFReHqGe8dmp4C04169cukEboSNBvUBxAfAJb0PRYMKhO0eS5eIMw YUMUq6eei4FI5Pj9iNTBQ05/5scHSiOj68Nl5dChHnocP3GRkhGQuC04inRuZKtCVdM6 ByyoogFnb0LlSSTH82FhbxmQ6Fl1H3XBzglDN/cUB7JABfGwclFXMRqqqzPgNR9r5xhX 7b6Q== X-Gm-Message-State: AOAM530rGhEH7//4A9gRDXoirxi6g9QlyCY9/2NKq4Kb3xOrXvJ3ej/P seUDEIGWKmV+1feyASAdqbHSaQ== X-Google-Smtp-Source: ABdhPJxhHeHLzzaOnn/pWZIgh10DABqluBMaiek+pXyKckHE0Z7JhbMmnmW/oLcgBBc+sn3jYb75Vg== X-Received: by 2002:a05:6000:11c2:: with SMTP id i2mr10628297wrx.21.1605822984741; Thu, 19 Nov 2020 13:56:24 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 04/28] target/arm: Implement VSCCLRM insn Date: Thu, 19 Nov 2020 21:55:53 +0000 Message-Id: <20201119215617.29887-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the v8.1M VSCCLRM insn, which zeros floating point registers if there is an active floating point context. This requires support in write_neon_element32() for the MO_32 element size, so add it. Because we want to use arm_gen_condlabel(), we need to move the definition of that function up in translate.c so it is before the #include of translate-vfp.c.inc. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 9 ++++ target/arm/m-nocp.decode | 8 +++- target/arm/translate.c | 21 +++++---- target/arm/translate-vfp.c.inc | 84 ++++++++++++++++++++++++++++++++++ 4 files changed, 111 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e5514c82862..11400a9d248 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3555,6 +3555,15 @@ static inline bool isar_feature_aa32_mprofile(const = ARMISARegisters *id) return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) !=3D 0; } =20 +static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id) +{ + /* + * Return true if M-profile state handling insns + * (VSCCLRM, CLRM, FPCTX access insns) are implemented + */ + return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >=3D 3; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* Sadly this is encoded differently for A-profile and M-profile */ diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode index 28c8ac6b94c..ccd62e8739a 100644 --- a/target/arm/m-nocp.decode +++ b/target/arm/m-nocp.decode @@ -29,13 +29,17 @@ # If the coprocessor is not present or disabled then we will generate # the NOCP exception; otherwise we let the insn through to the main decode. =20 +%vd_dp 22:1 12:4 +%vd_sp 12:4 22:1 + &nocp cp =20 { # Special cases which do not take an early NOCP: VLLDM and VLSTM VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 - # TODO: VSCCLRM (new in v8.1M) is similar: - #VSCCLRM 1110 1100 1-01 1111 ---- 1011 ---- ---0 + # VSCCLRM (new in v8.1M) is similar: + VSCCLRM 1110 1100 1.01 1111 .... 1011 imm:7 0 vd=3D%vd_dp size=3D3 + VSCCLRM 1110 1100 1.01 1111 .... 1010 imm:8 vd=3D%vd_sp size=3D2 =20 NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- &nocp diff --git a/target/arm/translate.c b/target/arm/translate.c index 6d04ca3a8a0..9f2b6018a21 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -100,6 +100,15 @@ void arm_translate_init(void) a64_translate_init(); } =20 +/* Generate a label used for skipping this instruction */ +static void arm_gen_condlabel(DisasContext *s) +{ + if (!s->condjmp) { + s->condlabel =3D gen_new_label(); + s->condjmp =3D 1; + } +} + /* Flags for the disas_set_da_iss info argument: * lower bits hold the Rt register number, higher bits are flags. */ @@ -1221,6 +1230,9 @@ static void write_neon_element64(TCGv_i64 src, int re= g, int ele, MemOp memop) long off =3D neon_element_offset(reg, ele, memop); =20 switch (memop) { + case MO_32: + tcg_gen_st32_i64(src, cpu_env, off); + break; case MO_64: tcg_gen_st_i64(src, cpu_env, off); break; @@ -5156,15 +5168,6 @@ static void gen_srs(DisasContext *s, s->base.is_jmp =3D DISAS_UPDATE_EXIT; } =20 -/* Generate a label used for skipping this instruction */ -static void arm_gen_condlabel(DisasContext *s) -{ - if (!s->condjmp) { - s->condlabel =3D gen_new_label(); - s->condjmp =3D 1; - } -} - /* Skip this instruction if the ARM condition is false */ static void arm_skip_unless(DisasContext *s, uint32_t cond) { diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 96948f5a2d3..2a67ed0f6e2 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -3406,6 +3406,90 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_V= LLDM_VLSTM *a) return true; } =20 +static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) +{ + int btmreg, topreg; + TCGv_i64 zero; + TCGv_i32 aspen, sfpa; + + if (!dc_isar_feature(aa32_m_sec_state, s)) { + /* Before v8.1M, fall through in decode to NOCP check */ + return false; + } + + /* Explicitly UNDEF because this takes precedence over NOCP */ + if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) { + unallocated_encoding(s); + return true; + } + + if (!dc_isar_feature(aa32_vfp_simd, s)) { + /* NOP if we have neither FP nor MVE */ + return true; + } + + /* + * If FPCCR.ASPEN !=3D 0 && CONTROL_S.SFPA =3D=3D 0 then there is no + * active floating point context so we must NOP (without doing + * any lazy state preservation or the NOCP check). + */ + aspen =3D load_cpu_field(v7m.fpccr[M_REG_S]); + sfpa =3D load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK); + tcg_gen_or_i32(sfpa, sfpa, aspen); + arm_gen_condlabel(s); + tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel); + + if (s->fp_excp_el !=3D 0) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); + return true; + } + + topreg =3D a->vd + a->imm - 1; + btmreg =3D a->vd; + + /* Convert to Sreg numbers if the insn specified in Dregs */ + if (a->size =3D=3D 3) { + topreg =3D topreg * 2 + 1; + btmreg *=3D 2; + } + + if (topreg > 63 || (topreg > 31 && !(topreg & 1))) { + /* UNPREDICTABLE: we choose to undef */ + unallocated_encoding(s); + return true; + } + + /* Silently ignore requests to clear D16-D31 if they don't exist */ + if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) { + topreg =3D 31; + } + + if (!vfp_access_check(s)) { + return true; + } + + /* Zero the Sregs from btmreg to topreg inclusive. */ + zero =3D tcg_const_i64(0); + if (btmreg & 1) { + write_neon_element64(zero, btmreg >> 1, 1, MO_32); + btmreg++; + } + for (; btmreg + 1 <=3D topreg; btmreg +=3D 2) { + write_neon_element64(zero, btmreg >> 1, 0, MO_64); + } + if (btmreg =3D=3D topreg) { + write_neon_element64(zero, btmreg >> 1, 0, MO_32); + btmreg++; + } + assert(btmreg =3D=3D topreg + 1); + /* TODO: when MVE is implemented, zero VPR here */ + return true; +} + static bool trans_NOCP(DisasContext *s, arg_nocp *a) { /* --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823362; cv=none; d=zohomail.com; s=zohoarc; b=alXtFbOaDjz+QES4+d5wHWWIbyUCsEA1MgEBrFdKIYDq6Ig4aMxX1boScTfTCj9zJlPUMCYHw25/zs6A/gJ0/CgFycq0H/wkKcE1aDy3U5M399f9nTcU7TwrhrFL3NODAM3OBe3wN91C6d3ENTEgR87zaX46rXTrKTIG0XVCXUg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Geuo7aDlDntl9E+BThf4Sp6VC9Xi1ojKJ4sXKRlUeWo=; b=JdH587DAedQ+MR5KaQmfLjoDSs7/agOQHmuT6/EJfhzf3xwW81Flu2A2OHxY/6vEGK vVN18Dkgbr0yVm9hNdJ3xW5KgbxKAt27xtXNje7GiCEpBByB1uZo2E+xB2yQ40UDZfKD kTQX9PB8f3vBdyEk4GX4nmtmwp6N63jLk++9eM5VXmIngflVEKOStewieoNvpRmjzDcM BCeHDEAUkjpb6/Hbh3OB/f8OITAq+CjOtdXirDCuGUw4Ypd9vr1hWI1qAew/p+uNHA6z fARb183/ML4PDu+9Q7e1KNh1aOh3Cknsxn+3IHLELwbQTjbw6orE8MToU9Ne0zB2Xs9F SCTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Geuo7aDlDntl9E+BThf4Sp6VC9Xi1ojKJ4sXKRlUeWo=; b=eo7czMOUb6CUhViiQrBGlGuvVv4fjO9z8EG00YULajPd7bmcWyORk7BBlQiJ9I6ibE TZgEca5HkzaBZiZ5LRt0JJnAoOvlMpf8IlzGyP902R7pQezmHfe8vvC90+WLpXyEEZM1 dqLz94u038yMbYFurKJqbn1yhES2gWHrDFd+qs4vurzRcbC45ehx4pLft1ztT8hDUL07 2nDfcLa5PZAP4p7rWLar1mjNyv2sxGjea+H/Y/CjUt9aqnvbsh86VJwtcVIJjTblWn6z KyJpvfiYBEJZla/ax8EN7VhCPKi/HBJTE2a3IlnuKHe9JVaEe+4ArpMQNDL0YWR4JctC AxoA== X-Gm-Message-State: AOAM53002tdxYJkwoNE3cDNDnwnNWyJFXw6sUZ7YLhHX7sp5UnRp6YNZ kNOIYFROjKAzJRTyGBzDBvHlGw== X-Google-Smtp-Source: ABdhPJyCdxkj3DFBUYd1D3h/aiunzKZaf4sOByuhQg1u8wES0KZxL7nPVrurSkllNvqZg182neTbQg== X-Received: by 2002:a5d:4802:: with SMTP id l2mr12095180wrq.424.1605822985894; Thu, 19 Nov 2020 13:56:25 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 05/28] target/arm: Implement CLRM instruction Date: Thu, 19 Nov 2020 21:55:54 +0000 Message-Id: <20201119215617.29887-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In v8.1M the new CLRM instruction allows zeroing an arbitrary set of the general-purpose registers and APSR. Implement this. The encoding is a subset of the LDMIA T2 encoding, using what would be Rn=3D0b1111 (which UNDEFs for LDMIA). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/t32.decode | 6 +++++- target/arm/translate.c | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/target/arm/t32.decode b/target/arm/t32.decode index cfcc71bfb0a..f045eb62c84 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -609,7 +609,11 @@ UXTAB 1111 1010 0101 .... 1111 .... 10.. ..= .. @rrr_rot =20 STM_t32 1110 1000 10.0 .... ................ @ldstm i=3D1= b=3D0 STM_t32 1110 1001 00.0 .... ................ @ldstm i=3D0= b=3D1 -LDM_t32 1110 1000 10.1 .... ................ @ldstm i=3D1= b=3D0 +{ + # Rn=3D15 UNDEFs for LDM; M-profile CLRM uses that encoding + CLRM 1110 1000 1001 1111 list:16 + LDM_t32 1110 1000 10.1 .... ................ @ldstm i=3D1= b=3D0 +} LDM_t32 1110 1001 00.1 .... ................ @ldstm i=3D0= b=3D1 =20 &rfe !extern rn w pu diff --git a/target/arm/translate.c b/target/arm/translate.c index 9f2b6018a21..47a1a5739c8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7968,6 +7968,44 @@ static bool trans_LDM_t16(DisasContext *s, arg_ldst_= block *a) return do_ldm(s, a, 1); } =20 +static bool trans_CLRM(DisasContext *s, arg_CLRM *a) +{ + int i; + TCGv_i32 zero; + + if (!dc_isar_feature(aa32_m_sec_state, s)) { + return false; + } + + if (extract32(a->list, 13, 1)) { + return false; + } + + if (!a->list) { + /* UNPREDICTABLE; we choose to UNDEF */ + return false; + } + + zero =3D tcg_const_i32(0); + for (i =3D 0; i < 15; i++) { + if (extract32(a->list, i, 1)) { + /* Clear R[i] */ + tcg_gen_mov_i32(cpu_R[i], zero); + } + } + if (extract32(a->list, 15, 1)) { + /* + * Clear APSR (by calling the MSR helper with the same argument + * as for "MSR APSR_nzcvqg, Rn": mask =3D 0b1100, SYSM=3D0) + */ + TCGv_i32 maskreg =3D tcg_const_i32(0xc << 8); + gen_helper_v7m_msr(cpu_env, maskreg, zero); + tcg_temp_free_i32(maskreg); + } + tcg_temp_free_i32(zero); + return true; +} + /* * Branch, branch with link */ --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823333; cv=none; d=zohomail.com; s=zohoarc; b=ea0mjh+5+wo8ivrTlxecagzYfckf0f65Oy15n3BW19eZPZSHfEf+Yr88gdVfRK46PtkkYliTsl6hmtTWGF3YW1gy1iI7JVuP0FaNrHb8fnEKfQdTfoK/5Co6E701J8sWMDXI1J23oo3huic5pu/Ho/iPWDqaahhb8ydcwPzsOKc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823333; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8+XlTYUesFmn7xGnqY89ywEYlA7oUC0DSrJvhHCe1y4=; b=XCINxBITJMmBPQ76yEm4IknM4BE+Uh9IXq3nXOASwEhSFavuE4bUGqStz+V7Utz0UTM3CS4hirtyPiGZjcIjCc+0rciCc208raloWPsaX59SHtRCD9Xs28/wdBDohEwble1Ep982U7g1xARZ0Bu0E4AtKlEjEDfHDHafkprP7QI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605823333751898.6024034140543; Thu, 19 Nov 2020 14:02:13 -0800 (PST) Received: from localhost ([::1]:56002 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfs0K-0006d2-JQ for importer@patchew.org; Thu, 19 Nov 2020 17:02:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfruo-0000eP-5E for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:30 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:44550) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrum-00049C-CB for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:29 -0500 Received: by mail-wr1-x443.google.com with SMTP id c17so7955075wrc.11 for ; Thu, 19 Nov 2020 13:56:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8+XlTYUesFmn7xGnqY89ywEYlA7oUC0DSrJvhHCe1y4=; b=ATAp569PDfzF+YrpxcB6+d0W5+Qs7SQLOV01UCKfalb3Wk2I0l6p4oezdQMcz12Nmw aku+dW0JakM0KX/QrjWx8sTSFyejhwA8QQrbmHHGAslL6X8r8b3QsP0vShhiRhtNGEXK NIJ0aeDl9cin3F+/ywHunUKKMUXC4gKMtOtaJvE1poz3fiYihfhGwZ7acp++0AnrDVV6 xEJYCSYPGwAjVSrVTcNdTKffqHU1TRgim5aEfvAx8J5ahb0JFGe4Dre5FnZLhymrhUvm QeAUvXt3oMOE1VMnvPy15jn0511OS9Hcm7fXp3I3+CxJIkd5pUUZcmf5Hz8lqXwjjmNL zJtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8+XlTYUesFmn7xGnqY89ywEYlA7oUC0DSrJvhHCe1y4=; b=PJBIqQuJlqAOTbGiU+rFcNE0b6/pBam8vEdQ5UHcPaYuXKejj1mTHD3deeyzXKA7kv D7sBjdPsUnmURoeghcqZ3jpO6kcyqp7woQcxbk/wgHN2supS7FofBvC26SNIbDxQ2YJI Ki79fY7QnhfWdFI/X6dCBALyx9J2/6yBsT9LFkF735J8G5Sudf8jsuI2BD5/b5COIPvR hMLu5X+pVvfkRbs/msbzPEf176+vSrOIygmz9CdGoUueRA5mI9FBGnHTQQs8NWukxc+1 gZ9e3yXWL4Z1Awoc2IMab6mOplKPJeOLiaPrh50wXxLrBzG2i4W4iWUfWlxV7eLhRGw2 DV4A== X-Gm-Message-State: AOAM531256cNwuhmfq5b7qCRgc6s7+MIyuM6F4SCsY3FI3lqQW7HuunR gqEePxXkMHTwaAISN8ASO/G4gw== X-Google-Smtp-Source: ABdhPJw7PLQ9P5KkIr+Ie6Bru5iOxMKzRF6VZdnhMJ34538L3QOm20eKoAwsL40dcVI80QnlxU9QsQ== X-Received: by 2002:a5d:51cd:: with SMTP id n13mr11931796wrv.87.1605822986900; Thu, 19 Nov 2020 13:56:26 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 06/28] target/arm: Enforce M-profile VMRS/VMSR register restrictions Date: Thu, 19 Nov 2020 21:55:55 +0000 Message-Id: <20201119215617.29887-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For M-profile before v8.1M, the only valid register for VMSR/VMRS is the FPSCR. We have a comment that states this, but the actual logic to forbid accesses for any other register value is missing, so we would end up with A-profile style behaviour. Add the missing check. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.c.inc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 2a67ed0f6e2..e100182a32c 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -622,7 +622,10 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_= VMRS *a) * Accesses to R15 are UNPREDICTABLE; we choose to undef. * (FPSCR -> r15 is a special case which writes to the PSR flags.) */ - if (a->rt =3D=3D 15 && (!a->l || a->reg !=3D ARM_VFP_FPSCR)) { + if (a->reg !=3D ARM_VFP_FPSCR) { + return false; + } + if (a->rt =3D=3D 15 && !a->l) { return false; } } --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823175; cv=none; d=zohomail.com; s=zohoarc; b=PsnIj4ld4aXDS95LWQckrgFr76atjcZDQxpIWToHU+3f8ythg9iTiuFV8MtTnm2+N6FLNzpi476zqRM6EG+aKDzW1mqJbfTHc0jJ4p2xLlCu+sEwybrfxqjZX84kfIdbtnWWE+y+v2tkiA4AGZcMt37LBoit0AVNQ8VL2ZGOye8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823175; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ldCy4DDuaD1wPIoSnJu2ePFEefVEzvaqh++kwHOTnPk=; b=ac5cMDz/CEi3IHDoI0qTm34zU8jJGDm7bHTPf7YMsERzA7jAMcCpLj4I2B/KRzLEYogj9jM8K0QzHht+l2Rs7xDmYVxVzp4n7VjClQalXpvjsRfTy25YQEMXvOVOjNGIHfIPUteWDnHiyfSrAuu7HKj+Z4eQOot3nB/1HEbLNYg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605823175071248.51960058170914; Thu, 19 Nov 2020 13:59:35 -0800 (PST) Received: from localhost ([::1]:49556 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfrxl-0003sx-RS for importer@patchew.org; Thu, 19 Nov 2020 16:59:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51166) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrup-0000hA-V4 for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:31 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:38769) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrun-00049a-Ip for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:31 -0500 Received: by mail-wr1-x429.google.com with SMTP id p8so8018714wrx.5 for ; Thu, 19 Nov 2020 13:56:29 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ldCy4DDuaD1wPIoSnJu2ePFEefVEzvaqh++kwHOTnPk=; b=ghvHk2zN5ps4XzgRTRiPnV+I9VY0xcL3xMTUTqIKj2LD0HWYWhHznMa106OJyP+Tku YvZ+4gxylw7j7m9Pm9G5Z8AlHIt0SqcIYBPwY3PHuiQXiT06XL326DkApNrAQ2UMS3qS WIJUypz1ZhP6qGBCE1Ieyx0mEoT2SkG7moBNnWrJDZEe0j6Py+gnXGTO2E6AYChcpBiV QXaiqXgNV1q566SENiW4cRVvEqtAZtV/j9VnbDO6vBisZUoxkxtfTLnD26GD3JIyKcGe EjwmDNngkoQWVFaX8bElcgUc24GVhci4wBwC0q+ZgbTP6T8QU57r3BwSEtKb8MkahbKH 1mkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ldCy4DDuaD1wPIoSnJu2ePFEefVEzvaqh++kwHOTnPk=; b=oIYwWqW38CGUPzDCsO6/uZjLhzxr9u9fy95cyiutd2emxQicCI/1/mWJmQmgGv3KZN Hkj3eZ1nR+s6VHllKUCOK01B9XtNjumwoJSd0wJMZSYX4ymbfTN6B0J2Ew73+fOMHYks s8gTkbZikcjZQ2jHCrMKWabr0QleMiPApYsI3TEOsrHf80blWxXwpqbOIbTyjvbK0fby pAb/yTwr+LNnwQKIp1TfH4tFTFDr/3ZXAvDCiU4TarfogUAgoQi1Iv7Tkv4I+UXX0p4F vPzMOwu/bLPVA9+aLnwXWWevgpDHwT8UDlxIqujS74tNhjPuAwszGVD8Bci0vhxmEMtt QNgQ== X-Gm-Message-State: AOAM532JEheN/cUICpa2NEwlFgvKaPlpFsbV5M1VnhBISE09cJjguMte PmV2Q1cirR1/ykS5xXRTNlyi+A== X-Google-Smtp-Source: ABdhPJxrT3FK5gSxYnKMt6Ae78u/V9cZcFvPjMQ1uL+pGjASI6Kq1cPVuBEH9a8W/57Tucw56XcOEw== X-Received: by 2002:adf:de12:: with SMTP id b18mr12890957wrm.187.1605822988219; Thu, 19 Nov 2020 13:56:28 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 07/28] target/arm: Refactor M-profile VMSR/VMRS handling Date: Thu, 19 Nov 2020 21:55:56 +0000 Message-Id: <20201119215617.29887-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Currently M-profile borrows the A-profile code for VMSR and VMRS (access to the FP system registers), because all it needs to support is the FPSCR. In v8.1M things become significantly more complicated in two ways: * there are several new FP system registers; some have side effects on read, and one (FPCXT_NS) needs to avoid the usual vfp_access_check() and the "only if FPU implemented" check * all sysregs are now accessible both by VMRS/VMSR (which reads/writes a general purpose register) and also by VLDR/VSTR (which reads/writes them directly to memory) Refactor the structure of how we handle VMSR/VMRS to cope with this: * keep the M-profile code entirely separate from the A-profile code * abstract out the "read or write the general purpose register" part of the code into a loadfn or storefn function pointer, so we can reuse it for VLDR/VSTR. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 3 + target/arm/translate-vfp.c.inc | 181 ++++++++++++++++++++++++++++++--- 2 files changed, 170 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 11400a9d248..ad8b80c667d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1569,6 +1569,9 @@ enum arm_cpu_mode { #define ARM_VFP_FPINST 9 #define ARM_VFP_FPINST2 10 =20 +/* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ +#define QEMU_VFP_FPSCR_NZCV 0xffff + /* iwMMXt coprocessor control registers. */ #define ARM_IWMMXT_wCID 0 #define ARM_IWMMXT_wCon 1 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index e100182a32c..2d201ad0888 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -607,27 +607,180 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) return true; } =20 +/* + * M-profile provides two different sets of instructions that can + * access floating point system registers: VMSR/VMRS (which move + * to/from a general purpose register) and VLDR/VSTR sysreg (which + * move directly to/from memory). In some cases there are also side + * effects which must happen after any write to memory (which could + * cause an exception). So we implement the common logic for the + * sysreg access in gen_M_fp_sysreg_write() and gen_M_fp_sysreg_read(), + * which take pointers to callback functions which will perform the + * actual "read/write general purpose register" and "read/write + * memory" operations. + */ + +/* + * Emit code to store the sysreg to its final destination; frees the + * TCG temp 'value' it is passed. + */ +typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 val= ue); +/* + * Emit code to load the value to be copied to the sysreg; returns + * a new TCG temporary + */ +typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque); + +/* Common decode/access checks for fp sysreg read/write */ +typedef enum fp_sysreg_check_result { + fp_sysreg_check_failed, /* caller should return false */ + fp_sysreg_check_done, /* caller should return true */ + fp_sysreg_check_continue, /* caller should continue generating code */ +} fp_sysreg_check_result; + +static fp_sysreg_check_result fp_sysreg_checks(DisasContext *s, int regno) +{ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return fp_sysreg_check_failed; + } + + switch (regno) { + case ARM_VFP_FPSCR: + case QEMU_VFP_FPSCR_NZCV: + break; + default: + return fp_sysreg_check_failed; + } + + if (!vfp_access_check(s)) { + return fp_sysreg_check_done; + } + + return fp_sysreg_check_continue; +} + +static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, + fp_sysreg_loadfn *loadfn, + void *opaque) +{ + /* Do a write to an M-profile floating point system register */ + TCGv_i32 tmp; + + switch (fp_sysreg_checks(s, regno)) { + case fp_sysreg_check_failed: + return false; + case fp_sysreg_check_done: + return true; + case fp_sysreg_check_continue: + break; + } + + switch (regno) { + case ARM_VFP_FPSCR: + tmp =3D loadfn(s, opaque); + gen_helper_vfp_set_fpscr(cpu_env, tmp); + tcg_temp_free_i32(tmp); + gen_lookup_tb(s); + break; + default: + g_assert_not_reached(); + } + return true; +} + +static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, + fp_sysreg_storefn *storefn, + void *opaque) +{ + /* Do a read from an M-profile floating point system register */ + TCGv_i32 tmp; + + switch (fp_sysreg_checks(s, regno)) { + case fp_sysreg_check_failed: + return false; + case fp_sysreg_check_done: + return true; + case fp_sysreg_check_continue: + break; + } + + switch (regno) { + case ARM_VFP_FPSCR: + tmp =3D tcg_temp_new_i32(); + gen_helper_vfp_get_fpscr(tmp, cpu_env); + storefn(s, opaque, tmp); + break; + case QEMU_VFP_FPSCR_NZCV: + /* + * Read just NZCV; this is a special case to avoid the + * helper call for the "VMRS to CPSR.NZCV" insn. + */ + tmp =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + storefn(s, opaque, tmp); + break; + default: + g_assert_not_reached(); + } + return true; +} + +static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value) +{ + arg_VMSR_VMRS *a =3D opaque; + + if (a->rt =3D=3D 15) { + /* Set the 4 flag bits in the CPSR */ + gen_set_nzcv(value); + tcg_temp_free_i32(value); + } else { + store_reg(s, a->rt, value); + } +} + +static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque) +{ + arg_VMSR_VMRS *a =3D opaque; + + return load_reg(s, a->rt); +} + +static bool gen_M_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) +{ + /* + * Accesses to R15 are UNPREDICTABLE; we choose to undef. + * FPSCR -> r15 is a special case which writes to the PSR flags; + * set a->reg to a special value to tell gen_M_fp_sysreg_read() + * we only care about the top 4 bits of FPSCR there. + */ + if (a->rt =3D=3D 15) { + if (a->l && a->reg =3D=3D ARM_VFP_FPSCR) { + a->reg =3D QEMU_VFP_FPSCR_NZCV; + } else { + return false; + } + } + + if (a->l) { + /* VMRS, move FP system register to gp register */ + return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_gpr, a); + } else { + /* VMSR, move gp register to FP system register */ + return gen_M_fp_sysreg_write(s, a->reg, gpr_to_fp_sysreg, a); + } +} + static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) { TCGv_i32 tmp; bool ignore_vfp_enabled =3D false; =20 - if (!dc_isar_feature(aa32_fpsp_v2, s)) { - return false; + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return gen_M_VMSR_VMRS(s, a); } =20 - if (arm_dc_feature(s, ARM_FEATURE_M)) { - /* - * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. - * Accesses to R15 are UNPREDICTABLE; we choose to undef. - * (FPSCR -> r15 is a special case which writes to the PSR flags.) - */ - if (a->reg !=3D ARM_VFP_FPSCR) { - return false; - } - if (a->rt =3D=3D 15 && !a->l) { - return false; - } + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; } =20 switch (a->reg) { --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823390; cv=none; d=zohomail.com; s=zohoarc; b=Sg4gb9Xespc+AjWPk5ccbzOmv0qCY1LeWgVUtFm7QZN19N6I14nFsZ/P3CW/X0hocFmHIRUIkdrMsTzdd3qFqEtnYnO/84OBf0Ll4QL+uGHbdgYIvYLBzti4uE/HqnfV7r6XXWiKTYgafUQzVuYNykr77p2ofCvfZgRy7Q9V2bs= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pBBk6mf/A2FWnkWRPu0U5rVmHOGw6pK6O+R7FycG+J4=; b=uKudqnU42FlYuQmcmnn0JAepZ84v+zOrFmL2CBY+tmVuapBpFyIwl1Zw0CMnih7qAv vgmugTgYALwSDZeTBsw5D6PWNDB/R6lhkdO6nLyspdfyEA5WlGYWau0GDTYnfapF0pBC JVn2eUxAqpW0wQC9KVCj7MPkr5d0/nt6HuSatSMMaeN+eJkuL169r7Dxo2KUrcxvsJ0+ x6w3IICBzpB9z2ORWei9kgoEieawgfLYzmylNvwUGcfTTwBJW6afLOqWQnxDDPD+IMN/ N78Y5rRfnpZ1XgEMBfgSWfAfwRsFjOUdo0qx+16kkq+h8Y4Jk0JFp2UbpVKv4rv4feEB leHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pBBk6mf/A2FWnkWRPu0U5rVmHOGw6pK6O+R7FycG+J4=; b=fVikNhA4aeAgNchIgQY65+BiR1tbq4wWg6gDKg/ttp5l8d9hDrS531B4icLbxSAbYf jUoGaen3Lk+N1NJHTPa1sttT3OEPk81ol4aExwlccvnVxgnFkgc5F/r1yArtKFdB9p6h OmgwpWk4OlLF9CY6GsfMQ5FBXVrQoU1TSRulfl2/+C75wwO8IB0drTo8cQI9KnCqVAYQ kU9xqQLwhHKcmrVFkrVJG0u0GfOqu8bGlCqg9nPm43wC+C/3vcYazaZevWEo0e1aO5JQ U1BYEuhflnJ8isO+xoSTHnVg++f5FA/UOsRHn0odDCcIhxNxBC5ce0sNTmxaUf0QYPFs +wtg== X-Gm-Message-State: AOAM532wdfbQq2KELZ8OcSSiM6bh9SN4V2ANpNMVFBdzhwp1bvXtdvWL iDwdY1v7G8pzwqnHZecm3pd6FQ== X-Google-Smtp-Source: ABdhPJxBokBEu1/+aSqCtjTxvUtjxSyJt62dWg6Z3yUPNf8HNvln2e2xVaPmfLCofVwjyhuljsbQ4g== X-Received: by 2002:a7b:c11a:: with SMTP id w26mr6886742wmi.78.1605822989504; Thu, 19 Nov 2020 13:56:29 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 08/28] target/arm: Move general-use constant expanders up in translate.c Date: Thu, 19 Nov 2020 21:55:57 +0000 Message-Id: <20201119215617.29887-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The constant-expander functions like negate, plus_2, etc, are generally useful; move them up in translate.c so we can use them in the VFP/Neon decoders as well as in the A32/T32/T16 decoders. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.c | 46 +++++++++++++++++++++++------------------- 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 47a1a5739c8..f5acd32e76a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -109,6 +109,30 @@ static void arm_gen_condlabel(DisasContext *s) } } =20 +/* + * Constant expanders for the decoders. + */ + +static int negate(DisasContext *s, int x) +{ + return -x; +} + +static int plus_2(DisasContext *s, int x) +{ + return x + 2; +} + +static int times_2(DisasContext *s, int x) +{ + return x * 2; +} + +static int times_4(DisasContext *s, int x) +{ + return x * 4; +} + /* Flags for the disas_set_da_iss info argument: * lower bits hold the Rt register number, higher bits are flags. */ @@ -5177,29 +5201,9 @@ static void arm_skip_unless(DisasContext *s, uint32_= t cond) =20 =20 /* - * Constant expanders for the decoders. + * Constant expanders used by T16/T32 decode */ =20 -static int negate(DisasContext *s, int x) -{ - return -x; -} - -static int plus_2(DisasContext *s, int x) -{ - return x + 2; -} - -static int times_2(DisasContext *s, int x) -{ - return x * 2; -} - -static int times_4(DisasContext *s, int x) -{ - return x * 4; -} - /* Return only the rotation part of T32ExpandImm. */ static int t32_expandimm_rot(DisasContext *s, int x) { --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823500; cv=none; d=zohomail.com; s=zohoarc; b=YHEKgPLs3/5T05vI+GLGpSF8WX7jA1ARcUjinmLxUnlp3UCLjzHGbB7gbH4qcH6cTIkoLhyAaUmwxJnGK9KH3zxkKr5KUPGTNVL7Afu6MbDj3P5EhXi+kE0paT9rDIc1A0z3NCveTV6TicelFtvXsVx9FD769weMyZuYGtJz064= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823500; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=opCzeDjiGx7OhE/oRP6OxBZouGB0q+W7fnmO9TQA2f8=; b=Zhic0Hb1qHBMbDbAQ/lSs4oIKe7rVsrN8tSfpPaEZtOabFtYuub1fskRlr/w3LlBkUWEumu7asWn0d5XbuFVcBuWYw1kLie6mhfuYeq1C8cetyHjbOIyh8h+AWOCfXI9UlmS0vCD6GG8bPcs/ypBb0iCY5IsoAPnAP/BMs9g160= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605823500908526.3037633586655; Thu, 19 Nov 2020 14:05:00 -0800 (PST) Received: from localhost ([::1]:36122 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfs31-0001fS-Kt for importer@patchew.org; Thu, 19 Nov 2020 17:04:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfruy-0000kG-St for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:41 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:51452) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfruq-0004Az-CS for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:35 -0500 Received: by mail-wm1-x344.google.com with SMTP id a186so5772143wme.1 for ; Thu, 19 Nov 2020 13:56:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=opCzeDjiGx7OhE/oRP6OxBZouGB0q+W7fnmO9TQA2f8=; b=DnyxAwOt3qo/5R8xN/DI/1otRLHGaffGampfIR2NhhRfk5rcGxtz9gu5Vv4dSZXWFk AA03zyxijF9rnmIVVHEztuBInt55RxSvWLeKkFlDtf+pzptR2RC4JrA1HF1w72vxrBDv rCYaY5NUJ8rxOpuotB0YV6Wa0QCjLsSuVI9YbwVHlyRyGASf9oXXbVavdn/H35yQYakc owd7hW5daN9Y4wDKhNTFUVbMs1+5IpEYxwVRx0WOW2timUlkYZhiSLjs2Rd0C0LwofCh SDz3vHZKP3fOCDqcK3gDUbDXf/+i/1lifTCNRWWKN3s/7va41XRWJP/Ww+415eyHCBlP 2cKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=opCzeDjiGx7OhE/oRP6OxBZouGB0q+W7fnmO9TQA2f8=; b=phllxMN1Q6PsDnC4zQS3Hb7l1KQ0ufdBYQyGWJdYSduYPgZsrYnaYlJ2nmCQVF//4l ICE/KnagJY3B53nRCWtL/bUpZIcCJ9/+x5bEPc0YtqKfms6aeMfW1MdtcSnjcILqg4Ao kotyMIPvyHNuu6I1prVC7XQGfDPMIDI9TCwcGGUYukV5p1DG81Unm9cycCm4WLra3fZb ZLIhqtXPgSug9Iyc8JnOzNH7xZAb4W1Pq0xeOHAaXdKubKYBZ+B4P2ujc/n9SwzdhQ56 GkVrloH96WxDyXvaX2a7ZYQn3wcnu4vURQjPOU2Aiw+LeX3kDw7baC4RK+5rLz+8sJDu zSaQ== X-Gm-Message-State: AOAM533UBTkY5m6+pBPzBJ5p9xYtAZx1e+OlLwwKbSHDSPkUMb1Xmks7 4O7ylncdnonY53uk7KwxmM94SNGISbdBdw== X-Google-Smtp-Source: ABdhPJxVxPpNphSJK9xbveE4tszKOWjJnL8VpNvHcs7dF0jp3FE7qX8H2VRZXY+Cv5C+w2lpaC1aYA== X-Received: by 2002:a1c:e907:: with SMTP id q7mr6607945wmc.161.1605822990883; Thu, 19 Nov 2020 13:56:30 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 09/28] target/arm: Implement VLDR/VSTR system register Date: Thu, 19 Nov 2020 21:55:58 +0000 Message-Id: <20201119215617.29887-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the new-in-v8.1M VLDR/VSTR variants which directly read or write FP system registers to memory. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/vfp.decode | 14 ++++++ target/arm/translate-vfp.c.inc | 89 ++++++++++++++++++++++++++++++++++ 2 files changed, 103 insertions(+) diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 1300ba045dd..6f7f28f9a46 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -84,6 +84,20 @@ VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 = vd=3D%vd_sp VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=3D%vd_sp VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=3D%vd_dp =20 +# M-profile VLDR/VSTR to sysreg +%vldr_sysreg 22:1 13:3 +%imm7_0x4 0:7 !function=3Dtimes_4 + +&vldr_sysreg rn reg imm a w p +@vldr_sysreg .... ... . a:1 . . . rn:4 ... . ... .. ....... \ + reg=3D%vldr_sysreg imm=3D%imm7_0x4 &vldr_sysreg + +# P=3D0 W=3D0 is SEE "Related encodings", so split into two patterns +VLDR_sysreg ---- 110 1 . . w:1 1 .... ... 0 111 11 ....... @vldr_sysreg p= =3D1 +VLDR_sysreg ---- 110 0 . . 1 1 .... ... 0 111 11 ....... @vldr_sysreg p= =3D0 w=3D1 +VSTR_sysreg ---- 110 1 . . w:1 0 .... ... 0 111 11 ....... @vldr_sysreg p= =3D1 +VSTR_sysreg ---- 110 0 . . 1 0 .... ... 0 111 11 ....... @vldr_sysreg p= =3D0 w=3D1 + # We split the load/store multiple up into two patterns to avoid # overlap with other insns in the "Advanced SIMD load/store and 64-bit mov= e" # grouping: diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 2d201ad0888..dc26759ab95 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -912,6 +912,95 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_= VMRS *a) return true; } =20 +static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 va= lue) +{ + arg_vldr_sysreg *a =3D opaque; + uint32_t offset =3D a->imm; + TCGv_i32 addr; + + if (!a->a) { + offset =3D - offset; + } + + addr =3D load_reg(s, a->rn); + if (a->p) { + tcg_gen_addi_i32(addr, addr, offset); + } + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + gen_aa32_st32(s, value, addr, get_mem_index(s)); + tcg_temp_free_i32(value); + + if (a->w) { + /* writeback */ + if (!a->p) { + tcg_gen_addi_i32(addr, addr, offset); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } +} + +static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque) +{ + arg_vldr_sysreg *a =3D opaque; + uint32_t offset =3D a->imm; + TCGv_i32 addr; + TCGv_i32 value =3D tcg_temp_new_i32(); + + if (!a->a) { + offset =3D - offset; + } + + addr =3D load_reg(s, a->rn); + if (a->p) { + tcg_gen_addi_i32(addr, addr, offset); + } + + if (s->v8m_stackcheck && a->rn =3D=3D 13 && a->w) { + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + gen_aa32_ld32u(s, value, addr, get_mem_index(s)); + + if (a->w) { + /* writeback */ + if (!a->p) { + tcg_gen_addi_i32(addr, addr, offset); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } + return value; +} + +static bool trans_VLDR_sysreg(DisasContext *s, arg_vldr_sysreg *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + if (a->rn =3D=3D 15) { + return false; + } + return gen_M_fp_sysreg_write(s, a->reg, memory_to_fp_sysreg, a); +} + +static bool trans_VSTR_sysreg(DisasContext *s, arg_vldr_sysreg *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + if (a->rn =3D=3D 15) { + return false; + } + return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_memory, a); +} + static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a) { TCGv_i32 tmp; --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Bs7VQGF+Epl5dZ+q3vps3mLgkN/vGMivqNsTt71dwm8=; b=oA7gVbTWZTt37QDLprXb/lVmoFA2pgIdX0su8AJgdOvc9u0nLh65Y8/k6BCiFKGEUR EEMOziIeBspfWQNpB5pG21kYk8HMMi3MRl0DnrR5NVdRnmPoxswcWXbqKf/duSWH3c0F 1BQqypH4Er+xomJbb1N4Y4jqnYqqUePKQCOk6ha5wGNqW4Gt/4hKXQwHRUn4DRFADViV If5RW+QUIT25VAfIHta4qDsQh3fvQR6fltf/dl22pfBdC7T3OQTRqbaI12/b6P9lyCMj FDtibzMdpI0D4uvxohyRswB7OtqUOh5Ne0WpDE5MBJTolcQvBxDaw8Tn3lR5QWRNzeYC Lb2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Bs7VQGF+Epl5dZ+q3vps3mLgkN/vGMivqNsTt71dwm8=; b=buMBea0ovy9lGuxUJn/RXZ/LU8nIBbvL+cEhuw6D9Oo7O2AXQw1L+Ja5FT0XjmXWc5 72j96ovo0yfaZDmTArS9BS1cK3DeTrPFc/gVgXuysdhK9rOQR/HoyEDfz8wftj7scN+Q vnlZPR/7TtcL+neQfPUPaU2NbqZnmeZ0naqis8orwb6+CQ2k5/tOTt0YE3sy/xQbeLZx L6LE7MdVa9sioH5OBq/oFOOssGQww5KIfGKKZ+v62f5ZeXjAvSOJNbXHU9eknfVAUHqv qp4AswLy0aUUfsfApduRYCXGwItVmaS5KjtN91DY2WF5WOmb7ABes2YlYBIPN9Cd2Rcz 0kgw== X-Gm-Message-State: AOAM5312CxkOxYa1zr+8OjTv9drAi5Jp0TbQ44DGX/l0ddv3wlmjA2X8 BEoGrStVUEkQhZ4Bc0qNM5y87A== X-Google-Smtp-Source: ABdhPJwD+e3jTYI+KuAD2ckSiZudCxC0vwxEThvzYBNrcc+j9FKN0ZQ1j5Q5S8AT2qCoeO9691zksQ== X-Received: by 2002:a1c:21c1:: with SMTP id h184mr6999755wmh.106.1605822991957; Thu, 19 Nov 2020 13:56:31 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 10/28] target/arm: Implement M-profile FPSCR_nzcvqc Date: Thu, 19 Nov 2020 21:55:59 +0000 Message-Id: <20201119215617.29887-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" v8.1M defines a new FP system register FPSCR_nzcvqc; this behaves like the existing FPSCR, except that it reads and writes only bits [31:27] of the FPSCR (the N, Z, C, V and QC flag bits). (Unlike the FPSCR, the special case for Rt=3D15 of writing the CPSR.NZCV is not permitted.) Implement the register. Since we don't yet implement MVE, we handle the QC bit as RES0, with todo comments for where we will need to add support later. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 13 +++++++++++++ target/arm/translate-vfp.c.inc | 27 +++++++++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ad8b80c667d..04f6220b2f7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1524,6 +1524,13 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ #define FPCR_DN (1 << 25) /* Default NaN enable bit */ #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ +#define FPCR_V (1 << 28) /* FP overflow flag */ +#define FPCR_C (1 << 29) /* FP carry flag */ +#define FPCR_Z (1 << 30) /* FP zero flag */ +#define FPCR_N (1 << 31) /* FP negative flag */ + +#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) +#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) =20 static inline uint32_t vfp_get_fpsr(CPUARMState *env) { @@ -1568,6 +1575,12 @@ enum arm_cpu_mode { #define ARM_VFP_FPEXC 8 #define ARM_VFP_FPINST 9 #define ARM_VFP_FPINST2 10 +/* These ones are M-profile only */ +#define ARM_VFP_FPSCR_NZCVQC 2 +#define ARM_VFP_VPR 12 +#define ARM_VFP_P0 13 +#define ARM_VFP_FPCXT_NS 14 +#define ARM_VFP_FPCXT_S 15 =20 /* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */ #define QEMU_VFP_FPSCR_NZCV 0xffff diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index dc26759ab95..6c4b7db8213 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -648,6 +648,11 @@ static fp_sysreg_check_result fp_sysreg_checks(DisasCo= ntext *s, int regno) case ARM_VFP_FPSCR: case QEMU_VFP_FPSCR_NZCV: break; + case ARM_VFP_FPSCR_NZCVQC: + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + break; default: return fp_sysreg_check_failed; } @@ -682,6 +687,22 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int= regno, tcg_temp_free_i32(tmp); gen_lookup_tb(s); break; + case ARM_VFP_FPSCR_NZCVQC: + { + TCGv_i32 fpscr; + tmp =3D loadfn(s, opaque); + /* + * TODO: when we implement MVE, write the QC bit. + * For non-MVE, QC is RES0. + */ + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); + fpscr =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); + tcg_gen_or_i32(fpscr, fpscr, tmp); + store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); + tcg_temp_free_i32(tmp); + break; + } default: g_assert_not_reached(); } @@ -710,6 +731,12 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int = regno, gen_helper_vfp_get_fpscr(tmp, cpu_env); storefn(s, opaque, tmp); break; + case ARM_VFP_FPSCR_NZCVQC: + /* + * TODO: MVE has a QC bit, which we probably won't store + * in the xregs[] field. For non-MVE, where QC is RES0, + * we can just fall through to the FPSCR_NZCV case. + */ case QEMU_VFP_FPSCR_NZCV: /* * Read just NZCV; this is a special case to avoid the --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823554; cv=none; d=zohomail.com; s=zohoarc; b=BCd4N3WdeUMC8WkrIIge2fIPARhT4jEUJBc/PNg04urYSa4b7kAG/M1VMx8q6PE3wLPgknXpFvnb4dIiMKIQ4PaWoYB9ytbkPO4Mam1Zr+Hl+QBHNs1GKLgEPrckdfx+0c6PTsO0tIgwG10CXXihWdeeYxqXMydkDHYtuKhkyME= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823554; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/mxHZqml/sxi9C4g39lKbtODJz0/J/tLjXqLI1lW7vU=; b=ihVAv0vHUIqRTi9Tnz2OYA5FYjZPsNixQg0FMHiMbEg17oQoFy0vaBKKaD5uuNp1BbpcffhvqE0rdrUfbHNVklBYaWcQDfLjFHxRwSDxY4JdEZMNNWTuyxIabsix4m9qKeBG+6mtsjVYN/DJcoL/whU50tDtXFMN7pqjDJlV17U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605823554151842.6494149271695; Thu, 19 Nov 2020 14:05:54 -0800 (PST) Received: from localhost ([::1]:39038 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfs3t-0002vW-3Q for importer@patchew.org; Thu, 19 Nov 2020 17:05:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51396) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrv5-0000mV-4v for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:47 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:56108) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrut-0004BS-1q for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:43 -0500 Received: by mail-wm1-x344.google.com with SMTP id c9so8564843wml.5 for ; Thu, 19 Nov 2020 13:56:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/mxHZqml/sxi9C4g39lKbtODJz0/J/tLjXqLI1lW7vU=; b=nxFyYulYsF0yBXz4oR+n7HTloQyiEsdWnpMjmtkNqhZ7RiyQr/IVUIQ47c0KBTdMxw 7wlAeEU8T9Z650FIqyM3efubhYLJMj6eu1QjmGoWmMPdsN5O3NWusKVLAK6RY7Tol3xn S39BMvhSoufmnNwfUXy/RnFLC6tOvAf2+xy3YtwGgFz7R8Ch9U8yjhJQJOTyqASF2YYu 8A4203+JnTJl+4ZnO6i14+3NYPUgeEU5QtMVd738URvTMSTRJYogWaMYidGh9Lt/s/oj IzPySAnxvoTUUUQL6c1gj50QUNfq8sLn8YIpjLW3SH2jKUOSnqnyiwcLZPesBmzcJQRK TxfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/mxHZqml/sxi9C4g39lKbtODJz0/J/tLjXqLI1lW7vU=; b=n5fLMNYL1F5CIKOAXp4EbXywoUc6BEhhB/0v18d+KjGQYOKb/Lctb5nkL3YqamvhHb SKf8YEKGixUDbETRm+XBy4QcR6gkx88lc8KbIv9D8lD5ablMuiM+sCjQMKTc2kGyU4Vc olxe6dLD8vT9li/g/O6cCDMGSxS41ZR+PjCxT+Um71lFgY8cWM7XmIPtjBDWG0Eu7xdS 5sYHvZ38/p9IJg1zl+phzbq9mrUb7luGqrH9mYqCn+6K6QI6LhHPHIYyk5OMXUdmyMa9 3lajGqFUA8uW+UIgSA1Fi7kFn8TCa5z81P82c3iRoA25CBTegchsYmMKl12ZY6cxfzLt 3bUQ== X-Gm-Message-State: AOAM532rCgkiodzjPFcRU5qS0iFT5+G4QHXZlI5MEfTVE3VxxkLleKoo GlMYfpcpMW4rOu25KyO+NuUYrhWxyDPXYA== X-Google-Smtp-Source: ABdhPJz6b0uIYJvjiAKagJNV+iygmsbR5CdmKyo93UtlCBqj6USvrvn3BbwJ54aqyFqN4pnbxsRiUQ== X-Received: by 2002:a1c:7c02:: with SMTP id x2mr6247348wmc.64.1605822992994; Thu, 19 Nov 2020 13:56:32 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 11/28] target/arm: Use new FPCR_NZCV_MASK constant Date: Thu, 19 Nov 2020 21:56:00 +0000 Message-Id: <20201119215617.29887-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR in the previous commit; use it in a couple of places in existing code, where we're masking out everything except NZCV for the "load to Rt=3D15 sets CPSR.NZCV" special case. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 6c4b7db8213..6bc327e9819 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -743,7 +743,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, * helper call for the "VMRS to CPSR.NZCV" insn. */ tmp =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); - tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); storefn(s, opaque, tmp); break; default: @@ -884,7 +884,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) case ARM_VFP_FPSCR: if (a->rt =3D=3D 15) { tmp =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); - tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); } else { tmp =3D tcg_temp_new_i32(); gen_helper_vfp_get_fpscr(tmp, cpu_env); --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823683; cv=none; d=zohomail.com; s=zohoarc; b=VrWc9A7ffOfK8cRZ4eIbS9OLoSyFdLplO/6QwIY4muL2twfhsaPFl4w9QFjXfaHPjpHSW6P2lQe7fhBku0MFiXvVlrDmdHLEWZMVS4eIi/Di6bLU2dNFTMxoHU8SKVRnfSYpGTHvuG9nLIv85A6BeYvWphmh2CrqLo66N+j9Hok= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823683; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6unaasnFxd79TDn7gyVT0FcWmgVKe5+lejxSz6Mjv8k=; b=AH3FmUXZiTFrojXPEN7Z8exaXPHb0Mb1gSgOvSpbC7/I/cMK33hPs6h8mGRgW+CBNIUU2FeMDpTZUePo++kV35ut/Ii2SYgR9oagrDPcOFEGAcom7OA1QvIF6AENJDiylGoTvURXHCRMTEaAxxFsW8i1TXSiRbtkIOAqpihCDSw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605823683698659.9316500896343; Thu, 19 Nov 2020 14:08:03 -0800 (PST) Received: from localhost ([::1]:47568 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfs5y-0006OG-KV for importer@patchew.org; Thu, 19 Nov 2020 17:08:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrv7-0000oD-3l for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:52 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:52964) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrut-0004Be-RR for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:46 -0500 Received: by mail-wm1-x342.google.com with SMTP id 10so8569447wml.2 for ; Thu, 19 Nov 2020 13:56:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6unaasnFxd79TDn7gyVT0FcWmgVKe5+lejxSz6Mjv8k=; b=VImRXyVr8v2AhsA+OQFglH3J+4fxaUB05LqJkM8Bnv1wWfeg9Nt9PtBoJKaiDefaZ1 ldVOX161fbX8pKM2DcE3JXJ0Fo03hwX4SWcE0MY2Jymykhh1iWzdGtBRJ9nxl1T3+SJZ BBznWDEJWNd/Jb57DXtkk/AE4/IOPDsU9LpoWWNf8bO3DQIEYuLPW2KZcwAY38Ghohe3 uCZUJyS9zImN3txhqwg19UzfZJ7AZmZJoZRV6HxIJtJJkZzatTs4Ak6g/OKUORXbejoJ WnXvUWU6fZpcvvzN0TCcXMr7fObTwQIONqp6jsLuSHiJlVNFX524nmLUpzX6A5cCLDmw xmYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6unaasnFxd79TDn7gyVT0FcWmgVKe5+lejxSz6Mjv8k=; b=cxy55Zy1PG7YwQjlExAWVkdQ3qxpNNlUfLT+0bECKtKtnP/fkylGFc/ri6H9E9fGZ9 do0695g8IyvcxYKEQZfI/5ZIbgTTcSPDkrz+ol7MmSgTKoceubWLhO3kTjk0rad3XNAS 32S1AvUekKbDDEBBQZSt3U6cXzDS//B0xugCX8ma1+nEsvzwLADUka6dwd+QpLAt8JTm GSaabU+Ahlm98MXPFAeV31QAon1gSjTqmfUvI8TXvLxWDySZDI04qY7SXi2YSWc869eJ plVvRw8lwsfB14jDWo2wzddI4PF0woZj5TxLe6RcwQTLGTyfo6pA3t2J+SKDvCsOpAAj rZQg== X-Gm-Message-State: AOAM531+CKuSXlQkSoUU843aT8FnPQe3wZPNye9MK6CTVgoIT6MGMkYj dMeyJSNW0raglYMoiAc4tAaL3w== X-Google-Smtp-Source: ABdhPJykWvuK7P+gY061RHidsApYiwxHOQuC24iG+VAuO4/inOPKzFpcDdjImKMuiayB/uTcgxLI9A== X-Received: by 2002:a1c:230e:: with SMTP id j14mr6380189wmj.187.1605822994200; Thu, 19 Nov 2020 13:56:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 12/28] target/arm: Factor out preserve-fp-state from full_vfp_access_check() Date: Thu, 19 Nov 2020 21:56:01 +0000 Message-Id: <20201119215617.29887-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Factor out the code which handles M-profile lazy FP state preservation from full_vfp_access_check(); accesses to the FPCXT_NS register are a special case which need to do just this part (corresponding in the pseudocode to the PreserveFPState() function), and not the full set of actions matching the pseudocode ExecuteFPCheck() which normal FP instructions need to do. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/translate-vfp.c.inc | 45 ++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 18 deletions(-) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 6bc327e9819..9c90c0647bd 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -83,6 +83,32 @@ static inline long vfp_f16_offset(unsigned reg, bool top) return offs; } =20 +/* + * Generate code for M-profile lazy FP state preservation if needed; + * this corresponds to the pseudocode PreserveFPState() function. + */ +static void gen_preserve_fp_state(DisasContext *s) +{ + if (s->v7m_lspact) { + /* + * Lazy state saving affects external memory and also the NVIC, + * so we must mark it as an IO operation for icount (and cause + * this to be the last insn in the TB). + */ + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + s->base.is_jmp =3D DISAS_UPDATE_EXIT; + gen_io_start(); + } + gen_helper_v7m_preserve_fp_state(cpu_env); + /* + * If the preserve_fp_state helper doesn't throw an exception + * then it will clear LSPACT; we don't need to repeat this for + * any further FP insns in this TB. + */ + s->v7m_lspact =3D false; + } +} + /* * Check that VFP access is enabled. If it is, do the necessary * M-profile lazy-FP handling and then return true. @@ -113,24 +139,7 @@ static bool full_vfp_access_check(DisasContext *s, boo= l ignore_vfp_enabled) /* Handle M-profile lazy FP state mechanics */ =20 /* Trigger lazy-state preservation if necessary */ - if (s->v7m_lspact) { - /* - * Lazy state saving affects external memory and also the NVIC, - * so we must mark it as an IO operation for icount (and cause - * this to be the last insn in the TB). - */ - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - s->base.is_jmp =3D DISAS_UPDATE_EXIT; - gen_io_start(); - } - gen_helper_v7m_preserve_fp_state(cpu_env); - /* - * If the preserve_fp_state helper doesn't throw an exception - * then it will clear LSPACT; we don't need to repeat this for - * any further FP insns in this TB. - */ - s->v7m_lspact =3D false; - } + gen_preserve_fp_state(s); =20 /* Update ownership of FP context: set FPCCR.S to match current st= ate */ if (s->v8m_fpccr_s_wrong) { --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823668; cv=none; d=zohomail.com; s=zohoarc; b=fx+wMUjvEe9uwLOqyMoLyHEeUMo6mqqrRBV3bT3wki5epd2k/NNYADqSuFuhxkiUQ1+k5ogRjMS5yQmbn2zOCC84Ol7BL0UUqiuATaJK1/Aae2HVLNxq/0O2sLq2GGE53ktmZeBgswdlM6pebHopcapNAW+8slHLPPBXep2cobo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823668; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=G9ItV+eP1VFQWsVotetxM6YhffQ3YD5Q2yWIGtJOv7I=; b=fcVsy8q2obwJIYj9IdGfvkJngBcg7M7zL2l/b3ZwmSWMfWnC/KbpKO6s46VRAGWLya8EdQEqVLveytqy48Hzu1nzTuM+iQ/Go9691WwxqdR8r15ZJ5h3POGdXsT6S3n77eg2lwPYNFDpWB7jDigUsreAlMxqA7UuSuiXKW8C4pY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605823668529687.1049343736165; Thu, 19 Nov 2020 14:07:48 -0800 (PST) Received: from localhost ([::1]:45950 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfs5j-0005kc-7j for importer@patchew.org; Thu, 19 Nov 2020 17:07:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51520) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrvC-0000q1-Sp for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:54 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:46025) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrux-0004Ca-9C for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:54 -0500 Received: by mail-wr1-x442.google.com with SMTP id p1so7954309wrf.12 for ; Thu, 19 Nov 2020 13:56:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=G9ItV+eP1VFQWsVotetxM6YhffQ3YD5Q2yWIGtJOv7I=; b=fmtik6kg+o6mS9TDPqbREWvIgts027IR0xq+jiDAOCNdl0+DhdY4txojPZa3shZ5E+ x2Jsgo4FQ2zXHdzPAyWPHYVy8N8wopLyHcIZPgfp6dLCF6vt/blWNGHl+tOZJYHCJru+ vLt1fEugXfKVapznfcPvFPLxEWt/uQwz3G7FHTw5FwOixXs3pUrKrwmBOp1r2hAPrkTN YQIhAptlmBpajuYaSoJWAyvd3PFYWYlNBzy60ubLsOD/Cvhp8/OmLA+l5VnxPTulGPDU QMbGWEg/w3eLZmD26AG+a7OTRLHYLGq59E2Zf3axINApIwnNyxLHu98jry43WUQu4ZV5 cO3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=G9ItV+eP1VFQWsVotetxM6YhffQ3YD5Q2yWIGtJOv7I=; b=gqDTKYgfY5eQifUX3OYxXCenDODJU7Sf0MUzIy7RKS1Le+nbBK57gi6TMIqoiYPy6m zJp2VTxuU42xIipbTgENGL1zEjeOk2Hyvosaci957/uM8bWPufMqMdifjw0UtcbajR4s A0Puu8adt8F0/Q6nXrWToly1Zh4dhUQsci4VB22AeBN0+DJydVpQvNWQy1Ri1dEhzIB3 DDEHiuibYrXkYcf0cmB/EDVHEDLTCRrr0jrHbWX49EwCTFQW+Bl3UvHl0rRaCxGYJcZW EdY5OIYK2JDNUZk5IcAi2G/16m8sSNRUKbOmkuqD+XTkdFQv4GKyjgkfoaYYhreFVCrE b+mA== X-Gm-Message-State: AOAM5320UJvEGbD30KsJbnOz+ijT+3CFkAd4neWvYLi7AbfpsHZXrALg 0KkiqR1i7cd0AYRj9nb1Cdei0YkUSjITmg== X-Google-Smtp-Source: ABdhPJx/5j8CAVUeBjN2F3J27Y+RKeLGWxe4FzVvZ4dBYbIA6ABDOaZJtPyewFik5zQcnhHUz+eY9A== X-Received: by 2002:adf:e912:: with SMTP id f18mr12331065wrm.79.1605822995509; Thu, 19 Nov 2020 13:56:35 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 13/28] target/arm: Implement FPCXT_S fp system register Date: Thu, 19 Nov 2020 21:56:02 +0000 Message-Id: <20201119215617.29887-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the new-in-v8.1M FPCXT_S floating point system register. This is for saving and restoring the secure floating point context, and it reads and writes bits [27:0] from the FPSCR and the CONTROL.SFPA bit in bit [31]. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.c.inc | 58 ++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 9c90c0647bd..ebc59daf613 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -662,6 +662,14 @@ static fp_sysreg_check_result fp_sysreg_checks(DisasCo= ntext *s, int regno) return false; } break; + case ARM_VFP_FPCXT_S: + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + if (!s->v8m_secure) { + return false; + } + break; default: return fp_sysreg_check_failed; } @@ -712,6 +720,26 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int= regno, tcg_temp_free_i32(tmp); break; } + case ARM_VFP_FPCXT_S: + { + TCGv_i32 sfpa, control, fpscr; + /* Set FPSCR[27:0] and CONTROL.SFPA from value */ + tmp =3D loadfn(s, opaque); + sfpa =3D tcg_temp_new_i32(); + tcg_gen_shri_i32(sfpa, tmp, 31); + control =3D load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_deposit_i32(control, control, sfpa, + R_V7M_CONTROL_SFPA_SHIFT, 1); + store_cpu_field(control, v7m.control[M_REG_S]); + fpscr =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK); + tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); + tcg_gen_or_i32(fpscr, fpscr, tmp); + store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(sfpa); + break; + } default: g_assert_not_reached(); } @@ -755,6 +783,36 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int = regno, tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); storefn(s, opaque, tmp); break; + case ARM_VFP_FPCXT_S: + { + TCGv_i32 control, sfpa, fpscr; + /* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */ + tmp =3D tcg_temp_new_i32(); + sfpa =3D tcg_temp_new_i32(); + gen_helper_vfp_get_fpscr(tmp, cpu_env); + tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); + control =3D load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); + tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); + tcg_gen_or_i32(tmp, tmp, sfpa); + tcg_temp_free_i32(sfpa); + /* + * Store result before updating FPSCR etc, in case + * it is a memory write which causes an exception. + */ + storefn(s, opaque, tmp); + /* + * Now we must reset FPSCR from FPDSCR_NS, and clear + * CONTROL.SFPA; so we'll end the TB here. + */ + tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK); + store_cpu_field(control, v7m.control[M_REG_S]); + fpscr =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); + gen_helper_vfp_set_fpscr(cpu_env, fpscr); + tcg_temp_free_i32(fpscr); + gen_lookup_tb(s); + break; + } default: g_assert_not_reached(); } --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/ahYnTL2lQGGWoIiaxWssj4cHQQA/2fHIGzeMpMrupQ=; b=q925+tpFFls1vtRVD379U6BT93JWUYXOT52mvfC66NIlG54kjVIkwiDfL2eLxVnYHd MgQsO45G7xnhG5xyxqN4siPpQg+3rJGmjJbwGJi82mXqFHp8fRccIdvaEyLWRpRXw3Ev KmYpuJq0/kF8Lp1OoD5nQLWysZu3HK69llpIC2EQoaioovm4mN7vMrJCS7lPg3AQLS2w PtRbAVbJbE2yYUctUIE92GklChI9ABCZ4kOTei0fS5GogjKuvLln8rNII6/PgytSsCKH Q4l4KL6aFmddHLAHasL47LDNN3aniJb6Z95DZwxkBtkhr101zghkC8tbkJS16fGM0imr U7hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/ahYnTL2lQGGWoIiaxWssj4cHQQA/2fHIGzeMpMrupQ=; b=auD1Vq9dwy13GCjWnbnXFoOonAqWGawzd24aK4SxovVZqoF3ufPRB4NdY0exqAbsbv J3HDGPOtxbvM9oSb0Kdf9zZ71dEsSCwJ29eG5ElqUGWDGCs8T+InobZhABpaR4z5GBiT kboY/W5si2eCEmW954yT6v2dXcuvXDeQzEzb1HuvoJbFN/VdWLT8/rNUNZNBvkrYPer8 aID3jtxb07RVQqwV4QpnuPd7qz+mIZRqg93iVjt0lUWkAfEuHw9IqyVeJNgNp4kKxwhT QfvPNxHZC6rNVklfmoClolvKbpku38CRBIJhXs1t2zBAVmUVX5lQJL/KjFlDduwjfJoB BN7g== X-Gm-Message-State: AOAM5301cCnK//u+dNr2xfQrneEM0cRzYXTspKg1ie/I+KgUvRK8JrG0 SOpEIQ0Nk15cJosiRyxwL034JQ== X-Google-Smtp-Source: ABdhPJyFy3wKKeiRb4P+GIGEepRTAAAqGelbUV8+O5wTj7gnJdqwmVYT6mYVA9zGl162ZyGmrL6Ahg== X-Received: by 2002:a05:600c:210a:: with SMTP id u10mr6566072wml.98.1605822996466; Thu, 19 Nov 2020 13:56:36 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 14/28] target/arm: Implement FPCXT_NS fp system register Date: Thu, 19 Nov 2020 21:56:03 +0000 Message-Id: <20201119215617.29887-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the v8.1M FPCXT_NS floating-point system register. This is a little more complicated than FPCXT_S, because it has specific handling for "current FP state is inactive", and it only wants to do PreserveFPState(), not the full set of actions done by ExecuteFPCheck() which vfp_access_check() implements. Signed-off-by: Peter Maydell --- target/arm/translate-vfp.c.inc | 110 ++++++++++++++++++++++++++++++--- 1 file changed, 103 insertions(+), 7 deletions(-) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index ebc59daf613..1c2d31f6f30 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -647,8 +647,20 @@ typedef enum fp_sysreg_check_result { fp_sysreg_check_continue, /* caller should continue generating code */ } fp_sysreg_check_result; =20 -static fp_sysreg_check_result fp_sysreg_checks(DisasContext *s, int regno) +/* + * Emit code to check common UNDEF cases and handle lazy state preservation + * including the special casing for FPCXT_NS. For reads of sysregs, caller + * should provide storefn and opaque; for writes to sysregs these can be N= ULL. + * On return, if *insn_end_label is not NULL the caller needs to gen_set_l= abel() + * it at the end of the other code generated for the insn. + */ +static fp_sysreg_check_result fp_sysreg_checks(DisasContext *s, int regno, + fp_sysreg_storefn *storefn, + void *opaque, + TCGLabel **insn_end_label) { + *insn_end_label =3D NULL; + if (!dc_isar_feature(aa32_fpsp_v2, s)) { return fp_sysreg_check_failed; } @@ -663,6 +675,7 @@ static fp_sysreg_check_result fp_sysreg_checks(DisasCon= text *s, int regno) } break; case ARM_VFP_FPCXT_S: + case ARM_VFP_FPCXT_NS: if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { return false; } @@ -674,8 +687,46 @@ static fp_sysreg_check_result fp_sysreg_checks(DisasCo= ntext *s, int regno) return fp_sysreg_check_failed; } =20 - if (!vfp_access_check(s)) { - return fp_sysreg_check_done; + /* + * FPCXT_NS is a special case: it has specific handling for + * "current FP state is inactive", and must do the PreserveFPState() + * but not the usual full set of actions done by ExecuteFPCheck(). + * We don't have a TB flag that matches the fpInactive check, so we + * do it at runtime as we don't expect FPCXT_NS accesses to be frequen= t. + * The code emitted here handles the fpInactive special case; + * the caller just has to do the codegen for the normal (!fpInactive) + * special case, and then set the label at the end. + */ + if (regno =3D=3D ARM_VFP_FPCXT_NS) { + /* fpInactive =3D FPCCR_NS.ASPEN =3D=3D 1 && CONTROL.FPCA =3D=3D 0= */ + TCGLabel *fp_active_label =3D gen_new_label(); + TCGv_i32 aspen, fpca; + aspen =3D load_cpu_field(v7m.fpccr[M_REG_NS]); + fpca =3D load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); + tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK); + tcg_gen_or_i32(fpca, fpca, aspen); + tcg_gen_brcondi_i32(TCG_COND_NE, fpca, 0, fp_active_label); + tcg_temp_free_i32(aspen); + tcg_temp_free_i32(fpca); + + /* fpInactive case: FPCXT_NS reads as FPDSCR_NS, write is NOP */ + if (storefn) { + TCGv_i32 tmp =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); + storefn(s, opaque, tmp); + } + /* jump to end of insn */ + *insn_end_label =3D gen_new_label(); + tcg_gen_br(*insn_end_label); + + gen_set_label(fp_active_label); + /* !fpInactive: PreserveFPState() and handle register as normal */ + gen_preserve_fp_state(s); + } else { + if (!vfp_access_check(s)) { + return fp_sysreg_check_done; + } } =20 return fp_sysreg_check_continue; @@ -687,8 +738,10 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int= regno, { /* Do a write to an M-profile floating point system register */ TCGv_i32 tmp; + TCGLabel *insn_end_label; + bool lookup_tb =3D false; =20 - switch (fp_sysreg_checks(s, regno)) { + switch (fp_sysreg_checks(s, regno, NULL, NULL, &insn_end_label)) { case fp_sysreg_check_failed: return false; case fp_sysreg_check_done: @@ -702,7 +755,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, tmp =3D loadfn(s, opaque); gen_helper_vfp_set_fpscr(cpu_env, tmp); tcg_temp_free_i32(tmp); - gen_lookup_tb(s); + lookup_tb =3D true; break; case ARM_VFP_FPSCR_NZCVQC: { @@ -721,6 +774,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int = regno, break; } case ARM_VFP_FPCXT_S: + case ARM_VFP_FPCXT_NS: { TCGv_i32 sfpa, control, fpscr; /* Set FPSCR[27:0] and CONTROL.SFPA from value */ @@ -743,6 +797,12 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int= regno, default: g_assert_not_reached(); } + if (insn_end_label) { + gen_set_label(insn_end_label); + } + if (lookup_tb) { + gen_lookup_tb(s); + } return true; } =20 @@ -752,8 +812,10 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int = regno, { /* Do a read from an M-profile floating point system register */ TCGv_i32 tmp; + TCGLabel *insn_end_label; + bool lookup_tb =3D false; =20 - switch (fp_sysreg_checks(s, regno)) { + switch (fp_sysreg_checks(s, regno, storefn, opaque, &insn_end_label)) { case fp_sysreg_check_failed: return false; case fp_sysreg_check_done: @@ -810,12 +872,46 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int= regno, fpscr =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); gen_helper_vfp_set_fpscr(cpu_env, fpscr); tcg_temp_free_i32(fpscr); - gen_lookup_tb(s); + lookup_tb =3D true; + break; + } + case ARM_VFP_FPCXT_NS: + { + TCGv_i32 control, sfpa, fpscr, fpdscr, zero; + /* Reads the same as FPCXT_S, but side effects differ */ + tmp =3D tcg_temp_new_i32(); + sfpa =3D tcg_temp_new_i32(); + fpscr =3D tcg_temp_new_i32(); + gen_helper_vfp_get_fpscr(fpscr, cpu_env); + tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK); + control =3D load_cpu_field(v7m.control[M_REG_S]); + tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); + tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); + tcg_gen_or_i32(tmp, tmp, sfpa); + tcg_temp_free_i32(control); + /* Store result before updating FPSCR, in case it faults */ + storefn(s, opaque, tmp); + /* If SFPA is zero then set FPSCR from FPDSCR_NS */ + fpdscr =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); + zero =3D tcg_const_i32(0); + tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr); + gen_helper_vfp_set_fpscr(cpu_env, fpscr); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(sfpa); + tcg_temp_free_i32(fpdscr); + tcg_temp_free_i32(fpscr); + lookup_tb =3D true; break; } default: g_assert_not_reached(); } + if (insn_end_label) { + gen_set_label(insn_end_label); + } + if (lookup_tb) { + gen_lookup_tb(s); + } return true; } =20 --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823980; cv=none; d=zohomail.com; s=zohoarc; b=FLeecb1GzgU8nCDZVhY03ZGGIyt0bCD2aJmTjs5xGEmN/UBCicTPIrgDNvAENuZTxg9kt/dlqteX9T5E1ZnpkAH866bJRMAC6W/W5cO6X1R2gNtsQYlPwnPUdUr9+0cqYyhClHN2OBFaLOD+e4ctj6zI+abR2mG41HlqDhCr4Rc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823980; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fefp6vwB13CDumLtzkP2IpkRHFYQ0KIOF0eOKK7wtig=; b=nd7u1B9kpFWzHYZRvxVazfHHYNvyfxzO6xgPAwVrd1DwAThMgU465X54DBdRFb4hwGML24rPBPKhW4RT2jhHeQLRxkJb5gEl/Qhigr6+pfqdLqX51vqdxTX7XI40vk2WsyHtQiIXUSXeDEFAYKPzLXfzPgJ5UUR06liKZIP51Zc= ARC-Authentication-Results: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fefp6vwB13CDumLtzkP2IpkRHFYQ0KIOF0eOKK7wtig=; b=XUf1ePKdWlFArUr8NFMEqWBYBkV8FtwP/roIG2d8hreGeCm1jsvAOyPLWUmWXRbl76 oD0cLWQuoA2CGpgqFvrH/PiDXxhbLlBxa9/rkTUj7KrT8rFcT7MAzc4Yt6kT59OQpDak 1olUC3E+bRrmXJiXY8z3NzSxoXDl2smFYBcTlt+wkPCy9YJRvDe7eAxZFHO2o7XwxoYT eq74hV+XzLVGYXSKBdHlV/leeWLIfX3C8C/iuyxPEqHNDYtoenBguBVWJEf1UMSdRCtN 4Eite97WI5bRUAZ/7NcUMuWVS8G5haA6mU7xpi/da9yauA1BMfOHoKFpEfLUPTXdbLou eM1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fefp6vwB13CDumLtzkP2IpkRHFYQ0KIOF0eOKK7wtig=; b=cS6MHNctxLidxi/mgauZK8tGYAS/81zFxfX2WDKkVCRUay84L1EYpnwuWGEEzwYfck 754LQjr1qO5G3kHk+z0aXvOJrFO7DULK/nc+eH0Nj6KQvVgrZ05VaQyrOfj4TodCMY0S HhVWSxiwmAc3BhyGCFd1dXteOXgiSejKRT95P5sTXh1T2C39ueC/Rh42D2by8nsQ4Do3 xImwahH9DkQOkxCd3MY4Zuiqoio/BIS13tjTQz1YB9oCwC7J2iWMsFcQjEwzX9XdH+aw /S38hezwMfhKcjzfJVaLLVXXRAb7arE8fxhxUF2s/W+y0L+z5HZGvb33YkiXr99OQB31 5CGw== X-Gm-Message-State: AOAM532nSNJRMiU3PMDuLFWQR/EJsiNUwTQqJxLgtPRMUfHfW9xP4oyO X9kNJLF6yKhT7AuWVTzs8t+OZ8VesZEUVQ== X-Google-Smtp-Source: ABdhPJykeR8H8mxNeiDG5Qb/7Vsot3Feo96G0Fa1Ab/nhNmZyy+vKKzPXMf+bjZ6KWZbRUGKq/kvrQ== X-Received: by 2002:adf:e3cf:: with SMTP id k15mr12319588wrm.259.1605822997628; Thu, 19 Nov 2020 13:56:37 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 15/28] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M Date: Thu, 19 Nov 2020 21:56:04 +0000 Message-Id: <20201119215617.29887-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The FPDSCR register has a similar layout to the FPSCR. In v8.1M it gains new fields FZ16 (if half-precision floating point is supported) and LTPSIZE (always reads as 4). Update the reset value and the code that handles writes to this register accordingly. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ hw/intc/armv7m_nvic.c | 9 ++++++++- target/arm/cpu.c | 3 +++ 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 04f6220b2f7..47cb5032ce9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1521,14 +1521,19 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPCR_IXE (1 << 12) /* Inexact exception trap enable */ #define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */ #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ +#define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */ #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ #define FPCR_DN (1 << 25) /* Default NaN enable bit */ +#define FPCR_AHP (1 << 26) /* Alternative half-precision */ #define FPCR_QC (1 << 27) /* Cumulative saturation bit */ #define FPCR_V (1 << 28) /* FP overflow flag */ #define FPCR_C (1 << 29) /* FP carry flag */ #define FPCR_Z (1 << 30) /* FP zero flag */ #define FPCR_N (1 << 31) /* FP negative flag */ =20 +#define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */ +#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT) + #define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V) #define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC) =20 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 9628ce876e0..be3bc1f1f45 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2068,7 +2068,14 @@ static void nvic_writel(NVICState *s, uint32_t offse= t, uint32_t value, break; case 0xf3c: /* FPDSCR */ if (cpu_isar_feature(aa32_vfp_simd, cpu)) { - value &=3D 0x07c00000; + uint32_t mask =3D FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MA= SK; + if (cpu_isar_feature(any_fp16, cpu)) { + mask |=3D FPCR_FZ16; + } + value &=3D mask; + if (cpu_isar_feature(aa32_lob, cpu)) { + value |=3D 4 << FPCR_LTPSIZE_SHIFT; + } cpu->env.v7m.fpdscr[attrs.secure] =3D value; } break; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 40f3f798b2b..d6188f6566a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -262,6 +262,9 @@ static void arm_cpu_reset(DeviceState *dev) * always reset to 4. */ env->v7m.ltpsize =3D 4; + /* The LTPSIZE field in FPDSCR is constant and reads as 4. */ + env->v7m.fpdscr[M_REG_NS] =3D 4 << FPCR_LTPSIZE_SHIFT; + env->v7m.fpdscr[M_REG_S] =3D 4 << FPCR_LTPSIZE_SHIFT; } =20 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823562; cv=none; d=zohomail.com; s=zohoarc; b=bdcaPPBieqiQG1OPI3qCY73vOprdsC9R5QcHBJNkmtBX5WQUII394pCRsetgDp1UNm6+c5S0K1bOyoXHcwVqBIvnbHZlIWjgCsw4dMFGnpA5iE4EUR10qjfI6KmthUQ7kdFJSU25IU3uN7wwrIdUKKhj6neVeGM2M2TN4VEfUK8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823562; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dmuz2iP7WEA/tvUoqpMotG3FBE2Nn1szm0QJrAqWTGk=; b=cTZa/5r6rmSiOVAWuvsMrWrFS8CctDJXqYsGHEDaGUG7rX3PucZiHSBPefS2LNvNqx2H1OxmEn78P3YMlGosprZk9Xngejr8dnJn+Z+qck2d/iYdRuv8X68M404hcrzIqaYwe5NkRJ9bDhtaxo8yMdSKlAqV1TXFcXvo/GnQghc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160582356262765.50564500824271; Thu, 19 Nov 2020 14:06:02 -0800 (PST) Received: from localhost ([::1]:39752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfs41-0003Fp-IK for importer@patchew.org; Thu, 19 Nov 2020 17:06:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51506) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrvC-0000ow-D4 for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:54 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:34719) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfruz-0004DI-8v for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:54 -0500 Received: by mail-wm1-x343.google.com with SMTP id x13so1671473wmj.1 for ; Thu, 19 Nov 2020 13:56:39 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dmuz2iP7WEA/tvUoqpMotG3FBE2Nn1szm0QJrAqWTGk=; b=kYBF8L3K6y9rm7F16oLlrGgWMYpUAgbXdg7iFtFl7HLmlSM2+H7zHdwYhWAvr36KCw FrDaDaKFw4T/TTmIqLqDQDXrapvx2pjz5v86NIExxlRyjKsbnwA6NKQHNRssKicrQMUc Ow9vmFLQpeGM+ZlPj2Zx6+YuCo3zO7WPI8uNTFjannSSYMz24CnxpterjVsnozbxzOyn wGLafW5XoZpe6ReDGZkOj2XeZo5OsQ89J6Q0wu4E65QS1JxxKfRM0M32W6IK2aShq3NR /jOJdx9cUwMOsejQY6M8mQqXqz8Ug24mWi2blgPFSsQaEFzefeu0IaIJPRUXxkm9euOJ DA1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dmuz2iP7WEA/tvUoqpMotG3FBE2Nn1szm0QJrAqWTGk=; b=Y/Bn6GZ6EBJg7Yrgp8N+r0JdwV20EWlQ9/RVtCMEbaudL2afkcUmBJKTYKUvnIvTIG QlBTABUdSPbySQluY5tQfs+Vegw00NYtDRe8LTrWFJbcZSlUQBOzkTyf97/OQgbZiVA3 0JDjsupwRF66+UPgQvKfDKz80lou4ESUK/HzCiYpZguCEDxAKY1Dwn1mVAzLba0orGfV 3KsTHWgYj4Kp6LEfS5nfe+kzJEq9gyVBSG/ebJEmdlBToL67syV3hPowTwhI7TEGrFz8 0fV8DcWPvlvDXuYA305mr091hpK6l++Yn0Ad8DrjCJvPr7agtGrKCuJdIAp3CYSHmSUS u6JA== X-Gm-Message-State: AOAM5327EAz6YxqRUnQexc4xKUSRdsm9J3+zDDizZAFcpX0gcs4cHlyW AeHTHz94G6VyKPRs4L1IN6p+MQCnsj8u4w== X-Google-Smtp-Source: ABdhPJxSAl432dF/goP65OG8QxOX5hS+eV4oPyXiw90G073FQeB6sr8lG70P5u0+v6uNvZLEmO8NVQ== X-Received: by 2002:a1c:7e8e:: with SMTP id z136mr6852627wmc.46.1605822998689; Thu, 19 Nov 2020 13:56:38 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 16/28] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry Date: Thu, 19 Nov 2020 21:56:05 +0000 Message-Id: <20201119215617.29887-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR are zeroed for an exception taken to Non-secure state; for an exception taken to Secure state they become UNKNOWN, and we chose to leave them at their previous values. In v8.1M the behaviour is specified more tightly and these registers are always zeroed regardless of the security state that the exception targets (see rule R_KPZV). Implement this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/m_helper.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index aad01ea0127..721b4b4896e 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -897,10 +897,12 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t= lr, bool dotailchain, * Clear registers if necessary to prevent non-secure exception * code being able to see register values from secure code. * Where register values become architecturally UNKNOWN we leave - * them with their previous values. + * them with their previous values. v8.1M is tighter than v8.0M + * here and always zeroes the caller-saved registers regardless + * of the security state the exception is targeting. */ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - if (!targets_secure) { + if (!targets_secure || arm_feature(env, ARM_FEATURE_V8_1M)) { /* * Always clear the caller-saved registers (they have been * pushed to the stack earlier in v7m_push_stack()). @@ -909,10 +911,16 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t= lr, bool dotailchain, * v7m_push_callee_stack()). */ int i; + /* + * r4..r11 are callee-saves, zero only if background + * state was Secure (EXCRET.S =3D=3D 1) and exception + * targets Non-secure state + */ + bool zero_callee_saves =3D !targets_secure && + (lr & R_V7M_EXCRET_S_MASK); =20 for (i =3D 0; i < 13; i++) { - /* r4..r11 are callee-saves, zero only if EXCRET.S =3D= =3D 1 */ - if (i < 4 || i > 11 || (lr & R_V7M_EXCRET_S_MASK)) { + if (i < 4 || i > 11 || zero_callee_saves) { env->regs[i] =3D 0; } } --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823780; cv=none; d=zohomail.com; s=zohoarc; b=mvB2nFCBsKzjvp6nC+AC7/E8XgnT1lDriiMvbj1Z5nBz6LtoNPwRjJPAkulsDu50YlrbMABRcpUid1P2uuTGqhg3R0qzR0LjyhZZQAQdDXPBiPa1v5PCbTNWu34I/NA+v90o5fR8v+0MUltx72Na2vVfDRc4cgS+1pS6vq09E1w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823780; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=v15Qy4cmfx4WYV2eDBerGMLhauNtxeDDRpl5ncA8vg0=; b=adcxwPhehGfBAep7f6hZW0ixzzrlyCV2XSqKoAyc6jjInzxByLjicBTGUQBvfYukgLOfFUyLiF4d8tgbbi22YPw5NLkCjuZ8MchprvMCLxHq/aeVDHOU1QvdQzgKS60k/9PNqi4J6oJXQe1HLAqHLelQy56ij8K2E6s+lwF1gb0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605823780460410.8870636409391; Thu, 19 Nov 2020 14:09:40 -0800 (PST) Received: from localhost ([::1]:54528 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfs7X-0000kF-5r for importer@patchew.org; Thu, 19 Nov 2020 17:09:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51536) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrvD-0000rC-Hy for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:55 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:34720) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfruz-0004DP-9A for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:55 -0500 Received: by mail-wm1-x344.google.com with SMTP id x13so1671506wmj.1 for ; Thu, 19 Nov 2020 13:56:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=v15Qy4cmfx4WYV2eDBerGMLhauNtxeDDRpl5ncA8vg0=; b=AmN8XAie1TKtvsdLRfjQ/dFCvWAJHMslGdiIQ/DWeD+q/5w78IypkBWjWW2nxld5iJ JOfR0SQ6UPpTyAJy8fa3SEJwe7Iz96+SxMVlyRWcDJrwiO98WiT8vxiaER9ekoiQAq8p Pbp8hfVAcM7oBIJY2VDIkQHnoQokjUuYHwDkK+svsnx15aSPyi5yKi0J3x/m8uLAgC7K P6Z1ZI/82SI0TnjpEigRhIZD88bwZXlyOPgXdIgVbPjGTsVtwGIUbnulq3EMs9Caj37S 3ABuwFz2fPF0df6tQRkkHmwtaiJHIyTfK98D1EgHOzOOkSBk6PjyBCqOE59Z8cg/xNo/ Vlaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v15Qy4cmfx4WYV2eDBerGMLhauNtxeDDRpl5ncA8vg0=; b=gLoWM41cQX0bloY6X57xE/kKI+UXWKXZDR+qXoDkOjBHSHn66K57yNqsoZl1/y8i89 ihtpi2H/1Kf79i7WgmjT5xAcQ5m1MpVg2qqXw1DJrZ7qPKTpYjW/vs2vXud12V10OQlT Wpup+pbqoOnZNR5gtArnHFMYkI3JiUg+95fa/qoOoSjkeZntOyUtjxg5gYf7rtRAJbPZ y4sGKiDc8evh+SZmEuoThouY6eP8EfUlFjIkRGGFwE8uBX3JEcyTu9T4RVMNsxiHdOkX SgZ0Z5hY8ELn5LMKcLO9gRaYpLdiXTw1EaP8Vp/vgI5AlaQEkPzEtRVOGoeorNVtihSB Jzkg== X-Gm-Message-State: AOAM530J2M5GymZbRv5TXHkbRYI42jJf6E9zw5qBQOpuZ+k7P+ndwk7W jHP4cC/AiHY1NvZBsRETIE9DWQ== X-Google-Smtp-Source: ABdhPJyWOQsVdQ2wYaDhvxFhI4Rw+D5OuWvwt6d7+eJAaoll51Kf8PZYr4apt4ZKz26IkKT5819JZA== X-Received: by 2002:a1c:490b:: with SMTP id w11mr6599129wma.101.1605822999633; Thu, 19 Nov 2020 13:56:39 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 17/28] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures Date: Thu, 19 Nov 2020 21:56:06 +0000 Message-Id: <20201119215617.29887-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In v8.1M, vector table fetch failures don't set HFSR.FORCED (see rule R_LLRP). (In previous versions of the architecture this was either required or IMPDEF.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/m_helper.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 721b4b4896e..9cdc8a64c29 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -722,11 +722,15 @@ load_fail: * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are * secure); otherwise it targets the same security state as the * underlying exception. + * In v8.1M HardFaults from vector table fetch fails don't set FORCED. */ if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { exc_secure =3D true; } - env->v7m.hfsr |=3D R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK; + env->v7m.hfsr |=3D R_V7M_HFSR_VECTTBL_MASK; + if (!arm_feature(env, ARM_FEATURE_V8_1M)) { + env->v7m.hfsr |=3D R_V7M_HFSR_FORCED_MASK; + } armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secur= e); return false; } --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605824162; cv=none; d=zohomail.com; s=zohoarc; b=FO4/T/GPsYoMDMZzpExpNQNECajU36Y3AZtpFsgHVj68ZeqjVWVPlzsyT8qipo06xE5YZ+OBVjWkKCorX4d9jJiiK/0Tzh2mTCbhvq1XSjSCQPMI1IrTxbtyU3pVjGt5Lm8zTElIkG3TANJRmuS1PumQT/SN6P/g26GArUkZMIM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605824162; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=x/1ikKgCtIh33k/Ei8GUh695aaBVR/KcxDX2doWvQMY=; b=m1ia9Ly09EkJEe2KorZpFN1Kk++U+Y2h6LNYWVHWJTR0JIdUta1gNsMzFB7MNWpP9mO6GO5AMcvPco/dxeFfVSylFIDxsKPvtPRe8xm/JCFgRkgDzstkEKJX3IOlgo95ViDsUdyc+FOY5L7gx6QrehLa98yplV1WCUCfZ0qj9Kc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605824162762603.9165090462845; Thu, 19 Nov 2020 14:16:02 -0800 (PST) Received: from localhost ([::1]:44376 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfsDh-0008G6-G2 for importer@patchew.org; Thu, 19 Nov 2020 17:16:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51574) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrvF-0000va-5q for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:57 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:51451) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrv1-0004De-81 for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:56 -0500 Received: by mail-wm1-x341.google.com with SMTP id a186so5772469wme.1 for ; Thu, 19 Nov 2020 13:56:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=x/1ikKgCtIh33k/Ei8GUh695aaBVR/KcxDX2doWvQMY=; b=opmGv8RDBXEjJGAPXp5nLTJIqrWGs4Zd6lF6a+Unm/qXUKITnmBLaOjy3MGV5iuXtd 3sMgTCk0dVT9iqtTAbsb5ZRxTlEn1r7rsdkZ56lJiG+ddZ6KgJJ5rgKwlDTJz2Eo1W2A NtilX51tqFnmtJviuU3OETDm1EmBWjrQZ91HZpIyOSnbYp23CjhDxyS27wRR/pbiiM+6 f4ej8IsbeR9MTZfhJmoxUap2S+IQvmsi0MVkr/JoK4yy1WZiU9IFuQU4wuvmuhLvhbJQ g2drs+BEcVH2GPVCyyzhDkY2BrPP/12jIZF3i8amIESeZnsPOQi63meCAvCfDRIfjAAA tfMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x/1ikKgCtIh33k/Ei8GUh695aaBVR/KcxDX2doWvQMY=; b=tOZ+u5eKjCczskuyJfRAVzYb45vFoqxQU8Oco0AekEK1xQqWFe3+xPR0+myaYUrN9Z EJIAwoGX/4RjqlO+m7G8rVAbYNI/ZcA3ezgGWKNmo4tzTPa6o+DOMoQj1gzh7alSX9Px y3L/JhAm8ktO7QfMhZRelFPfk8izkmdkT5AvpiosmG0SeAHcMW43QfcgSan9sVFYBWfe wzS3hnPDRHU6Eps+/xhBCDoAV17BWolpv8+yinSCH8ra8kUMiI2nBuIhJRDIjHwnclmC 46kVWoHr22hONlmhUl9yZprw0tpArleXp4zTjz8/0dqdNglVmn19B60laZdMK5MA3cCD b8oQ== X-Gm-Message-State: AOAM531gT0rlqdsN4tj9N0uPz8m22y5vvVGmIt5oyBmR3LOUvkjJr/Vu KiwsDCmiV1IijwihGR1abUdeNQ== X-Google-Smtp-Source: ABdhPJxY2c9Aom5y6kcieM4xj5K0YJFqHVdv2r1DBOHkyL+DRNJc9trPllSOp8gqH/M5UJzd0ZxNSA== X-Received: by 2002:a1c:103:: with SMTP id 3mr6381648wmb.81.1605823000830; Thu, 19 Nov 2020 13:56:40 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 18/28] target/arm: Implement v8.1M REVIDR register Date: Thu, 19 Nov 2020 21:56:07 +0000 Message-Id: <20201119215617.29887-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In v8.1M a REVIDR register is defined, which is at address 0xe00ecfc and is a read-only IMPDEF register providing implementation specific minor revision information, like the v8A REVIDR_EL1. Implement this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/armv7m_nvic.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index be3bc1f1f45..effc4a784ca 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1025,6 +1025,11 @@ static uint32_t nvic_readl(NVICState *s, uint32_t of= fset, MemTxAttrs attrs) } return val; } + case 0xcfc: + if (!arm_feature(&cpu->env, ARM_FEATURE_V8_1M)) { + goto bad_offset; + } + return cpu->revidr; case 0xd00: /* CPUID Base. */ return cpu->midr; case 0xd04: /* Interrupt Control State (ICSR) */ --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605824055; cv=none; d=zohomail.com; s=zohoarc; b=czxXDUFR9LwFIjJq9lyxkb1ksjlHbGtC8BnrZI5sYOoHNGdliRCM5hL3kQSk3QGYhwlSSMGFbwkzGIJ+gC6M8jYVd8yQmJA9ysJ6RAr7aheSmjbDsjqpK5E//Q2wlEfT/plHhH7il3+9vpeAuxTI3vTUNbgGdhrYR2B0GTnz7Eo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605824055; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ztib3BbeM9JUbGctUP1Ui7NNujTzQdmeDBZWCNALq4Y=; b=YHJHsprFYO9ho/XsNsi+PknjMDsH26gyc8f3fDnfOaCJ38bvn069+ZnhMH4nFQdTayBA2gUu3wd2I0MMPlaG4AtKJdFwrFXIHexJK2gFHnVjNLZUe36GpUrviSOYy8VUqQzeJ4KAVMPnv9oBhH9E0scI4rEa9mteSFcpNZqQAPE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605824055301888.6003870690587; Thu, 19 Nov 2020 14:14:15 -0800 (PST) Received: from localhost ([::1]:40082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfsBy-0006Ui-6l for importer@patchew.org; Thu, 19 Nov 2020 17:14:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrvG-0000ya-AN for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:58 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:53283) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrv1-0004Ec-96 for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:56:57 -0500 Received: by mail-wm1-x341.google.com with SMTP id p22so8566970wmg.3 for ; Thu, 19 Nov 2020 13:56:42 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ztib3BbeM9JUbGctUP1Ui7NNujTzQdmeDBZWCNALq4Y=; b=mUXBV4Y+GEwgY3duB07dfXllNzghYWt8Z2qs1Ffwu7SivtqckZ2A2G9CFDsP8kAsdN woUBO8uPbrj7ezmWhc0KnpEyJm6WIJ7p2N1xSJlMwlt9hSjrTmJlUUd1k8zjb6A2qHbD YP02FDN3y3BnILNvMEtlraIr9M6WAnX1JNyfms0kTSwqjgMHdEnG1HfMAXw/f20Mr43h vodutjC8lSytAyUqlTCBbXNLP6XaGF7hGiQxLTpOig9zN4W4dIjMfUOo5qhm0QsrD2Pj mLbfKdXbk+7vMhT3fweZnAkXsGWARfJe4NAUN+4KHbSvqIdm3SW6dBEoTBblOrGB4ZYJ PW+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ztib3BbeM9JUbGctUP1Ui7NNujTzQdmeDBZWCNALq4Y=; b=djLU+2qx+cOFXIDzZRgZz9lCF42AxiSq2F5b4kl+4B8h7nKgGZNoqiCsUZqFaFebgS PCQRgLuqbUZHsFhSZIEquKLFW67QBGAjPn+LQH2Af0tTp4qMQxUBIcd1HWIHed3bMi+3 wKjRaQUjPuBbi7z0aTTy7FzSCYwBgyNY+QTQ4NFRIJIhPVlHMu6uSBaSaCdrT04Vuce/ g6CDyh+bXMPyc0OW9MeL6P7cwkapCqcUaAMX58z4i0EvClhOMjvfjv2xnm4QJ2B6u23A 6zEV6eRvZaRpvlG0rOKvqCLnzhgUgwX9BA8MZCTxFxcGq/iB8GQoAQxjLWiH8TaGax+m SYhQ== X-Gm-Message-State: AOAM531qhbYIWaqKgPP3W3ZkDXjNeZ+tiZDpWMOFQ8/rjZTJ2GaPLe32 g1FHDSBv59eP+1YN7hemUHBtFwP+66U5Vg== X-Google-Smtp-Source: ABdhPJy5lYRFRQqmheM5QAa2OxDAuhqj9nnrwW/ihm3vwafRVssOdiG0u25fMidyWM4ChSONfBVqfQ== X-Received: by 2002:a1c:1d51:: with SMTP id d78mr6547219wmd.60.1605823001969; Thu, 19 Nov 2020 13:56:41 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 19/28] target/arm: Implement new v8.1M NOCP check for exception return Date: Thu, 19 Nov 2020 21:56:08 +0000 Message-Id: <20201119215617.29887-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In v8.1M a new exception return check is added which may cause a NOCP UsageFault (see rule R_XLTP): before we clear s0..s15 and the FPSCR we must check whether access to CP10 from the Security state of the returning exception is disabled; if it is then we must take a fault. (Note that for our implementation CPPWR is always RAZ/WI and so can never cause CP10 accesses to fail.) The other v8.1M change to this register-clearing code is that if MVE is implemented VPR must also be cleared, so add a TODO comment to that effect. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/m_helper.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 9cdc8a64c29..0bdd3cc10e9 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1515,7 +1515,27 @@ static void do_v7m_exception_exit(ARMCPU *cpu) v7m_exception_taken(cpu, excret, true, false); return; } else { - /* Clear s0..s15 and FPSCR */ + if (arm_feature(env, ARM_FEATURE_V8_1M)) { + /* v8.1M adds this NOCP check */ + bool nsacr_pass =3D exc_secure || + extract32(env->v7m.nsacr, 10, 1); + bool cpacr_pass =3D v7m_cpacr_pass(env, exc_secure, true); + if (!nsacr_pass) { + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, = true); + env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_NOCP_MASK; + qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on ex= isting " + "stackframe: NSACR prevents clearing FPU registers= \n"); + v7m_exception_taken(cpu, excret, true, false); + } else if (!cpacr_pass) { + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, + exc_secure); + env->v7m.cfsr[exc_secure] |=3D R_V7M_CFSR_NOCP_MASK; + qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on ex= isting " + "stackframe: CPACR prevents clearing FPU registers= \n"); + v7m_exception_taken(cpu, excret, true, false); + } + } + /* Clear s0..s15 and FPSCR; TODO also VPR when MVE is implemen= ted */ int i; =20 for (i =3D 0; i < 16; i +=3D 2) { --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605824569; cv=none; d=zohomail.com; s=zohoarc; b=JUfIeL/n9MsCjcHbCIY2xsnkJI2CHrRU2EjfQH31Y3ZwdbYpxAWY/E5/e8M98ju5YerVzm2EYDWnvubQPVzOSjE5kKwQ+v0Sym6VdzGrsWKU36skVJm85OujVZ/V0r1ibRFVOUDy3eT7M3W/18EA8IRLrotAVmBoBQOwxhAq79s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605824569; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=muF03FIBUNjZmHA9ePjBGJ37JzD55SGiha97SZN8IOk=; b=fm2Ph4M1L2pj8aPgy1LRDNaklrIS5W+jr7GLzz34QucJByHmN0LPRsXRGU13W0snENj+Sv+H+FLrAnfued61N24Yw0ET3HnODRtrCVnWj9R7WNYdqFxslzPEyUPCRIP1XSbhnenUaqftnUBCYlpaKi3hB6v59islXUEzA1FpyOE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605824569369268.01941771722795; Thu, 19 Nov 2020 14:22:49 -0800 (PST) Received: from localhost ([::1]:59310 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfsKG-0006Sz-6X for importer@patchew.org; Thu, 19 Nov 2020 17:22:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51676) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrvJ-00015J-3W for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:01 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:39734) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrv4-0004Es-TE for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:00 -0500 Received: by mail-wm1-x32b.google.com with SMTP id s13so8060678wmh.4 for ; Thu, 19 Nov 2020 13:56:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=muF03FIBUNjZmHA9ePjBGJ37JzD55SGiha97SZN8IOk=; b=LNSGrqMCuRgAepOKkGnCY8Il1Hai1AenwzHczZ+hlPqbBXT3VM70xBqA403YN2Q5Se LhyNOfqT9mtUarm8U9bmlKosznj1FTbIW0Sx0ZgPDKd03ke/9rOcNUMXYJCWpLKWT620 qpGCFq5vlPjd5OUDsbkqjRJcTWyZvMFgdzUozumFNm1/0mpMf1ZzWmJjYYAuQYVOzaTk wFU933felh2fG8xtsjT/yd8Xaa02PV/mY3eoGMam0XfS8nBrs32hg0EHHd0p4eY+2HKJ P3ZDQbDQy8yz39xNUBTJYCvOX6gjXbTBjX/Sp73ccPtFxWMmlgk9sOdISDPl2Ds0xYL0 skHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=muF03FIBUNjZmHA9ePjBGJ37JzD55SGiha97SZN8IOk=; b=uFyAYscPB3AQ0hWoiVXcT9DzChXT72ERGdnV93X2eRkSnadTZ7oMqDKEhvdDZ4zADm ux4wInsufUpsSQLW8JKuq/D08NJLzkMaXcBdVXtVZYmpDPk/QUK/fGU8KJw4P2l5v5Ib w2ca2h2urk/BT7SFlDZ3dJ7wyPMcEIbdU+PJiJtduORKzHGLfD3cRfpusCMb3l7/M2UG PXWeieOmT5WYwSIr6B+adljdQ4woLlJ+Wg4c48OCFQWCHjirnlZoBvsvvHRxLADuWAuF mqx2tNKCcGfhv8Oqer/4BWuRkYc2tDg3tCQr1qpAf61vW9qjKnO378RtmnmoeGrq+9By J6wA== X-Gm-Message-State: AOAM5334zA+bnr3qHd1gZTbaN+iBhI9GMrIAA/LqxIEw2NSVMYH5MlHa bBYEYaFzf81nFbHy9j3TqaMVvw== X-Google-Smtp-Source: ABdhPJyrRe7WC9rYZU4zM+T2QsvPbJ3R6A6PUt9K8FVjeRo+C4WQ5fkvznW13B6k9nJp6oN0THDxwQ== X-Received: by 2002:a1c:4e06:: with SMTP id g6mr3363475wmh.119.1605823003029; Thu, 19 Nov 2020 13:56:43 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 20/28] target/arm: Implement new v8.1M VLLDM and VLSTM encodings Date: Thu, 19 Nov 2020 21:56:09 +0000 Message-Id: <20201119215617.29887-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" v8.1M adds new encodings of VLLDM and VLSTM (where bit 7 is set). The only difference is that: * the old T1 encodings UNDEF if the implementation implements 32 Dregs (this is currently architecturally impossible for M-profile) * the new T2 encodings have the implementation-defined option to read from memory (discarding the data) or write UNKNOWN values to memory for the stack slots that would be D16-D31 We choose not to make those accesses, so for us the two instructions behave identically assuming they don't UNDEF. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/m-nocp.decode | 2 +- target/arm/translate-vfp.c.inc | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode index ccd62e8739a..6699626d7cb 100644 --- a/target/arm/m-nocp.decode +++ b/target/arm/m-nocp.decode @@ -36,7 +36,7 @@ =20 { # Special cases which do not take an early NOCP: VLLDM and VLSTM - VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 + VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 op:1 000 0000 # VSCCLRM (new in v8.1M) is similar: VSCCLRM 1110 1100 1.01 1111 .... 1011 imm:7 0 vd=3D%vd_dp size=3D3 VSCCLRM 1110 1100 1.01 1111 .... 1010 imm:8 vd=3D%vd_sp size=3D2 diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 1c2d31f6f30..c974d5b0e16 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -3814,6 +3814,31 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_V= LLDM_VLSTM *a) !arm_dc_feature(s, ARM_FEATURE_V8)) { return false; } + + if (a->op) { + /* + * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not + * to take the IMPDEF option to make memory accesses to the stack + * slots that correspond to the D16-D31 registers (discarding + * read data and writing UNKNOWN values), so for us the T2 + * encoding behaves identically to the T1 encoding. + */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + } else { + /* + * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs. + * This is currently architecturally impossible, but we add the + * check to stay in line with the pseudocode. Note that we must + * emit code for the UNDEF so it takes precedence over the NOCP. + */ + if (dc_isar_feature(aa32_simd_r32, s)) { + unallocated_encoding(s); + return true; + } + } + /* * If not secure, UNDEF. We must emit code for this * rather than returning false so that this takes --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605824404; cv=none; d=zohomail.com; s=zohoarc; b=B11XkSGo9Q8trEx97/DP6FzI1dH+q6+LmBX+pfQxMulII10rDFCyuRg4goALmuqZyJopgUGA7sUHYE/85cXp0GURpgojj+/X1awbhZv0Rd/TINiDrZajYlfmJ3jSkbZNCeN5ZLuXx7ol3WccAQAlDqICN0hp7bolGiG1wC1J8nY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605824404; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IYl49JEXLJ4NfyGT6TJwXfRcF2SPUTrLyQsnI7fa5Vo=; b=bLXwd5p587eKlS6qKZb6KrhUi6804w6z8epAf7aeDR1tuLqRiuCm5CLb9joiOfnwBDUfESKKuiYU5gByKylG/EbcBOnDhPtPGnmbTZEZz/iL0rAsb5pSqS9uuB7nSuq6o6saafI5lSAUt2KhUsJopTl0udU2ETmRaHXP3gNwpAY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605824404740238.28017620446929; Thu, 19 Nov 2020 14:20:04 -0800 (PST) Received: from localhost ([::1]:53490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfsHb-0003va-Jr for importer@patchew.org; Thu, 19 Nov 2020 17:20:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51674) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrvJ-00015E-2r for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:01 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:38626) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrv4-0004F5-Ty for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:00 -0500 Received: by mail-wm1-x343.google.com with SMTP id 1so8077326wme.3 for ; Thu, 19 Nov 2020 13:56:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=IYl49JEXLJ4NfyGT6TJwXfRcF2SPUTrLyQsnI7fa5Vo=; b=RW65dYVUokAroAYmmJpkqUnENT9sMP0nallQRhd0kU0t/hoFmbuIswAHFv2fMl+/GA Ik8qLEPuDJ7lv+b22tytoetx7VCDoDaKy1v6gbaGd2qnhCs4g1V5ays4E0z5fi/27ki3 NCAFhWgC5OttC5+cPeXCCn1JR1bIsPi2TxpH68MnTT9666ftSfMpiB49p1TQofN2/Kxs k9Y3NMeMLjo/ihCrWIPALS4dk76ZxK4UN28iRsInnpcyIFWe4/NkOLtOTemac7C/YquQ Fc0nkr3gp/kKGEXheQadq+1GXz9jUqrOWI95vZOGOmdc3D9a11SBAc4X0ge2nyhmctzK RqlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IYl49JEXLJ4NfyGT6TJwXfRcF2SPUTrLyQsnI7fa5Vo=; b=eQCDiSlOeSkI3gPlmX9+1mH3VeciwIYZ8EGAZa/9+jbCalFx7Zl+UdzAMRNkkIqfKv iCU5G00gNFmOVh1RUMqPphOujshoqmM6igC1RUpgvbpRNlyAejzjzBmvtbpnV9riAkW/ LDFrLJ7CH+3+Itqhi73Xg2+U5fbEe7stb8eyZCmYxiLswPJE1N0CX2gP9lxbdMtYtTu7 FaaefStSAQEZlvo2AxW2KCGM3AyNua9qdsZmCQbmxkuZfm5y6YeWnHI/pqpTAKz4Yt3k zIL/oW9gwMKa6q5DJG8tzRWOIYd0B6R154tUgCrQ2TIVMJxC4A5BV0gMvRAIe9CsMJ2q OYog== X-Gm-Message-State: AOAM532eJGltYtFe3X2Dx16Zdp13lB6dJUAJgnGHqRsXLPwX0NckM18C smCv2rzEjkmO9uSxSpixzxtNPrV9VjURDA== X-Google-Smtp-Source: ABdhPJxvVI/1BYdgnRBy3xNUFt3qZgRraeg6gk3AiE8hGzTnuq6+JpDzafrmWg6FA+Nh2K3Ziylakg== X-Received: by 2002:a1c:a5d8:: with SMTP id o207mr6629056wme.0.1605823004064; Thu, 19 Nov 2020 13:56:44 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 21/28] hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN Date: Thu, 19 Nov 2020 21:56:10 +0000 Message-Id: <20201119215617.29887-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The CCR is a register most of whose bits are banked between security states but where BFHFNMIGN is not, and we keep it in the non-secure entry of the v7m.ccr[] array. The logic which tries to handle this bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS is zero" requirement; correct the omission. Signed-off-by: Peter Maydell --- hw/intc/armv7m_nvic.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index effc4a784ca..deb4bd56c95 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1100,6 +1100,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t of= fset, MemTxAttrs attrs) */ val =3D cpu->env.v7m.ccr[attrs.secure]; val |=3D cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; + /* BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0 */ + if (!attrs.secure) { + if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { + val &=3D ~R_V7M_CCR_BFHFNMIGN_MASK; + } + } return val; case 0xd24: /* System Handler Control and State (SHCSR) */ if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { @@ -1662,6 +1668,11 @@ static void nvic_writel(NVICState *s, uint32_t offse= t, uint32_t value, (cpu->env.v7m.ccr[M_REG_NS] & ~R_V7M_CCR_BFHFNMIGN_MASK) | (value & R_V7M_CCR_BFHFNMIGN_MASK); value &=3D ~R_V7M_CCR_BFHFNMIGN_MASK; + } else { + /* BFHFNMIGN is RAZ/WI from NS if AIRCR.BFHFNMINS is 0 */ + if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { + value &=3D ~R_V7M_CCR_BFHFNMIGN_MASK; + } } =20 cpu->env.v7m.ccr[attrs.secure] =3D value; --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605824483; cv=none; d=zohomail.com; s=zohoarc; b=Vpbpp85PoRouOCN+/3GmI1CiXh/34kuExjoVe0SMv0kYN3EhIqAKt6eu+r90ommVzHOWgXj7XCjKchiKavXuL7c3xNjsrSoRZ3Qmr/3buNeiKk9xItnoIoNh1KaD4+ell2vKoOJiM9fFOt4cb8Jkwuei0ziGQ8SJ/YMPFjJXLSo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605824483; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FpA8YdBjlu14/nCrS6Lp83etaqEBGx7TEBIGVpu3Jpk=; b=K6ETEqA3oXUKUROsX8oriIFeKxYEt3wb71k8Da9WDOgeMtBrVpjrrVPzFVZd0vGZZTbjRgRmbGdJub2E5ORuVFW+QvO2LSN7zsdb21s2Vcl9oW4yPTfX83MJgTv85gB7P897Ho+gk4Ocp2oFCaI5tRjZvhW6zY7m7x2AzuQf0uY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605824483131343.7735823415935; Thu, 19 Nov 2020 14:21:23 -0800 (PST) Received: from localhost ([::1]:55204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfsIr-0004gl-Qc for importer@patchew.org; Thu, 19 Nov 2020 17:21:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51702) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrvJ-00016h-Th for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:01 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:47073) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrv4-0004FJ-Tm for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:01 -0500 Received: by mail-wr1-x443.google.com with SMTP id d12so7934300wrr.13 for ; Thu, 19 Nov 2020 13:56:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FpA8YdBjlu14/nCrS6Lp83etaqEBGx7TEBIGVpu3Jpk=; b=qXqI9wb6HJ6sXwzyb+WpiQCPa7hLU3IDz9099pavJn/uvGGybNrgLTFQrP0QoDkLDW /h+6Ofkh5P/Z06RliBmuw5Ef4cMZNULDRfeoDjza8nSuOBUA5XKURpAZB3mGBOWcdYVz rPuEmJNCKQm9Bo6w6t8Tzwa+7e4fspOJ7Kk1q01kHXPr+R5nAD4KM5MYto44xZsVk7zT E75lGDqV06qSWezP80tCU++BaQZ9KhrJadBI6xI0fF8xV/xGokc07IMz97bIKmrKPr0P hoo3mrQdtPSWq2OuDzvt71ISfBzw25fNr+JMaP7Pggfy5bFHAfbpRjPzz5ZlyYfQ5ra1 WdNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FpA8YdBjlu14/nCrS6Lp83etaqEBGx7TEBIGVpu3Jpk=; b=TL9XMwPZi+BpRWhy7FVQsneSUCPiH/11KWlL53HC1VHZGbA57AeFJwcY6FrCsZ45XT jHR+1Iv0BybO9uon8+Wz2ZRs4DIF001S9rzqeaz2mKJtVM4cYB2RBuocp6MIKL+Zoc6y MySmuFHs7rJDJvpV2eKoF/MRYiWV4hW+2zsSn9cIrv5bCfXt1e1aYMu6NhOwpHJz9KFW ns8taS5dG4G6AzE2BlQh3Ag5+udJGTfJ9Oyj7IdCKQUH2JBvLCzkm+jaJpoxzN+oezY7 hcH8QyzcF4dE3B0KpmscT86Wye/iXrrH5IpzNPBMe+j3TprBy844WP55wqbtFgdXRR3w fu7g== X-Gm-Message-State: AOAM530PNqwJNTjBoo9L78GqgyAjMt7qL+TjLa63XFUWB4LY/hrxaemu UCLzP7ilRki1uLz6YEZ+/Y2DKJzvEOZTRw== X-Google-Smtp-Source: ABdhPJy5FNOkj9U1o22EC4Hc53bBKhqbfOvsuTBwDhx4IAHg+P6PIfZd750odasuQNCUl8+CQwoObw== X-Received: by 2002:a05:6000:c7:: with SMTP id q7mr12007763wrx.137.1605823005223; Thu, 19 Nov 2020 13:56:45 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 22/28] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit Date: Thu, 19 Nov 2020 21:56:11 +0000 Message-Id: <20201119215617.29887-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" v8.1M introduces a new TRD flag in the CCR register, which enables checking for stack frame integrity signatures on SG instructions. This bit is not banked, and is always RAZ/WI to Non-secure code. Adjust the code for handling CCR reads and writes to handle this. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 ++ hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++-------- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 47cb5032ce9..22c55c81933 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1611,6 +1611,8 @@ FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1) FIELD(V7M_CCR, DC, 16, 1) FIELD(V7M_CCR, IC, 17, 1) FIELD(V7M_CCR, BP, 18, 1) +FIELD(V7M_CCR, LOB, 19, 1) +FIELD(V7M_CCR, TRD, 20, 1) =20 /* V7M SCR bits */ FIELD(V7M_SCR, SLEEPONEXIT, 1, 1) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index deb4bd56c95..c901d20ae00 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1095,8 +1095,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) } return cpu->env.v7m.scr[attrs.secure]; case 0xd14: /* Configuration Control. */ - /* The BFHFNMIGN bit is the only non-banked bit; we - * keep it in the non-secure copy of the register. + /* + * Non-banked bits: BFHFNMIGN (stored in the NS copy of the regist= er) + * and TRD (stored in the S copy of the register) */ val =3D cpu->env.v7m.ccr[attrs.secure]; val |=3D cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; @@ -1645,17 +1646,25 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, cpu->env.v7m.scr[attrs.secure] =3D value; break; case 0xd14: /* Configuration Control. */ + { + uint32_t mask; + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { goto bad_offset; } =20 /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */ - value &=3D (R_V7M_CCR_STKALIGN_MASK | - R_V7M_CCR_BFHFNMIGN_MASK | - R_V7M_CCR_DIV_0_TRP_MASK | - R_V7M_CCR_UNALIGN_TRP_MASK | - R_V7M_CCR_USERSETMPEND_MASK | - R_V7M_CCR_NONBASETHRDENA_MASK); + mask =3D R_V7M_CCR_STKALIGN_MASK | + R_V7M_CCR_BFHFNMIGN_MASK | + R_V7M_CCR_DIV_0_TRP_MASK | + R_V7M_CCR_UNALIGN_TRP_MASK | + R_V7M_CCR_USERSETMPEND_MASK | + R_V7M_CCR_NONBASETHRDENA_MASK; + if (arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && attrs.secure) { + /* TRD is always RAZ/WI from NS */ + mask |=3D R_V7M_CCR_TRD_MASK; + } + value &=3D mask; =20 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */ @@ -1677,6 +1686,7 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, =20 cpu->env.v7m.ccr[attrs.secure] =3D value; break; + } case 0xd24: /* System Handler Control and State (SHCSR) */ if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { goto bad_offset; --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605824674; cv=none; d=zohomail.com; s=zohoarc; b=W8XEiN5Mq4CW6HV3FAzOtU2Jdwzv+fZFtxXnEAlMkGCN5EA2+YhHbAxsdkD12DCoMy5126nZt3ajkGh3EPRl5KGC8+b+tRNqfua8L1QCckbVD2PW/5ZC9TdK3TpdK0JxyYGUuqMJfCAZ+BloY2rXxtIO41h+7KVTGX9MFuROlX0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605824674; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bRQ6LKkswMJcfs4ISAyj5r3mJc9kOQ5yoQJcCkeM7Dg=; b=g3xV7NZvYciZTTwOyEFHiA4Ry9pVSzV0ZDaNVxPDoMJTkdK6PPePJcDD0qCq7SvRU5jF6YcbIItKVHyvQkDJO3VX8a9v20RMXZLaAloGnigkRf+7CRIc+VBKcUAeCv8BQGUsTd31wZAFxxpbNc1Cgjezz1z/d4j91yU2f5faCjk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605824674937148.08186549967309; Thu, 19 Nov 2020 14:24:34 -0800 (PST) Received: from localhost ([::1]:36004 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfsLx-0008WB-Pm for importer@patchew.org; Thu, 19 Nov 2020 17:24:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51718) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrvK-00017b-Gn for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:02 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:56109) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrv6-0004FT-SV for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:02 -0500 Received: by mail-wm1-x343.google.com with SMTP id c9so8565242wml.5 for ; Thu, 19 Nov 2020 13:56:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bRQ6LKkswMJcfs4ISAyj5r3mJc9kOQ5yoQJcCkeM7Dg=; b=ANldRKYfYFp7ZWO5tnor1LhxHF+ZknTbld/DqkdJZfbDDg87aNMMAaO/2uM4+myX4j AQCPJY3mNtq7Lnb+zc9QQDsHEEMnl4CRvLXJDj4bqQr/+3HoS0HR43/3AWzw9tn8GK3t r8934wzE8MNPfflF4bi+aVvLsBpoOpVpoWOYW85RbeWu3ZoUCcVtQULcc680G0LvZdmR P5I93ZIPCpa3KZipFJVQLuAkNORaPEzGejRURcNIttBWOLQ1Lpt37UdI7Me88F7ajYYX 6RK45BSQiTMTuGgP7H+Z1OhyixwvT9rIPQygEZWj5dq/gw92HGIzlUWSZxmFCae5BBXY z6MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bRQ6LKkswMJcfs4ISAyj5r3mJc9kOQ5yoQJcCkeM7Dg=; b=BTMFk5jRfD2ZPvdZKfJreQBI0OcU+ZpyVu0I69AvmVMLeVsImIUPLpxbMI36ZeKo/V rob3YBb/zQvyeEL89rBtfl8agSQs7IGtuXJNylMyKTnrBDqO9vtIFrS81s1b105A/v/X v8fEFYZ1/9a0zuF6R7ziZL0Bf5zE/qHWNQ2SM48oDs7HFYoll9lJejbmFru1u+WXa3SC QCtlfyz88WoPt3dgXgjpBP5ssb+sJLKvZjOA+m5ZNoZJTNVi259jszRvlS2C3zGXARa9 M8zFZdxVCos4QtQJit7BMuBvc+GgHdNVmeNICJLMUTK9VfGY59n02fnLzEUG5JczcZ7x Yg3w== X-Gm-Message-State: AOAM5335K+nR9ZN8Rt8cCcdr9ITztge0div70cgwPNtiHrSqOeSrU3dd hL/9neYmFVV7DLuHWkmX7qubKg== X-Google-Smtp-Source: ABdhPJzSs8mLfvlR586qbDijNpMHuoAB8Tovot2v+VdyyrTYyx0iKvJyws23Bj/POiufr5XCd/mC5g== X-Received: by 2002:a7b:c92d:: with SMTP id h13mr6481295wml.96.1605823006157; Thu, 19 Nov 2020 13:56:46 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 23/28] target/arm: Implement CCR_S.TRD behaviour for SG insns Date: Thu, 19 Nov 2020 21:56:12 +0000 Message-Id: <20201119215617.29887-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" v8.1M introduces a new TRD flag in the CCR register, which enables checking for stack frame integrity signatures on SG instructions. Add the code in the SG insn implementation for the new behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/m_helper.c | 86 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 0bdd3cc10e9..643dcafb83d 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -1999,6 +1999,64 @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUId= x mmu_idx, return true; } =20 +static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx, + uint32_t addr, uint32_t *spdata) +{ + /* + * Read a word of data from the stack for the SG instruction, + * writing the value into *spdata. If the load succeeds, return + * true; otherwise pend an appropriate exception and return false. + * (We can't use data load helpers here that throw an exception + * because of the context we're called in, which is halfway through + * arm_v7m_cpu_do_interrupt().) + */ + CPUState *cs =3D CPU(cpu); + CPUARMState *env =3D &cpu->env; + MemTxAttrs attrs =3D {}; + MemTxResult txres; + target_ulong page_size; + hwaddr physaddr; + int prot; + ARMMMUFaultInfo fi =3D {}; + ARMCacheAttrs cacheattrs =3D {}; + uint32_t value; + + if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr, + &attrs, &prot, &page_size, &fi, &cacheattrs)) { + /* MPU/SAU lookup failed */ + if (fi.type =3D=3D ARMFault_QEMU_SFault) { + qemu_log_mask(CPU_LOG_INT, + "...SecureFault during stack word read\n"); + env->v7m.sfsr |=3D R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVAL= ID_MASK; + env->v7m.sfar =3D addr; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); + } else { + qemu_log_mask(CPU_LOG_INT, + "...MemManageFault during stack word read\n"); + env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_DACCVIOL_MASK | + R_V7M_CFSR_MMARVALID_MASK; + env->v7m.mmfar[M_REG_S] =3D addr; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, false); + } + return false; + } + value =3D address_space_ldl(arm_addressspace(cs, attrs), physaddr, + attrs, &txres); + if (txres !=3D MEMTX_OK) { + /* BusFault trying to read the data */ + qemu_log_mask(CPU_LOG_INT, + "...BusFault during stack word read\n"); + env->v7m.cfsr[M_REG_NS] |=3D + (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK); + env->v7m.bfar =3D addr; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); + return false; + } + + *spdata =3D value; + return true; +} + static bool v7m_handle_execute_nsc(ARMCPU *cpu) { /* @@ -2055,6 +2113,34 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) */ qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx= 32 ", executing it\n", env->regs[15]); + + if (cpu_isar_feature(aa32_m_sec_state, cpu) && + !arm_v7m_is_handler_mode(env)) { + /* + * v8.1M exception stack frame integrity check. Note that we + * must perform the memory access even if CCR_S.TRD is zero + * and we aren't going to check what the data loaded is. + */ + uint32_t spdata, sp; + + /* + * We know we are currently NS, so the S stack pointers must be + * in other_ss_{psp,msp}, not in regs[13]/other_sp. + */ + sp =3D v7m_using_psp(env) ? env->v7m.other_ss_psp : env->v7m.other= _ss_msp; + if (!v7m_read_sg_stack_word(cpu, mmu_idx, sp, &spdata)) { + /* Stack access failed and an exception has been pended */ + return false; + } + + if (env->v7m.ccr[M_REG_S] & R_V7M_CCR_TRD_MASK) { + if (((spdata & ~1) =3D=3D 0xfefa125a) || + !(env->v7m.control[M_REG_S] & 1)) { + goto gen_invep; + } + } + } + env->regs[14] &=3D ~1; env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; switch_v7m_security_state(env, true); --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605824279; cv=none; d=zohomail.com; s=zohoarc; b=P5pS/A7VRu/vWagKtAN8ou9uOJdrO2OwknJ/mkiU/CyeXOq7YzSaVqnX/PecwIjHaMNpMKTImfySjyCzxNZjE4XxM3lANsMYghOK/npkyOWgrQfkmj+4xCqoeaDNju99m0fpqQB0fRTXM1xI+Y3h5BmdD5GFWhSodvuE1cJNTl0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605824279; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qhzFhrjKvRUsyJDSYv8WmAYUo+hfPFVK5biMG9ZuE5U=; b=FDQRqSQcEPKrgr4hyFuDO+9XNwRZXdndnattasjIylDhtlcGqoLQwYfKJKMoYUL90qZFrd943BBizBAyshfeVbMdVzdLyn9XJ5cWrTaevEBZBR9cNXUhrlUUvVwn4W7ESKuhXu/ewld9ynLoVNgPGxWLBebxjw6ynpzduvVmZyE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605824279237905.515056916224; Thu, 19 Nov 2020 14:17:59 -0800 (PST) Received: from localhost ([::1]:49338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfsFa-00025W-2x for importer@patchew.org; Thu, 19 Nov 2020 17:17:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrvJ-00016A-Jg for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:01 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:39028) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrv6-0004Fm-SM for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:01 -0500 Received: by mail-wr1-x444.google.com with SMTP id o15so8013788wru.6 for ; Thu, 19 Nov 2020 13:56:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qhzFhrjKvRUsyJDSYv8WmAYUo+hfPFVK5biMG9ZuE5U=; b=nRCltpfiNj8puXdNtUbVovJr2ZSkVIJKxwz1gIuU3ZLTadSYkjYvYVwfzryu8ltrOm d3aKVhhbGKrjP9WevHXOLpuyD1e9zGicapjq1Pf4Akz16QL4FBk7NZRSgUWpsphyU9ax iDqDRkjf/Hro1ZYHK78svN/WFr6u6u0NxolQvLKPFn8tkyHPLRwiU7Ejcv7zJUWqnpGo 9ubtkDh7aEuItxACr2SqBisEoN8f5KVpdpN0GjCLKKMi+TYjI/wZJnYn88vRLh9+i12D V0XMwRedslP4NI1XR5OfzAqKgCnd7fhdsCm3aY04IDBLN2MFHDbzC+D9rA/YpyR+ahKw 9dng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qhzFhrjKvRUsyJDSYv8WmAYUo+hfPFVK5biMG9ZuE5U=; b=UUpI0UUV5naoXdoHFcJkcq2Kc6vtKifDkxNdyeSkJkmBfvj4zVAqR58gImUN7df4Ac MOgY2qZ+rPRknTPwE/3OjOITgcMKDagj5/mquOQ0RTZxZ7uLeZWSbcMKmjI90nnwiy3x yvIogRuyDWNt2ddymAc6P+qH/hwN13CRvzo7xy+4zTFd3OJ9805I5VXAjVKOyCJN8rDS csrMFfW/wnV6WPeE1PNKWi+jHKUFN0af+eHV6M0eZuelo8EVXdcGegcnEHbhFJsRYKkT GxzwD7UHCQTqd0bq5vviM9Zs3LE0gYdep6Lpr6834TgQgQipPwBIiHqJllTnilttWQly ET8g== X-Gm-Message-State: AOAM53060/MUy6rqHdsuk6LmMOZYyEPKqV8T7S49VBkiLLV2KkDFXOg5 eO6R5I2B0ZtWAsedkFEWofjDczywQ9JsZg== X-Google-Smtp-Source: ABdhPJzJK5llb6Bz14AVQJcW8CyMO84vyI3I+hK+/PrCw+2lDrWaXGJwUpxwg2bT+F1lVTsGPkd49Q== X-Received: by 2002:adf:e950:: with SMTP id m16mr13516157wrn.0.1605823007281; Thu, 19 Nov 2020 13:56:47 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 24/28] hw/intc/armv7m_nvic: Fix "return from inactive handler" check Date: Thu, 19 Nov 2020 21:56:13 +0000 Message-Id: <20201119215617.29887-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In commit 077d7449100d824a4 we added code to handle the v8M requirement that returns from NMI or HardFault forcibly deactivate those exceptions regardless of what interrupt the guest is trying to deactivate. Unfortunately this broke the handling of the "illegal exception return because the returning exception number is not active" check for those cases. In the pseudocode this test is done on the exception the guest asks to return from, but because our implementation was doing this in armv7m_nvic_complete_irq() after the new "deactivate NMI/HardFault regardless" code we ended up doing the test on the VecInfo for that exception instead, which usually meant failing to raise the illegal exception return fault. In the case for "configurable exception targeting the opposite security state" we detected the illegal-return case but went ahead and deactivated the VecInfo anyway, which is wrong because that is the VecInfo for the other security state. Rearrange the code so that we first identify the illegal return cases, then see if we really need to deactivate NMI or HardFault instead, and finally do the deactivation. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/armv7m_nvic.c | 59 +++++++++++++++++++++++-------------------- 1 file changed, 32 insertions(+), 27 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index c901d20ae00..fa8aeca82ec 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -832,10 +832,40 @@ int armv7m_nvic_complete_irq(void *opaque, int irq, b= ool secure) { NVICState *s =3D (NVICState *)opaque; VecInfo *vec =3D NULL; - int ret; + int ret =3D 0; =20 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); =20 + trace_nvic_complete_irq(irq, secure); + + if (secure && exc_is_banked(irq)) { + vec =3D &s->sec_vectors[irq]; + } else { + vec =3D &s->vectors[irq]; + } + + /* + * Identify illegal exception return cases. We can't immediately + * return at this point because we still need to deactivate + * (either this exception or NMI/HardFault) first. + */ + if (!exc_is_banked(irq) && exc_targets_secure(s, irq) !=3D secure) { + /* + * Return from a configurable exception targeting the opposite + * security state from the one we're trying to complete it for. + * Clear vec because it's not really the VecInfo for this + * (irq, secstate) so we mustn't deactivate it. + */ + ret =3D -1; + vec =3D NULL; + } else if (!vec->active) { + /* Return from an inactive interrupt */ + ret =3D -1; + } else { + /* Legal return, we will return the RETTOBASE bit value to the cal= ler */ + ret =3D nvic_rettobase(s); + } + /* * For negative priorities, v8M will forcibly deactivate the appropria= te * NMI or HardFault regardless of what interrupt we're being asked to @@ -865,32 +895,7 @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bo= ol secure) } =20 if (!vec) { - if (secure && exc_is_banked(irq)) { - vec =3D &s->sec_vectors[irq]; - } else { - vec =3D &s->vectors[irq]; - } - } - - trace_nvic_complete_irq(irq, secure); - - if (!vec->active) { - /* Tell the caller this was an illegal exception return */ - return -1; - } - - /* - * If this is a configurable exception and it is currently - * targeting the opposite security state from the one we're trying - * to complete it for, this counts as an illegal exception return. - * We still need to deactivate whatever vector the logic above has - * selected, though, as it might not be the same as the one for the - * requested exception number. - */ - if (!exc_is_banked(irq) && exc_targets_secure(s, irq) !=3D secure) { - ret =3D -1; - } else { - ret =3D nvic_rettobase(s); + return ret; } =20 vec->active =3D 0; --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605824787; cv=none; d=zohomail.com; s=zohoarc; b=YBPq1t+HvPzpO/bmLhhyZbLGY6jhWM2LhkkARRTV4rb5zc/VV1MiGUWCGEmm3Cnftn0nzJJSQsgUzA99HWP4H5VmRZwkq/5oAc+gSbz2GsUSryukoFbGKJVYI6tY+2ey3hXZioCx0l3+EJ0j723RnF7zDFnaHVFwmPVgRGnu61Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605824787; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hc3nzG7RWM4GF2g+cHgdNWNtIjr6cjy/0CNOT4ryRb8=; b=gLvWL+5n8wsG4GGUHkqvhiv5lPulXOe+VLwPkgqpa5EjSVXUkozDkViriNR4IIubUoo49l6il23BAn9mF7cuWqGuQcKAp/Ol448zZJAEcn3XEjGhoSSsmDqUcYu2OqlWikSaaGXZ8m3QWL+woy45c11gF7k3aJoioQkeEqVt44w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605824786956527.5423101761364; Thu, 19 Nov 2020 14:26:26 -0800 (PST) Received: from localhost ([::1]:41280 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfsNl-0002LR-IL for importer@patchew.org; Thu, 19 Nov 2020 17:26:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51752) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrvL-00019O-8I for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:03 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:41157) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrv7-0004Fw-Nv for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:02 -0500 Received: by mail-wr1-x42a.google.com with SMTP id 23so7985344wrc.8 for ; Thu, 19 Nov 2020 13:56:49 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hc3nzG7RWM4GF2g+cHgdNWNtIjr6cjy/0CNOT4ryRb8=; b=RQtwC5zInM3ITyRG2NIjSUH0Hu3QyUL7tLZMXcUmuR+TZeBRTj4LmVL/0LfLr1QX4L 4ahWFWr9QLLLvi/ES4BZEFNgJwpVaDAOtWt2kTyoKLbOFrL9GuHuXTwszXR+4M4dR02V 0dR6yb+HEHEbrBjqD6DoLUigEu61FnqtKzE+t74UMXNioSjfXl964TulEIthU6J1RcVw bb5YPS8Ye+znT1kEHjUR+1igRpZKybkG0JEhURgqKX1Pfd9zjnVxSg+bSM8Hr9Fekilz MsJYWwf6d++jHbl+ARCmMLSvQQYHPNOflfZSrMQ02ZkRO26bwLDN7I31iL7M+EgY3ecT FDvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hc3nzG7RWM4GF2g+cHgdNWNtIjr6cjy/0CNOT4ryRb8=; b=a/AAm997pfvg/JuJSBvqZsPbu5LUYMMB7PYDskYFt2Vf75JDEZUS+YfL7uMgfViD5o jA523HUbukHms3u5dMLTVJiK+J37I8VHke1IAatfRWpOVygBYhTodJN+z1NnVky1bSxy ikV0YCjhS4/NnzglSfKM1StPk/mjSCnso79gT4vnaZKVGIo9heK1wep41gm+dHhQAaO/ pODfCyhLDbFz2QK6PUKpusvN63LFDfxXUMqDF3SUCY7spOmTG+iQEdZXxJ0Hdxv5ONet YjqIctBITEpiDCJNhhpKBq4Rvr5vGroNSueLJpzVUox4M7ShxFm2oUDjhf4ztvynUk0R NM5g== X-Gm-Message-State: AOAM530Rhdq4CMaQ/hK566BSKNUGj6/xhSz1Cgq9XS+l8xbtCUwTX4Kb aJNP5pjFp9agLsRtg1GpE07diwwDY2D/oQ== X-Google-Smtp-Source: ABdhPJy/u2on9eFhgXC+YN5vLUQVIz+jyBnF341YbEOOEkeBIiJ6OCnH+hlbwERipI0KNNyWHK9Q0A== X-Received: by 2002:adf:f881:: with SMTP id u1mr13311461wrp.103.1605823008351; Thu, 19 Nov 2020 13:56:48 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 25/28] target/arm: Implement M-profile "minimal RAS implementation" Date: Thu, 19 Nov 2020 21:56:14 +0000 Message-Id: <20201119215617.29887-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For v8.1M the architecture mandates that CPUs must provide at least the "minimal RAS implementation" from the Reliability, Availability and Serviceability extension. This consists of: * an ESB instruction which is a NOP -- since it is in the HINT space we need only add a comment * an RFSR register which will RAZ/WI * a RAZ/WI AIRCR.IESB bit -- the code which handles writes to AIRCR does not allow setting of RES0 bits, so we already treat this as RAZ/WI; add a comment noting that this is deliberate * minimal implementation of the RAS register block at 0xe0005000 -- this will be in a subsequent commit * setting the ID_PFR0.RAS field to 0b0010 -- we will do this when we add the Cortex-M55 CPU model Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 14 ++++++++++++++ target/arm/t32.decode | 4 ++++ hw/intc/armv7m_nvic.c | 13 +++++++++++++ 3 files changed, 31 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 22c55c81933..7e6c881a7e2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1827,6 +1827,15 @@ FIELD(ID_MMFR4, LSM, 20, 4) FIELD(ID_MMFR4, CCIDX, 24, 4) FIELD(ID_MMFR4, EVT, 28, 4) =20 +FIELD(ID_PFR0, STATE0, 0, 4) +FIELD(ID_PFR0, STATE1, 4, 4) +FIELD(ID_PFR0, STATE2, 8, 4) +FIELD(ID_PFR0, STATE3, 12, 4) +FIELD(ID_PFR0, CSV2, 16, 4) +FIELD(ID_PFR0, AMU, 20, 4) +FIELD(ID_PFR0, DIT, 24, 4) +FIELD(ID_PFR0, RAS, 28, 4) + FIELD(ID_PFR1, PROGMOD, 0, 4) FIELD(ID_PFR1, SECURITY, 4, 4) FIELD(ID_PFR1, MPROGMOD, 8, 4) @@ -3573,6 +3582,11 @@ static inline bool isar_feature_aa32_predinv(const A= RMISARegisters *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) !=3D 0; } =20 +static inline bool isar_feature_aa32_ras(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) !=3D 0; +} + static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) { return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) !=3D 0; diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f045eb62c84..8b2c487fa7a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -307,6 +307,10 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 ..= .. @rdm # SEV 1111 0011 1010 1111 1000 0000 0000 0100 # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 + # For M-profile minimal-RAS ESB can be a NOP, which is the + # default behaviour since it is in the hint space. + # ESB 1111 0011 1010 1111 1000 0000 0001 0000 + # The canonical nop ends in 0000 0000, but the whole rest # of the space is "reserved hint, behaves as nop". NOP 1111 0011 1010 1111 1000 0000 ---- ---- diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index fa8aeca82ec..c42b291f881 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1489,6 +1489,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t of= fset, MemTxAttrs attrs) return 0; } return cpu->env.v7m.sfar; + case 0xf04: /* RFSR */ + if (!cpu_isar_feature(aa32_ras, cpu)) { + goto bad_offset; + } + /* We provide minimal-RAS only: RFSR is RAZ/WI */ + return 0; case 0xf34: /* FPCCR */ if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; @@ -1617,6 +1623,7 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, R_V7M_AIRCR_PRIGROUP_SHIFT, R_V7M_AIRCR_PRIGROUP_LENGTH); } + /* AIRCR.IESB is RAZ/WI because we implement only minimal RAS = */ if (attrs.secure) { /* These bits are only writable by secure */ cpu->env.v7m.aircr =3D value & @@ -2037,6 +2044,12 @@ static void nvic_writel(NVICState *s, uint32_t offse= t, uint32_t value, } break; } + case 0xf04: /* RFSR */ + if (!cpu_isar_feature(aa32_ras, cpu)) { + goto bad_offset; + } + /* We provide minimal-RAS only: RFSR is RAZ/WI */ + break; case 0xf34: /* FPCCR */ if (cpu_isar_feature(aa32_vfp_simd, cpu)) { /* Not all bits here are banked. */ --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823854; cv=none; d=zohomail.com; s=zohoarc; b=fpyciIvo9pTr3Shk6izC85f0nUoiauqgaEuwUM83EFtMhiK99MSePPJIopQu0ffU7AShmOr5QT0SsUyOv0KS6udc3/GO0IF9cA7t2F10yVeM+ypDukcPit5ju91/CaqcA2NMOzOYFtNYkf8vS6uEXVkGVLH+SUgJJzYWhlALJP8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823854; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CpeB0JZIf82ouGJAcXNi10kk5fwgUTHRGskoxQo7vDg=; b=hdgkNouB5ItfbyRHffINmL4JrTmdBellkXnrDdyNs5WKQMNVxfV7B9PPwZy4xDXdl3+VYGfv7tadWdZYr377ZCHY0ni7Gjd8gfWqY92j/R/JUPXTzkdLM0wMAU9uyFgdoiZSWsnwlnnfLmkc1+EpgP7iEr/fnpHuFmqpA7b6VfE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605823854041214.7578180769666; Thu, 19 Nov 2020 14:10:54 -0800 (PST) Received: from localhost ([::1]:58354 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfs8g-0002KZ-LX for importer@patchew.org; Thu, 19 Nov 2020 17:10:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51766) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrvL-0001AB-HL for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:03 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:47074) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrv8-0004Gu-V1 for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:03 -0500 Received: by mail-wr1-x444.google.com with SMTP id d12so7934425wrr.13 for ; Thu, 19 Nov 2020 13:56:50 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CpeB0JZIf82ouGJAcXNi10kk5fwgUTHRGskoxQo7vDg=; b=tgNXkwZkzO8/NMl+u6brb0gRnqRQ9Zl9qth9CQwq5YqWCNeUOnD6vZzuOV72Wh6IMS nFrJVTntqy2y6q9z95NeVtwtnLKR1coHlH69KSh01p9ZlN1BE5WmK5qWtw/vsQZb6sWB hE6dn8HMkgnf5RMrtJwGz439OggcRc1CmV9SbPV9NdZi0RGwXuZwQ1PNcf+rfRmwNB+i s1nGD0KD4l8S/zfMDzOtuXzPof1wzcFILB4Nn0dvJKLIwpHm1PSwqE6RGmvuzch+gGS2 pf4J1O6G9c8frSl5SBBzH7gyd9BFzs341zIPCby6ywwA+Tr74YYvSVHtJ2MopTBVJt1q la7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CpeB0JZIf82ouGJAcXNi10kk5fwgUTHRGskoxQo7vDg=; b=kO/nE3EkXr5GG9wGMnTpV0QqABxQOwbqdaRt8DpP1JuQNfPkl0C/MK+lm2ogtzHoQm ia//JkK6+Cx8nxsO1cXEbhyX33llSaAhCnYlu3c6SlX8AYDIsC0JwUjA/kcj2SLB+Uhb fkjtP+eEU3QpLnrQHdtJAvuJjAV0Jh7bsx/RMisrw252cgBwIsyvDiELyn9ZZukGBCS5 eDifDH19XsTdfOdshoXTn+6XTVJ7f0WPCW5g09tlTvVMy/wOy0E2nm+IAVejiATl9Vjs sWBplmbDUvglF2ASBO5YbV+QXkZf5EdRdw5FhFHDE2nn78W53YQHmKSH7RBuxU5JDXu4 ImZQ== X-Gm-Message-State: AOAM533OwZJJR/nZZWf0dqMNJ+J1wNGNGipmWHS22/JUEfMZNJ71bEwQ 7xqv0NPa6iVR+rfxGbACXGcGgHeCRJLLSw== X-Google-Smtp-Source: ABdhPJx7sCOAACqCZbXA+CHbwJtI7rCIQHrufUSImsSy/g7hGs4OTWJdLMPDRVufG3P4Uco+M9VyUg== X-Received: by 2002:adf:db87:: with SMTP id u7mr12938687wri.334.1605823009436; Thu, 19 Nov 2020 13:56:49 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 26/28] hw/intc/armv7m_nvic: Implement read/write for RAS register block Date: Thu, 19 Nov 2020 21:56:15 +0000 Message-Id: <20201119215617.29887-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The RAS feature has a block of memory-mapped registers at offset 0x5000 within the PPB. For a "minimal RAS" implementation we provide no error records and so the only registers that exist in the block are ERRIIDR and ERRDEVID. The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour of the "nvic-default" region is actually valid for minimal-RAS, so the main benefit of providing an explicit implementation of the register block is more accurate LOG_UNIMP messages, and a framework for where we could add a real RAS implementation later if necessary. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/intc/armv7m_nvic.h | 1 + hw/intc/armv7m_nvic.c | 56 +++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 33b6d8810c7..39c71e15936 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -83,6 +83,7 @@ struct NVICState { MemoryRegion sysreg_ns_mem; MemoryRegion systickmem; MemoryRegion systick_ns_mem; + MemoryRegion ras_mem; MemoryRegion container; MemoryRegion defaultmem; =20 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index c42b291f881..5ab77a3530c 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2530,6 +2530,56 @@ static const MemoryRegionOps nvic_systick_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 + +static MemTxResult ras_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + if (attrs.user) { + return MEMTX_ERROR; + } + + switch (addr) { + case 0xe10: /* ERRIIDR */ + /* architect field =3D Arm; product/variant/revision 0 */ + *data =3D 0x43b; + break; + case 0xfc8: /* ERRDEVID */ + /* Minimal RAS: we implement 0 error record indexes */ + *data =3D 0; + break; + default: + qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n", + (uint32_t)addr); + *data =3D 0; + break; + } + return MEMTX_OK; +} + +static MemTxResult ras_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + if (attrs.user) { + return MEMTX_ERROR; + } + + switch (addr) { + default: + qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n", + (uint32_t)addr); + break; + } + return MEMTX_OK; +} + +static const MemoryRegionOps ras_ops =3D { + .read_with_attrs =3D ras_read, + .write_with_attrs =3D ras_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + /* * Unassigned portions of the PPB space are RAZ/WI for privileged * accesses, and fault for non-privileged accesses. @@ -2877,6 +2927,12 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) &s->systick_ns_mem, 1); } =20 + if (cpu_isar_feature(aa32_ras, s->cpu)) { + memory_region_init_io(&s->ras_mem, OBJECT(s), + &ras_ops, s, "nvic_ras", 0x1000); + memory_region_add_subregion(&s->container, 0x5000, &s->ras_mem); + } + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); } =20 --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605823750; cv=none; d=zohomail.com; s=zohoarc; b=HgNc+WagfZAe/XCXcUFGfLL0brD9C+coUTJD7FSDMrT2g/rksYrnyixGjnYlOYtaXQQ5Hs8QVf99T6s1Khcr0Qy4HUZQenBoGxt5iLXhhbw6x4/3r+dnH+qyvZWJuwwhBiIEZTbZUuttzi3BHHoizP0nN34OQNqPBOndHO7CUos= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605823750; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CsDF4FovkQi5FbhTGn1IjOoZht88RJrc3jvTDPCJ+f4=; b=im3kxjzmy+b/PMMQik6K7C1+W1p2qBbv8y37bFgkKP7797rdapSC32/myRibX8nIUr6bHS60qJ3FKgkH0zcki1yuqJday5OWqR69Oy8BYl34mC4pm/wF+A9u3VZIol9fj6KizFKzx08r4ISyND/ia8Qs+lkLjim18DQ7/OPX3pU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605823750908585.8912646950381; Thu, 19 Nov 2020 14:09:10 -0800 (PST) Received: from localhost ([::1]:52800 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfs73-0008UJ-Pz for importer@patchew.org; Thu, 19 Nov 2020 17:09:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51792) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrvN-0001EP-6F for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:05 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:37837) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrvA-0004H7-Jb for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:04 -0500 Received: by mail-wr1-x444.google.com with SMTP id b6so8027305wrt.4 for ; Thu, 19 Nov 2020 13:56:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CsDF4FovkQi5FbhTGn1IjOoZht88RJrc3jvTDPCJ+f4=; b=PuyNaGaF/liAFUxlvAqlL68JNMTQgeT9qx3MW8WXIeFb/KHkQaF1HIlaCeFvwnPvAd NYknIsTIJqoD99La5wvArLw4NBOYHqTV1+XDMFe7o8F1Gvy1DtjNzOyMClWIZLKWa8d8 sYnYMuul4BOC8/BwQUeK7c1l7ajthde9UFlPgs+wOTUW5MYJp11QlMCWhNjOuFlbJcMh 7BoXpe6s4sJ6yfiwPIH+2VeFu4nYP2rMlr+fbuDNaaEZFmTW0ldXOwSKnoNHO36u/qXJ XvO0XNqSZluFbhKIHN0ESs/gViP55GsAj58GrP8YpUQY98qdrt3J1kfQ1JjVD0OkXT+w BFog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CsDF4FovkQi5FbhTGn1IjOoZht88RJrc3jvTDPCJ+f4=; b=Eh+AqojEncY9dpaOeFTRLLNoHKdJoULhin+N4NCq4+vddsswFwEw05F0UULEsw2RLv IsMsXXtatJtC2tVA3xtze8og+p+kiWJp5RCCUqEqxwzU8REQZdJCNH8bxiW77D83lLei OT92uUD8GmmQV2g0Azm0/suR0qwBXN7IQV/B/fGYD4ZDyHwoPvtZC4RU69xLYw4DDSh5 PsSJ1iqqiZBIYc/oM93xkFM0b5wQ3+jEsE15Hz/58393s/nw6JSi3e8ZEjjxbQtTz66f KNguFtsH1icq83Bh7+pYZUJl5SLlKwArGH08xCG3wiOCtr8QtqXcGdh10Q/3PSPgLBro w6Fg== X-Gm-Message-State: AOAM5309z0idlZBb2HT8OqhxmzMIf6KDx0dMo2P9AfxMLxalklR2b+oC RRWw4R9kc5joX1s92EPfAwbFIexsLgLSaQ== X-Google-Smtp-Source: ABdhPJwkEj8B0IdamVUakuI9eF8iGFtDWObx7Y6mmXPmbKA4tgbu+altv592CpAG/x4nByC0dlPXwg== X-Received: by 2002:a5d:474f:: with SMTP id o15mr12479025wrs.100.1605823010527; Thu, 19 Nov 2020 13:56:50 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 27/28] hw/arm/armv7m: Correct typo in QOM object name Date: Thu, 19 Nov 2020 21:56:16 +0000 Message-Id: <20201119215617.29887-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Correct a typo in the name we give the NVIC object. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/arm/armv7m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 944f261dd05..8224d4ade9f 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -136,7 +136,7 @@ static void armv7m_instance_init(Object *obj) =20 memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX); =20 - object_initialize_child(obj, "nvnic", &s->nvic, TYPE_NVIC); + object_initialize_child(obj, "nvic", &s->nvic, TYPE_NVIC); object_property_add_alias(obj, "num-irq", OBJECT(&s->nvic), "num-irq"); =20 --=20 2.20.1 From nobody Sat Apr 20 05:24:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1605824016; cv=none; d=zohomail.com; s=zohoarc; b=CW+EOkE9PQBEw/naLw64jiSIhmSSX21orTsCK2JUoQVHvEILFymDKGI66JbMaEGJwMgKWXDg6owUpl//T09B6d+wb0OJlX7P6XEn9Hrg07TDA7Bl1iApi6TdR//ArfU0tpEGVsrK0bkOtjHIqP+CjY4Z+ffucAlJF/03pfZQLoo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605824016; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aUi6vcMH4o0CYad/653lpbXGwZgjtkuhUa4zld0PALo=; b=n+V6VMhgKkMA20+2fv9NCVV8OzBZa6Q1AUyEmeRfM6DGxVwtOAJO+RPSq981h5SskoKGxxq4DDmLiK03y6cKyl9FOGrVo5N77SCVpeWHf0+N0zvglskUr8eM+9N8cB8pYURz62GlgDZ25Rsrr8IwjqtqyJVeijaWM5VylnVnUGQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605824016429499.98392521625385; Thu, 19 Nov 2020 14:13:36 -0800 (PST) Received: from localhost ([::1]:38556 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfsBF-0005rh-RI for importer@patchew.org; Thu, 19 Nov 2020 17:13:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfrvN-0001G6-SS for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:06 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:33539) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfrvB-0004HP-Sx for qemu-devel@nongnu.org; Thu, 19 Nov 2020 16:57:05 -0500 Received: by mail-wr1-x443.google.com with SMTP id u12so8061014wrt.0 for ; Thu, 19 Nov 2020 13:56:52 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aUi6vcMH4o0CYad/653lpbXGwZgjtkuhUa4zld0PALo=; b=PgQliZ57diIrQv1+baj8vSQMq1u1jLzyk6HTxbSrZ3Ch0G5i0r2wy1aLn9bUXeSSBv EUOHeyNTHUU26GDUIXFaA9cmPmFjuOLPVY2xhv7ynqMV7+1cB1lR7BEwNvWthWmNLs22 dPruNGawe4FrL1tcWPgn48t6KjSsncEPbCupV0bcQWTgr5j1erLwCsGJzIH4E8MAnKKD m5vJgJCirRksrDtsrR3AYvgnzoThzdb7o/vkR2BXL5+uVSweHAEVJmYfFg5DWQWHBdYA PBafRt7YUhzeuygRWEMukJt5LgqiTPAuaUwIkuOmdf6SgzPeaXw3GpS20QpgZho6CWG4 Q46g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aUi6vcMH4o0CYad/653lpbXGwZgjtkuhUa4zld0PALo=; b=lEiHrTSgXOagptznXUQH9OpU9v0Hu/SzKqCywRovE4N/s3uAUcoancCqWqlHpa2z5J XM9sQkQ42kLgJ9PPLRca4XXeaIXqjNWavn9MKa5pJJL8wPTbbOBzvIGrjWdNM6nzPm1X LDDln9UxkLsG7hw1CPYG0Fc+bWWke8XZcXXOxWNv4siuC5PVz/rhnCRf63zH8WoON+th XsUzWD0Fsn94wgjpRHkz+MpFUcecHNuXp1fI1qxCxbk24tlUkZgopPENsV4lOFwcmVpK 7h58pKeSJBaiwXxMN0x7EyIuu+/6Ky9CmCtCqy7Qhhz7S7DFyMkYR3fE+tUcV6WOLIBB 7dLQ== X-Gm-Message-State: AOAM531cWr924sZ28BM+sec7YVUe8XDJtI/QRY33r2DsabZRowArlKxu tHPYWzirAc1VXZ/H4t2rXnRzVGTc/lECrw== X-Google-Smtp-Source: ABdhPJxlp7pM+b5MfsBIs4tC6VXGCBkh32ZYa1IkAXDwl1lkzhgRN8+IjvhAT+2nsJV+5AlxfxV6MA== X-Received: by 2002:adf:dc0a:: with SMTP id t10mr12696594wri.314.1605823011812; Thu, 19 Nov 2020 13:56:51 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 28/28] target/arm: Implement Cortex-M55 model Date: Thu, 19 Nov 2020 21:56:17 +0000 Message-Id: <20201119215617.29887-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Now that we have implemented all the features needed by the v8.1M architecture, we can add the model of the Cortex-M55. This is the configuration without MVE support; we'll add MVE later. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0013e25412f..98544db2df3 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -401,6 +401,46 @@ static void cortex_m33_initfn(Object *obj) cpu->ctr =3D 0x8000c000; } =20 +static void cortex_m55_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_V8_1M); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr =3D 0x410fd221; /* r0p1 */ + cpu->revidr =3D 0; + cpu->pmsav7_dregion =3D 16; + cpu->sau_sregion =3D 8; + /* + * These are the MVFR* values for the FPU, no MVE configuration; + * we will update them later when we implement MVE + */ + cpu->isar.mvfr0 =3D 0x10110221; + cpu->isar.mvfr1 =3D 0x12100011; + cpu->isar.mvfr2 =3D 0x00000040; + cpu->isar.id_pfr0 =3D 0x20000030; + cpu->isar.id_pfr1 =3D 0x00000230; + cpu->isar.id_dfr0 =3D 0x10200000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00111040; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01000000; + cpu->isar.id_mmfr3 =3D 0x00000011; + cpu->isar.id_isar0 =3D 0x01103110; + cpu->isar.id_isar1 =3D 0x02212000; + cpu->isar.id_isar2 =3D 0x20232232; + cpu->isar.id_isar3 =3D 0x01111131; + cpu->isar.id_isar4 =3D 0x01310132; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; + cpu->clidr =3D 0x00000000; /* caches not implemented */ + cpu->ctr =3D 0x8303c003; +} + static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { /* Dummy the TCM region regs for the moment */ { .name =3D "ATCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 0, @@ -655,6 +695,8 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m55", .initfn =3D cortex_m55_initfn, + .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, { .name =3D "ti925t", .initfn =3D ti925t_initfn }, --=20 2.20.1