From nobody Mon Feb 9 12:09:27 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1605750873; cv=none; d=zohomail.com; s=zohoarc; b=bqQWn/OG2xzVv3ODT1aVzZ7NQmUEz/RNb+oRimH+UYrwqMESGM8uCcJ1olQHgskGHNrDKAjqfQxH5A7xKTX6SGpHo2x+KDnNOo4+aBwMiun+A6emk0jhFod60MBSctlbiqYIpYZ1dB23T8WshHkUu1wgqyUaJg6QOPpjyLYz8H4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605750873; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/qzfB+s7WYqw7zSvFxNUiqMLYeqwUfr6/xR1NhWUQMk=; b=fUVkVXEyJyUaH+IXRDAkhsy1AJH0olOAxceqBDcXIOPqZM7r7u1Rlf3v1D08YvpZvWI8oUx33DlRgViHRsn2Bgjk4VtCBg1pEF9bEjsSxOByKcXZ1lr2OWn1eElrLMzDi9aqbfSzjVIYoZ8Mlxu2fGp7MIM6HCb8zgfumhs83Og= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605750873150332.1166301234782; Wed, 18 Nov 2020 17:54:33 -0800 (PST) Received: from localhost ([::1]:42086 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfZ9b-0003kh-NE for importer@patchew.org; Wed, 18 Nov 2020 20:54:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfZ6G-0008I7-Me for qemu-devel@nongnu.org; Wed, 18 Nov 2020 20:51:04 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:2153) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfZ6B-0003NH-3Y for qemu-devel@nongnu.org; Wed, 18 Nov 2020 20:51:04 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4Cc2gn32Xjz6y20; Thu, 19 Nov 2020 09:50:29 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Thu, 19 Nov 2020 09:50:37 +0800 From: Jiahui Cen To: Subject: [PATCH v10 1/9] acpi/gpex: Extract two APIs from acpi_dsdt_add_pci Date: Thu, 19 Nov 2020 09:48:33 +0800 Message-ID: <20201119014841.7298-2-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201119014841.7298-1-cenjiahui@huawei.com> References: <20201119014841.7298-1-cenjiahui@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.35; envelope-from=cenjiahui@huawei.com; helo=szxga07-in.huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/18 20:50:45 X-ACL-Warn: Detected OS = Linux 3.1-3.10 [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Peter Maydell , Jiahui Cen , berrange@redhat.com, Eduardo Habkost , "Michael S. Tsirkin" , Laszlo Ersek , Richard Henderson , Shannon Zhao , miaoyubo@huawei.com, Gerd Hoffmann , Paolo Bonzini , Igor Mammedov , philmd@redhat.com, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Yubo Miao Extract two APIs acpi_dsdt_add_pci_route_table and acpi_dsdt_add_pci_osc from acpi_dsdt_add_pci. The first API is used to specify the pci route table and the second API is used to declare the operation system capabilities. These two APIs would be used to specify the pxb-pcie in DSDT. Signed-off-by: Yubo Miao Signed-off-by: Jiahui Cen --- hw/pci-host/gpex-acpi.c | 112 +++++++++++--------- 1 file changed, 63 insertions(+), 49 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index dbb350a837..32a9f2796d 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -2,21 +2,11 @@ #include "hw/acpi/aml-build.h" #include "hw/pci-host/gpex.h" =20 -void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) +static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq) { - int nr_pcie_buses =3D cfg->ecam.size / PCIE_MMCFG_SIZE_MIN; - Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; + Aml *method, *crs; int i, slot_no; =20 - Aml *dev =3D aml_device("%s", "PCI0"); - aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); - aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); - aml_append(dev, aml_name_decl("_SEG", aml_int(0))); - aml_append(dev, aml_name_decl("_BBN", aml_int(0))); - aml_append(dev, aml_name_decl("_UID", aml_int(0))); - aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); - aml_append(dev, aml_name_decl("_CCA", aml_int(1))); - /* Declare the PCI Routing Table. */ Aml *rt_pkg =3D aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS); for (slot_no =3D 0; slot_no < PCI_SLOT_MAX; slot_no++) { @@ -34,7 +24,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cf= g) =20 /* Create GSI link device */ for (i =3D 0; i < PCI_NUM_PINS; i++) { - uint32_t irqs =3D cfg->irq + i; + uint32_t irqs =3D irq + i; Aml *dev_gsi =3D aml_device("GSI%d", i); aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i))); @@ -52,43 +42,11 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) aml_append(dev_gsi, method); aml_append(dev, dev_gsi); } +} =20 - method =3D aml_method("_CBA", 0, AML_NOTSERIALIZED); - aml_append(method, aml_return(aml_int(cfg->ecam.base))); - aml_append(dev, method); - - Aml *rbuf =3D aml_resource_template(); - aml_append(rbuf, - aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, - nr_pcie_buses)); - if (cfg->mmio32.size) { - aml_append(rbuf, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX= _FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0= 000, - cfg->mmio32.base, - cfg->mmio32.base + cfg->mmio32.size - = 1, - 0x0000, - cfg->mmio32.size)); - } - if (cfg->pio.size) { - aml_append(rbuf, - aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECO= DE, - AML_ENTIRE_RANGE, 0x0000, 0x0000, - cfg->pio.size - 1, - cfg->pio.base, - cfg->pio.size)); - } - if (cfg->mmio64.size) { - aml_append(rbuf, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX= _FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0= 000, - cfg->mmio64.base, - cfg->mmio64.base + cfg->mmio64.size - = 1, - 0x0000, - cfg->mmio64.size)); - } - aml_append(dev, aml_name_decl("_CRS", rbuf)); +static void acpi_dsdt_add_pci_osc(Aml *dev) +{ + Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf; =20 /* Declare an _OSC (OS Control Handoff) method */ aml_append(dev, aml_name_decl("SUPP", aml_int(0))); @@ -160,6 +118,62 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig = *cfg) buf =3D aml_buffer(1, byte_list); aml_append(method, aml_return(buf)); aml_append(dev, method); +} + +void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) +{ + int nr_pcie_buses =3D cfg->ecam.size / PCIE_MMCFG_SIZE_MIN; + Aml *method, *crs, *dev, *rbuf; + + dev =3D aml_device("%s", "PCI0"); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); + aml_append(dev, aml_name_decl("_SEG", aml_int(0))); + aml_append(dev, aml_name_decl("_BBN", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_int(0))); + aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + + acpi_dsdt_add_pci_route_table(dev, cfg->irq); + + method =3D aml_method("_CBA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(cfg->ecam.base))); + aml_append(dev, method); + + rbuf =3D aml_resource_template(); + aml_append(rbuf, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, + nr_pcie_buses)); + if (cfg->mmio32.size) { + aml_append(rbuf, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX= _FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0= 000, + cfg->mmio32.base, + cfg->mmio32.base + cfg->mmio32.size - = 1, + 0x0000, + cfg->mmio32.size)); + } + if (cfg->pio.size) { + aml_append(rbuf, + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECO= DE, + AML_ENTIRE_RANGE, 0x0000, 0x0000, + cfg->pio.size - 1, + cfg->pio.base, + cfg->pio.size)); + } + if (cfg->mmio64.size) { + aml_append(rbuf, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX= _FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0= 000, + cfg->mmio64.base, + cfg->mmio64.base + cfg->mmio64.size - = 1, + 0x0000, + cfg->mmio64.size)); + } + aml_append(dev, aml_name_decl("_CRS", rbuf)); + + acpi_dsdt_add_pci_osc(dev); =20 Aml *dev_res0 =3D aml_device("%s", "RES0"); aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); --=20 2.28.0