From nobody Mon May 6 05:32:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1605750873; cv=none; d=zohomail.com; s=zohoarc; b=bqQWn/OG2xzVv3ODT1aVzZ7NQmUEz/RNb+oRimH+UYrwqMESGM8uCcJ1olQHgskGHNrDKAjqfQxH5A7xKTX6SGpHo2x+KDnNOo4+aBwMiun+A6emk0jhFod60MBSctlbiqYIpYZ1dB23T8WshHkUu1wgqyUaJg6QOPpjyLYz8H4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605750873; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/qzfB+s7WYqw7zSvFxNUiqMLYeqwUfr6/xR1NhWUQMk=; b=fUVkVXEyJyUaH+IXRDAkhsy1AJH0olOAxceqBDcXIOPqZM7r7u1Rlf3v1D08YvpZvWI8oUx33DlRgViHRsn2Bgjk4VtCBg1pEF9bEjsSxOByKcXZ1lr2OWn1eElrLMzDi9aqbfSzjVIYoZ8Mlxu2fGp7MIM6HCb8zgfumhs83Og= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605750873150332.1166301234782; Wed, 18 Nov 2020 17:54:33 -0800 (PST) Received: from localhost ([::1]:42086 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfZ9b-0003kh-NE for importer@patchew.org; Wed, 18 Nov 2020 20:54:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfZ6G-0008I7-Me for qemu-devel@nongnu.org; Wed, 18 Nov 2020 20:51:04 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:2153) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfZ6B-0003NH-3Y for qemu-devel@nongnu.org; Wed, 18 Nov 2020 20:51:04 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4Cc2gn32Xjz6y20; Thu, 19 Nov 2020 09:50:29 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Thu, 19 Nov 2020 09:50:37 +0800 From: Jiahui Cen To: Subject: [PATCH v10 1/9] acpi/gpex: Extract two APIs from acpi_dsdt_add_pci Date: Thu, 19 Nov 2020 09:48:33 +0800 Message-ID: <20201119014841.7298-2-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201119014841.7298-1-cenjiahui@huawei.com> References: <20201119014841.7298-1-cenjiahui@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.35; envelope-from=cenjiahui@huawei.com; helo=szxga07-in.huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/18 20:50:45 X-ACL-Warn: Detected OS = Linux 3.1-3.10 [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Peter Maydell , Jiahui Cen , berrange@redhat.com, Eduardo Habkost , "Michael S. Tsirkin" , Laszlo Ersek , Richard Henderson , Shannon Zhao , miaoyubo@huawei.com, Gerd Hoffmann , Paolo Bonzini , Igor Mammedov , philmd@redhat.com, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Yubo Miao Extract two APIs acpi_dsdt_add_pci_route_table and acpi_dsdt_add_pci_osc from acpi_dsdt_add_pci. The first API is used to specify the pci route table and the second API is used to declare the operation system capabilities. These two APIs would be used to specify the pxb-pcie in DSDT. Signed-off-by: Yubo Miao Signed-off-by: Jiahui Cen --- hw/pci-host/gpex-acpi.c | 112 +++++++++++--------- 1 file changed, 63 insertions(+), 49 deletions(-) diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index dbb350a837..32a9f2796d 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -2,21 +2,11 @@ #include "hw/acpi/aml-build.h" #include "hw/pci-host/gpex.h" =20 -void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) +static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq) { - int nr_pcie_buses =3D cfg->ecam.size / PCIE_MMCFG_SIZE_MIN; - Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; + Aml *method, *crs; int i, slot_no; =20 - Aml *dev =3D aml_device("%s", "PCI0"); - aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); - aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); - aml_append(dev, aml_name_decl("_SEG", aml_int(0))); - aml_append(dev, aml_name_decl("_BBN", aml_int(0))); - aml_append(dev, aml_name_decl("_UID", aml_int(0))); - aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); - aml_append(dev, aml_name_decl("_CCA", aml_int(1))); - /* Declare the PCI Routing Table. */ Aml *rt_pkg =3D aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS); for (slot_no =3D 0; slot_no < PCI_SLOT_MAX; slot_no++) { @@ -34,7 +24,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cf= g) =20 /* Create GSI link device */ for (i =3D 0; i < PCI_NUM_PINS; i++) { - uint32_t irqs =3D cfg->irq + i; + uint32_t irqs =3D irq + i; Aml *dev_gsi =3D aml_device("GSI%d", i); aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i))); @@ -52,43 +42,11 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *= cfg) aml_append(dev_gsi, method); aml_append(dev, dev_gsi); } +} =20 - method =3D aml_method("_CBA", 0, AML_NOTSERIALIZED); - aml_append(method, aml_return(aml_int(cfg->ecam.base))); - aml_append(dev, method); - - Aml *rbuf =3D aml_resource_template(); - aml_append(rbuf, - aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, - nr_pcie_buses)); - if (cfg->mmio32.size) { - aml_append(rbuf, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX= _FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0= 000, - cfg->mmio32.base, - cfg->mmio32.base + cfg->mmio32.size - = 1, - 0x0000, - cfg->mmio32.size)); - } - if (cfg->pio.size) { - aml_append(rbuf, - aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECO= DE, - AML_ENTIRE_RANGE, 0x0000, 0x0000, - cfg->pio.size - 1, - cfg->pio.base, - cfg->pio.size)); - } - if (cfg->mmio64.size) { - aml_append(rbuf, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX= _FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0= 000, - cfg->mmio64.base, - cfg->mmio64.base + cfg->mmio64.size - = 1, - 0x0000, - cfg->mmio64.size)); - } - aml_append(dev, aml_name_decl("_CRS", rbuf)); +static void acpi_dsdt_add_pci_osc(Aml *dev) +{ + Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf; =20 /* Declare an _OSC (OS Control Handoff) method */ aml_append(dev, aml_name_decl("SUPP", aml_int(0))); @@ -160,6 +118,62 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig = *cfg) buf =3D aml_buffer(1, byte_list); aml_append(method, aml_return(buf)); aml_append(dev, method); +} + +void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) +{ + int nr_pcie_buses =3D cfg->ecam.size / PCIE_MMCFG_SIZE_MIN; + Aml *method, *crs, *dev, *rbuf; + + dev =3D aml_device("%s", "PCI0"); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); + aml_append(dev, aml_name_decl("_SEG", aml_int(0))); + aml_append(dev, aml_name_decl("_BBN", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_int(0))); + aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + + acpi_dsdt_add_pci_route_table(dev, cfg->irq); + + method =3D aml_method("_CBA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(cfg->ecam.base))); + aml_append(dev, method); + + rbuf =3D aml_resource_template(); + aml_append(rbuf, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, + nr_pcie_buses)); + if (cfg->mmio32.size) { + aml_append(rbuf, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX= _FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0= 000, + cfg->mmio32.base, + cfg->mmio32.base + cfg->mmio32.size - = 1, + 0x0000, + cfg->mmio32.size)); + } + if (cfg->pio.size) { + aml_append(rbuf, + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECO= DE, + AML_ENTIRE_RANGE, 0x0000, 0x0000, + cfg->pio.size - 1, + cfg->pio.base, + cfg->pio.size)); + } + if (cfg->mmio64.size) { + aml_append(rbuf, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX= _FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0= 000, + cfg->mmio64.base, + cfg->mmio64.base + cfg->mmio64.size - = 1, + 0x0000, + cfg->mmio64.size)); + } + aml_append(dev, aml_name_decl("_CRS", rbuf)); + + acpi_dsdt_add_pci_osc(dev); =20 Aml *dev_res0 =3D aml_device("%s", "RES0"); aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); --=20 2.28.0 From nobody Mon May 6 05:32:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1605751121; cv=none; d=zohomail.com; s=zohoarc; b=NcKK1mLuGykoK3AVeDxMLEupy1sEIu7XCwAKk/CIxpYqmq+xbtcUpXHtYYoPL7Y4Lnp3DIpCqM2DrSyNK6/Cv8hWqWKpOhUuOzVo66pod252OSGYRKOMEphZvp1JXqn7/VgeBza/yJZI10XI0eApzdZRzQl0bYpSgGITvu3r5qA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605751121; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=K3dl5WEmiNKQl7egHBJen0L9xbZl+q3MSD+sHJ9z6qI=; b=Z4NuaNH0hXmkhmEYc3i8IhAoXBwDZzqO7n8jH1Xqu9GhYhHdEfAWSO+i4q0r6cQaIDk3iOO/y+rN3zoStpLCBWCd7CIOuSI70gpojgcqdAh8liy7lfMWbrCHnYbkP4JW4++H1Nzs+nx3PlCh9NsXiZYFnKmW8Zqk80QBh4QRE2Y= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605751121979964.2222330920214; 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Thu, 19 Nov 2020 09:50:37 +0800 From: Jiahui Cen To: Subject: [PATCH v10 2/9] fw_cfg: Refactor extra pci roots addition Date: Thu, 19 Nov 2020 09:48:34 +0800 Message-ID: <20201119014841.7298-3-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201119014841.7298-1-cenjiahui@huawei.com> References: <20201119014841.7298-1-cenjiahui@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=cenjiahui@huawei.com; helo=szxga06-in.huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/18 20:50:45 X-ACL-Warn: Detected OS = Linux 3.1-3.10 [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Peter Maydell , Jiahui Cen , berrange@redhat.com, Eduardo Habkost , "Michael S. Tsirkin" , Laszlo Ersek , Richard Henderson , Shannon Zhao , miaoyubo@huawei.com, Gerd Hoffmann , Paolo Bonzini , Igor Mammedov , philmd@redhat.com, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Extract extra pci roots addition from pc machine, which could be used by other machines. In order to make uefi get the extra roots, it is necessary to write extra roots into fw_cfg. And only if the uefi knows there are extra roots, the config spaces of devices behind the root could be obtained. Signed-off-by: Jiahui Cen Signed-off-by: Yubo Miao --- hw/i386/pc.c | 18 +-------------- hw/nvram/fw_cfg.c | 23 ++++++++++++++++++++ include/hw/nvram/fw_cfg.h | 9 ++++++++ 3 files changed, 33 insertions(+), 17 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 17b514d1da..76a846ff9a 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -777,27 +777,11 @@ void pc_machine_done(Notifier *notifier, void *data) PCMachineState *pcms =3D container_of(notifier, PCMachineState, machine_done); X86MachineState *x86ms =3D X86_MACHINE(pcms); - PCIBus *bus =3D pcms->bus; =20 /* set the number of CPUs */ x86_rtc_set_cpus_count(x86ms->rtc, x86ms->boot_cpus); =20 - if (bus) { - int extra_hosts =3D 0; - - QLIST_FOREACH(bus, &bus->child, sibling) { - /* look for expander root buses */ - if (pci_bus_is_root(bus)) { - extra_hosts++; - } - } - if (extra_hosts && x86ms->fw_cfg) { - uint64_t *val =3D g_malloc(sizeof(*val)); - *val =3D cpu_to_le64(extra_hosts); - fw_cfg_add_file(x86ms->fw_cfg, - "etc/extra-pci-roots", val, sizeof(*val)); - } - } + fw_cfg_add_extra_pci_roots(pcms->bus, x86ms->fw_cfg); =20 acpi_setup(); if (x86ms->fw_cfg) { diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 08539a1aab..282ba93e2e 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -40,6 +40,7 @@ #include "qemu/cutils.h" #include "qapi/error.h" #include "hw/acpi/aml-build.h" +#include "hw/pci/pci_bus.h" =20 #define FW_CFG_FILE_SLOTS_DFLT 0x20 =20 @@ -1061,6 +1062,28 @@ bool fw_cfg_add_from_generator(FWCfgState *s, const = char *filename, return true; } =20 +void fw_cfg_add_extra_pci_roots(PCIBus *bus, FWCfgState *s) +{ + int extra_hosts =3D 0; + + if (!bus) { + return; + } + + QLIST_FOREACH(bus, &bus->child, sibling) { + /* look for expander root buses */ + if (pci_bus_is_root(bus)) { + extra_hosts++; + } + } + + if (extra_hosts && s) { + uint64_t *val =3D g_malloc(sizeof(*val)); + *val =3D cpu_to_le64(extra_hosts); + fw_cfg_add_file(s, "etc/extra-pci-roots", val, sizeof(*val)); + } +} + static void fw_cfg_machine_reset(void *opaque) { MachineClass *mc =3D MACHINE_GET_CLASS(qdev_get_machine()); diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h index 8a9f5738bf..0e7a8bc7af 100644 --- a/include/hw/nvram/fw_cfg.h +++ b/include/hw/nvram/fw_cfg.h @@ -308,6 +308,15 @@ void *fw_cfg_modify_file(FWCfgState *s, const char *fi= lename, void *data, bool fw_cfg_add_from_generator(FWCfgState *s, const char *filename, const char *gen_id, Error **errp); =20 +/** + * fw_cfg_add_extra_pci_roots: + * @bus: main pci root bus to be scanned from + * @s: fw_cfg device being modified + * + * Add a new fw_cfg item... + */ +void fw_cfg_add_extra_pci_roots(PCIBus *bus, FWCfgState *s); + FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, AddressSpace *dma_as); FWCfgState *fw_cfg_init_io(uint32_t iobase); --=20 2.28.0 From nobody Mon May 6 05:32:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 19 Nov 2020 09:50:38 +0800 From: Jiahui Cen To: Subject: [PATCH v10 3/9] hw/arm/virt: Write extra pci roots into fw_cfg Date: Thu, 19 Nov 2020 09:48:35 +0800 Message-ID: <20201119014841.7298-4-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201119014841.7298-1-cenjiahui@huawei.com> References: <20201119014841.7298-1-cenjiahui@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.35; envelope-from=cenjiahui@huawei.com; helo=szxga07-in.huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/18 20:50:45 X-ACL-Warn: Detected OS = Linux 3.1-3.10 [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Peter Maydell , Jiahui Cen , berrange@redhat.com, Eduardo Habkost , "Michael S. Tsirkin" , Laszlo Ersek , Richard Henderson , Shannon Zhao , miaoyubo@huawei.com, Gerd Hoffmann , Paolo Bonzini , Igor Mammedov , philmd@redhat.com, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Add bus property to virt machine for primary PCI root bus and use it to add extra pci roots behind it. Signed-off-by: Jiahui Cen Signed-off-by: Yubo Miao --- hw/arm/virt.c | 7 +++++-- include/hw/arm/virt.h | 1 + 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 27dbeb549e..847257aa5c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1289,7 +1289,8 @@ static void create_pcie(VirtMachineState *vms) } =20 pci =3D PCI_HOST_BRIDGE(dev); - if (pci->bus) { + vms->bus =3D pci->bus; + if (vms->bus) { for (i =3D 0; i < nb_nics; i++) { NICInfo *nd =3D &nd_table[i]; =20 @@ -1346,7 +1347,7 @@ static void create_pcie(VirtMachineState *vms) =20 switch (vms->iommu) { case VIRT_IOMMU_SMMUV3: - create_smmu(vms, pci->bus); + create_smmu(vms, vms->bus); qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", 0x0, vms->iommu_phandle, 0x0, 0x10000); break; @@ -1481,6 +1482,8 @@ void virt_machine_done(Notifier *notifier, void *data) exit(1); } =20 + fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg); + virt_acpi_setup(vms); virt_build_smbios(vms); } diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index aad6d69841..abf54fab49 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -163,6 +163,7 @@ struct VirtMachineState { DeviceState *gic; DeviceState *acpi_dev; Notifier powerdown_notifier; + PCIBus *bus; }; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) --=20 2.28.0 From nobody Mon May 6 05:32:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1605751001; cv=none; d=zohomail.com; s=zohoarc; b=MmOES3MSaOo3topMQPY735SbYy6EKHLJ5SIIfea43YJHb2UlYgM3ZlWgtWjXBnkd6TZQTRFzDX/bJMgQf2dRZYHm4x0LlJF4XkGrr73yKAwAxXZbLR8t7/1obCfzTbqCHwFYWjHK9XXj7HIs5sRqnqfrbTyzmgQ5sg6zHWtLtmI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605751001; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7/J6X9eElC7Snf20DEB8il27PGWcSaMK1F9TWp3xMxk=; b=i9EPuPxF6+60Ls/FfAmxCp3pT9Ix21UpbwH+FXPbJk1y+IRQMKBYS61gxGEACo+2nYcmQgCDL2DSBvvO/81aH6ac50jQP2SGWh0WRv7ZJgLTs+DlS3VEpSMFiZB0mGSUwkQtMpKb/ViWh8PZI9pxcEZ/nLVUBEak4ro0ls7TyJY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605751001499534.720035649569; Wed, 18 Nov 2020 17:56:41 -0800 (PST) Received: from localhost ([::1]:46884 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfZBg-0005mC-Dr for importer@patchew.org; Wed, 18 Nov 2020 20:56:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45600) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfZ6G-0008HM-Bg for qemu-devel@nongnu.org; Wed, 18 Nov 2020 20:51:04 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2528) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfZ6B-0003NR-23 for qemu-devel@nongnu.org; Wed, 18 Nov 2020 20:51:04 -0500 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4Cc2gs201PzhZ5f; Thu, 19 Nov 2020 09:50:33 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 19 Nov 2020 09:50:38 +0800 From: Jiahui Cen To: Subject: [PATCH v10 4/9] acpi: Extract crs build form acpi_build.c Date: Thu, 19 Nov 2020 09:48:36 +0800 Message-ID: <20201119014841.7298-5-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201119014841.7298-1-cenjiahui@huawei.com> References: <20201119014841.7298-1-cenjiahui@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=cenjiahui@huawei.com; helo=szxga05-in.huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/18 20:50:48 X-ACL-Warn: Detected OS = Linux 3.1-3.10 [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Peter Maydell , Jiahui Cen , berrange@redhat.com, Eduardo Habkost , "Michael S. Tsirkin" , Laszlo Ersek , Richard Henderson , Shannon Zhao , miaoyubo@huawei.com, Gerd Hoffmann , Paolo Bonzini , Igor Mammedov , philmd@redhat.com, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Yubo Miao Extract crs build form acpi_build.c, the function could also be used to build the crs for pxbs for arm. The resources are composed by two parts: 1. The bar space of pci-bridge/pcie-root-ports 2. The resources needed by devices behind PXBs. The base and limit of memory/io are obtained from the config via two APIs: pci_bridge_get_base and pci_bridge_get_limit Signed-off-by: Yubo Miao Signed-off-by: Jiahui Cen --- hw/acpi/aml-build.c | 285 +++++++++++++++++++ hw/i386/acpi-build.c | 293 -------------------- include/hw/acpi/aml-build.h | 22 ++ 3 files changed, 307 insertions(+), 293 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 3792ba96ce..f976aa667b 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -27,6 +27,9 @@ #include "sysemu/numa.h" #include "hw/boards.h" #include "hw/acpi/tpm.h" +#include "hw/pci/pci_host.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci/pci_bridge.h" =20 static GArray *build_alloc_array(void) { @@ -55,6 +58,128 @@ static void build_append_array(GArray *array, GArray *v= al) =20 #define ACPI_NAMESEG_LEN 4 =20 +void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) +{ + CrsRangeEntry *entry; + + entry =3D g_malloc(sizeof(*entry)); + entry->base =3D base; + entry->limit =3D limit; + + g_ptr_array_add(ranges, entry); +} + +static void crs_range_free(gpointer data) +{ + CrsRangeEntry *entry =3D (CrsRangeEntry *)data; + g_free(entry); +} + +void crs_range_set_init(CrsRangeSet *range_set) +{ + range_set->io_ranges =3D g_ptr_array_new_with_free_func(crs_range_free= ); + range_set->mem_ranges =3D g_ptr_array_new_with_free_func(crs_range_fre= e); + range_set->mem_64bit_ranges =3D + g_ptr_array_new_with_free_func(crs_range_free); +} + +void crs_range_set_free(CrsRangeSet *range_set) +{ + g_ptr_array_free(range_set->io_ranges, true); + g_ptr_array_free(range_set->mem_ranges, true); + g_ptr_array_free(range_set->mem_64bit_ranges, true); +} + +static gint crs_range_compare(gconstpointer a, gconstpointer b) +{ + CrsRangeEntry *entry_a =3D *(CrsRangeEntry **)a; + CrsRangeEntry *entry_b =3D *(CrsRangeEntry **)b; + + if (entry_a->base < entry_b->base) { + return -1; + } else if (entry_a->base > entry_b->base) { + return 1; + } else { + return 0; + } +} + +/* + * crs_replace_with_free_ranges - given the 'used' ranges within [start - = end] + * interval, computes the 'free' ranges from the same interval. + * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function + * will return { [base - a1], [a2 - b1], [b2 - limit] }. + */ +void crs_replace_with_free_ranges(GPtrArray *ranges, + uint64_t start, uint64_t end) +{ + GPtrArray *free_ranges =3D g_ptr_array_new(); + uint64_t free_base =3D start; + int i; + + g_ptr_array_sort(ranges, crs_range_compare); + for (i =3D 0; i < ranges->len; i++) { + CrsRangeEntry *used =3D g_ptr_array_index(ranges, i); + + if (free_base < used->base) { + crs_range_insert(free_ranges, free_base, used->base - 1); + } + + free_base =3D used->limit + 1; + } + + if (free_base < end) { + crs_range_insert(free_ranges, free_base, end); + } + + g_ptr_array_set_size(ranges, 0); + for (i =3D 0; i < free_ranges->len; i++) { + g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); + } + + g_ptr_array_free(free_ranges, true); +} + +/* + * crs_range_merge - merges adjacent ranges in the given array. + * Array elements are deleted and replaced with the merged ranges. + */ +static void crs_range_merge(GPtrArray *range) +{ + GPtrArray *tmp =3D g_ptr_array_new_with_free_func(crs_range_free); + CrsRangeEntry *entry; + uint64_t range_base, range_limit; + int i; + + if (!range->len) { + return; + } + + g_ptr_array_sort(range, crs_range_compare); + + entry =3D g_ptr_array_index(range, 0); + range_base =3D entry->base; + range_limit =3D entry->limit; + for (i =3D 1; i < range->len; i++) { + entry =3D g_ptr_array_index(range, i); + if (entry->base - 1 =3D=3D range_limit) { + range_limit =3D entry->limit; + } else { + crs_range_insert(tmp, range_base, range_limit); + range_base =3D entry->base; + range_limit =3D entry->limit; + } + } + crs_range_insert(tmp, range_base, range_limit); + + g_ptr_array_set_size(range, 0); + for (i =3D 0; i < tmp->len; i++) { + entry =3D g_ptr_array_index(tmp, i); + crs_range_insert(range, entry->base, entry->limit); + } + g_ptr_array_free(tmp, true); +} + static void build_append_nameseg(GArray *array, const char *seg) { @@ -1951,6 +2076,166 @@ void build_tpm2(GArray *table_data, BIOSLinker *lin= ker, GArray *tcpalog) tpm2_ptr, "TPM2", table_data->len - tpm2_start, 4, NULL, = NULL); } =20 +Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) +{ + Aml *crs =3D aml_resource_template(); + CrsRangeSet temp_range_set; + CrsRangeEntry *entry; + uint8_t max_bus =3D pci_bus_num(host->bus); + uint8_t type; + int devfn; + int i; + + crs_range_set_init(&temp_range_set); + for (devfn =3D 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { + uint64_t range_base, range_limit; + PCIDevice *dev =3D host->bus->devices[devfn]; + + if (!dev) { + continue; + } + + for (i =3D 0; i < PCI_NUM_REGIONS; i++) { + PCIIORegion *r =3D &dev->io_regions[i]; + + range_base =3D r->addr; + range_limit =3D r->addr + r->size - 1; + + /* + * Work-around for old bioses + * that do not support multiple root buses + */ + if (!range_base || range_base > range_limit) { + continue; + } + + if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { + crs_range_insert(temp_range_set.io_ranges, + range_base, range_limit); + } else { /* "memory" */ + uint64_t length =3D range_limit - range_base + 1; + if (range_limit <=3D UINT32_MAX && length <=3D UINT32_MAX)= { + crs_range_insert(temp_range_set.mem_ranges, range_base, + range_limit); + } else { + crs_range_insert(temp_range_set.mem_64bit_ranges, + range_base, range_limit); + } + } + } + + type =3D dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUN= CTION; + if (type =3D=3D PCI_HEADER_TYPE_BRIDGE) { + uint8_t subordinate =3D dev->config[PCI_SUBORDINATE_BUS]; + if (subordinate > max_bus) { + max_bus =3D subordinate; + } + + range_base =3D pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE= _IO); + range_limit =3D pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPA= CE_IO); + + /* + * Work-around for old bioses + * that do not support multiple root buses + */ + if (range_base && range_base <=3D range_limit) { + crs_range_insert(temp_range_set.io_ranges, + range_base, range_limit); + } + + range_base =3D + pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); + range_limit =3D + pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); + + /* + * Work-around for old bioses + * that do not support multiple root buses + */ + if (range_base && range_base <=3D range_limit) { + uint64_t length =3D range_limit - range_base + 1; + if (range_limit <=3D UINT32_MAX && length <=3D UINT32_MAX)= { + crs_range_insert(temp_range_set.mem_ranges, + range_base, range_limit); + } else { + crs_range_insert(temp_range_set.mem_64bit_ranges, + range_base, range_limit); + } + } + + range_base =3D + pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); + range_limit =3D + pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); + + /* + * Work-around for old bioses + * that do not support multiple root buses + */ + if (range_base && range_base <=3D range_limit) { + uint64_t length =3D range_limit - range_base + 1; + if (range_limit <=3D UINT32_MAX && length <=3D UINT32_MAX)= { + crs_range_insert(temp_range_set.mem_ranges, + range_base, range_limit); + } else { + crs_range_insert(temp_range_set.mem_64bit_ranges, + range_base, range_limit); + } + } + } + } + + crs_range_merge(temp_range_set.io_ranges); + for (i =3D 0; i < temp_range_set.io_ranges->len; i++) { + entry =3D g_ptr_array_index(temp_range_set.io_ranges, i); + aml_append(crs, + aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, + 0, entry->base, entry->limit, 0, + entry->limit - entry->base + 1)); + crs_range_insert(range_set->io_ranges, entry->base, entry->limit); + } + + crs_range_merge(temp_range_set.mem_ranges); + for (i =3D 0; i < temp_range_set.mem_ranges->len; i++) { + entry =3D g_ptr_array_index(temp_range_set.mem_ranges, i); + assert(entry->limit <=3D UINT32_MAX && + (entry->limit - entry->base + 1) <=3D UINT32_MAX); + aml_append(crs, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, AML_NON_CACHEABLE, + AML_READ_WRITE, + 0, entry->base, entry->limit, 0, + entry->limit - entry->base + 1)); + crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); + } + + crs_range_merge(temp_range_set.mem_64bit_ranges); + for (i =3D 0; i < temp_range_set.mem_64bit_ranges->len; i++) { + entry =3D g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); + aml_append(crs, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, AML_NON_CACHEABLE, + AML_READ_WRITE, + 0, entry->base, entry->limit, 0, + entry->limit - entry->base + 1)); + crs_range_insert(range_set->mem_64bit_ranges, + entry->base, entry->limit); + } + + crs_range_set_free(&temp_range_set); + + aml_append(crs, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + 0, + pci_bus_num(host->bus), + max_bus, + 0, + max_bus - pci_bus_num(host->bus) + 1)); + + return crs; +} + /* ACPI 5.0: 6.4.3.8.2 Serial Bus Connection Descriptors */ static Aml *aml_serial_bus_device(uint8_t serial_bus_type, uint8_t flags, uint16_t type_flags, diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 1f5c211245..76e27f8fad 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -613,299 +613,6 @@ static Aml *build_prt(bool is_pci0_prt) return method; } =20 -typedef struct CrsRangeEntry { - uint64_t base; - uint64_t limit; -} CrsRangeEntry; - -static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t li= mit) -{ - CrsRangeEntry *entry; - - entry =3D g_malloc(sizeof(*entry)); - entry->base =3D base; - entry->limit =3D limit; - - g_ptr_array_add(ranges, entry); -} - -static void crs_range_free(gpointer data) -{ - CrsRangeEntry *entry =3D (CrsRangeEntry *)data; - g_free(entry); -} - -typedef struct CrsRangeSet { - GPtrArray *io_ranges; - GPtrArray *mem_ranges; - GPtrArray *mem_64bit_ranges; - } CrsRangeSet; - -static void crs_range_set_init(CrsRangeSet *range_set) -{ - range_set->io_ranges =3D g_ptr_array_new_with_free_func(crs_range_free= ); - range_set->mem_ranges =3D g_ptr_array_new_with_free_func(crs_range_fre= e); - range_set->mem_64bit_ranges =3D - g_ptr_array_new_with_free_func(crs_range_free); -} - -static void crs_range_set_free(CrsRangeSet *range_set) -{ - g_ptr_array_free(range_set->io_ranges, true); - g_ptr_array_free(range_set->mem_ranges, true); - g_ptr_array_free(range_set->mem_64bit_ranges, true); -} - -static gint crs_range_compare(gconstpointer a, gconstpointer b) -{ - CrsRangeEntry *entry_a =3D *(CrsRangeEntry **)a; - CrsRangeEntry *entry_b =3D *(CrsRangeEntry **)b; - - if (entry_a->base < entry_b->base) { - return -1; - } else if (entry_a->base > entry_b->base) { - return 1; - } else { - return 0; - } -} - -/* - * crs_replace_with_free_ranges - given the 'used' ranges within [start - = end] - * interval, computes the 'free' ranges from the same interval. - * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function - * will return { [base - a1], [a2 - b1], [b2 - limit] }. - */ -static void crs_replace_with_free_ranges(GPtrArray *ranges, - uint64_t start, uint64_t end) -{ - GPtrArray *free_ranges =3D g_ptr_array_new(); - uint64_t free_base =3D start; - int i; - - g_ptr_array_sort(ranges, crs_range_compare); - for (i =3D 0; i < ranges->len; i++) { - CrsRangeEntry *used =3D g_ptr_array_index(ranges, i); - - if (free_base < used->base) { - crs_range_insert(free_ranges, free_base, used->base - 1); - } - - free_base =3D used->limit + 1; - } - - if (free_base < end) { - crs_range_insert(free_ranges, free_base, end); - } - - g_ptr_array_set_size(ranges, 0); - for (i =3D 0; i < free_ranges->len; i++) { - g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); - } - - g_ptr_array_free(free_ranges, true); -} - -/* - * crs_range_merge - merges adjacent ranges in the given array. - * Array elements are deleted and replaced with the merged ranges. - */ -static void crs_range_merge(GPtrArray *range) -{ - GPtrArray *tmp =3D g_ptr_array_new_with_free_func(crs_range_free); - CrsRangeEntry *entry; - uint64_t range_base, range_limit; - int i; - - if (!range->len) { - return; - } - - g_ptr_array_sort(range, crs_range_compare); - - entry =3D g_ptr_array_index(range, 0); - range_base =3D entry->base; - range_limit =3D entry->limit; - for (i =3D 1; i < range->len; i++) { - entry =3D g_ptr_array_index(range, i); - if (entry->base - 1 =3D=3D range_limit) { - range_limit =3D entry->limit; - } else { - crs_range_insert(tmp, range_base, range_limit); - range_base =3D entry->base; - range_limit =3D entry->limit; - } - } - crs_range_insert(tmp, range_base, range_limit); - - g_ptr_array_set_size(range, 0); - for (i =3D 0; i < tmp->len; i++) { - entry =3D g_ptr_array_index(tmp, i); - crs_range_insert(range, entry->base, entry->limit); - } - g_ptr_array_free(tmp, true); -} - -static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) -{ - Aml *crs =3D aml_resource_template(); - CrsRangeSet temp_range_set; - CrsRangeEntry *entry; - uint8_t max_bus =3D pci_bus_num(host->bus); - uint8_t type; - int devfn; - int i; - - crs_range_set_init(&temp_range_set); - for (devfn =3D 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { - uint64_t range_base, range_limit; - PCIDevice *dev =3D host->bus->devices[devfn]; - - if (!dev) { - continue; - } - - for (i =3D 0; i < PCI_NUM_REGIONS; i++) { - PCIIORegion *r =3D &dev->io_regions[i]; - - range_base =3D r->addr; - range_limit =3D r->addr + r->size - 1; - - /* - * Work-around for old bioses - * that do not support multiple root buses - */ - if (!range_base || range_base > range_limit) { - continue; - } - - if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { - crs_range_insert(temp_range_set.io_ranges, - range_base, range_limit); - } else { /* "memory" */ - uint64_t length =3D range_limit - range_base + 1; - if (range_limit <=3D UINT32_MAX && length <=3D UINT32_MAX)= { - crs_range_insert(temp_range_set.mem_ranges, range_base, - range_limit); - } else { - crs_range_insert(temp_range_set.mem_64bit_ranges, - range_base, range_limit); - } - } - } - - type =3D dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUN= CTION; - if (type =3D=3D PCI_HEADER_TYPE_BRIDGE) { - uint8_t subordinate =3D dev->config[PCI_SUBORDINATE_BUS]; - if (subordinate > max_bus) { - max_bus =3D subordinate; - } - - range_base =3D pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE= _IO); - range_limit =3D pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPA= CE_IO); - - /* - * Work-around for old bioses - * that do not support multiple root buses - */ - if (range_base && range_base <=3D range_limit) { - crs_range_insert(temp_range_set.io_ranges, - range_base, range_limit); - } - - range_base =3D - pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); - range_limit =3D - pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); - - /* - * Work-around for old bioses - * that do not support multiple root buses - */ - if (range_base && range_base <=3D range_limit) { - uint64_t length =3D range_limit - range_base + 1; - if (range_limit <=3D UINT32_MAX && length <=3D UINT32_MAX)= { - crs_range_insert(temp_range_set.mem_ranges, - range_base, range_limit); - } else { - crs_range_insert(temp_range_set.mem_64bit_ranges, - range_base, range_limit); - } - } - - range_base =3D - pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); - range_limit =3D - pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); - - /* - * Work-around for old bioses - * that do not support multiple root buses - */ - if (range_base && range_base <=3D range_limit) { - uint64_t length =3D range_limit - range_base + 1; - if (range_limit <=3D UINT32_MAX && length <=3D UINT32_MAX)= { - crs_range_insert(temp_range_set.mem_ranges, - range_base, range_limit); - } else { - crs_range_insert(temp_range_set.mem_64bit_ranges, - range_base, range_limit); - } - } - } - } - - crs_range_merge(temp_range_set.io_ranges); - for (i =3D 0; i < temp_range_set.io_ranges->len; i++) { - entry =3D g_ptr_array_index(temp_range_set.io_ranges, i); - aml_append(crs, - aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, - AML_POS_DECODE, AML_ENTIRE_RANGE, - 0, entry->base, entry->limit, 0, - entry->limit - entry->base + 1)); - crs_range_insert(range_set->io_ranges, entry->base, entry->limit); - } - - crs_range_merge(temp_range_set.mem_ranges); - for (i =3D 0; i < temp_range_set.mem_ranges->len; i++) { - entry =3D g_ptr_array_index(temp_range_set.mem_ranges, i); - assert(entry->limit <=3D UINT32_MAX && - (entry->limit - entry->base + 1) <=3D UINT32_MAX); - aml_append(crs, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, - AML_MAX_FIXED, AML_NON_CACHEABLE, - AML_READ_WRITE, - 0, entry->base, entry->limit, 0, - entry->limit - entry->base + 1)); - crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); - } - - crs_range_merge(temp_range_set.mem_64bit_ranges); - for (i =3D 0; i < temp_range_set.mem_64bit_ranges->len; i++) { - entry =3D g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); - aml_append(crs, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, - AML_MAX_FIXED, AML_NON_CACHEABLE, - AML_READ_WRITE, - 0, entry->base, entry->limit, 0, - entry->limit - entry->base + 1)); - crs_range_insert(range_set->mem_64bit_ranges, - entry->base, entry->limit); - } - - crs_range_set_free(&temp_range_set); - - aml_append(crs, - aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - 0, - pci_bus_num(host->bus), - max_bus, - 0, - max_bus - pci_bus_num(host->bus) + 1)); - - return crs; -} - static void build_hpet_aml(Aml *table) { Aml *crs; diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index fe0055fffb..e727bea1bc 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -224,6 +224,20 @@ struct AcpiBuildTables { BIOSLinker *linker; } AcpiBuildTables; =20 +typedef +struct CrsRangeEntry { + uint64_t base; + uint64_t limit; +} CrsRangeEntry; + +typedef +struct CrsRangeSet { + GPtrArray *io_ranges; + GPtrArray *mem_ranges; + GPtrArray *mem_64bit_ranges; +} CrsRangeSet; + + /* * ACPI 5.0: 6.4.3.8.2 Serial Bus Connection Descriptors * Serial Bus Type @@ -432,6 +446,14 @@ build_append_gas_from_struct(GArray *table, const stru= ct AcpiGenericAddress *s) s->access_width, s->address); } =20 +void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit); +void crs_replace_with_free_ranges(GPtrArray *ranges, + uint64_t start, uint64_t end); +void crs_range_set_init(CrsRangeSet *range_set); +void crs_range_set_free(CrsRangeSet *range_set); + +Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set); + void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, uint64_t len, int node, MemoryAffinityFlags flags); =20 --=20 2.28.0 From nobody Mon May 6 05:32:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1605750788; cv=none; d=zohomail.com; s=zohoarc; b=YLOYT7pW8diFqlJxONMoo/E5QUlPHK7hypKBV3Cu/scrPBKyujPgNDr38tEKYtwVIoFY/uiyWj9OoAjWpcrNi+AGrp+18InxV2MCDaW7HiwElrVEw5MDBaHMUqBIGQDT0uPKvb4/3lU3jJOdvb6ie3hf15+FF+7lsctaLo4KcbA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605750788; 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Wed, 18 Nov 2020 20:51:04 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2860) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfZ6B-0003NW-2j for qemu-devel@nongnu.org; Wed, 18 Nov 2020 20:51:03 -0500 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4Cc2gs6hPsz15MsD; Thu, 19 Nov 2020 09:50:33 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.487.0; Thu, 19 Nov 2020 09:50:39 +0800 From: Jiahui Cen To: Subject: [PATCH v10 5/9] acpi/gpex: Build tables for pxb Date: Thu, 19 Nov 2020 09:48:37 +0800 Message-ID: <20201119014841.7298-6-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201119014841.7298-1-cenjiahui@huawei.com> References: <20201119014841.7298-1-cenjiahui@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=cenjiahui@huawei.com; helo=szxga04-in.huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/18 20:50:47 X-ACL-Warn: Detected OS = Linux 3.1-3.10 [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Peter Maydell , Jiahui Cen , berrange@redhat.com, Eduardo Habkost , "Michael S. Tsirkin" , Laszlo Ersek , Richard Henderson , Shannon Zhao , miaoyubo@huawei.com, Gerd Hoffmann , Paolo Bonzini , Igor Mammedov , philmd@redhat.com, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Yubo Miao The resources of pxbs are obtained by crs_build and the resources used by pxbs would be moved from the resources defined for host-bridge. The resources for pxb are composed of following two parts: 1. The bar space of the pci-bridge/pcie-root-port behined it 2. The config space of devices behind it. Signed-off-by: Yubo Miao Signed-off-by: Jiahui Cen --- hw/arm/virt-acpi-build.c | 6 ++- hw/pci-host/gpex-acpi.c | 54 ++++++++++++++++++++ include/hw/pci-host/gpex.h | 1 + 3 files changed, 59 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9747a6458f..e0bed9037c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -153,7 +153,8 @@ static void acpi_dsdt_add_virtio(Aml *scope, } =20 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, - uint32_t irq, bool use_highmem, bool highmem= _ecam) + uint32_t irq, bool use_highmem, bool highmem= _ecam, + VirtMachineState *vms) { int ecam_id =3D VIRT_ECAM_ID(highmem_ecam); struct GPEXConfig cfg =3D { @@ -161,6 +162,7 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapE= ntry *memmap, .pio =3D memmap[VIRT_PCIE_PIO], .ecam =3D memmap[ecam_id], .irq =3D irq, + .bus =3D vms->bus, }; =20 if (use_highmem) { @@ -609,7 +611,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPO= RTS); acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), - vms->highmem, vms->highmem_ecam); + vms->highmem, vms->highmem_ecam, vms); if (vms->acpi_dev) { build_ged_aml(scope, "\\_SB."GED_DEVICE, HOTPLUG_HANDLER(vms->acpi_dev), diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 32a9f2796d..7f20ee1c98 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -1,6 +1,10 @@ #include "qemu/osdep.h" #include "hw/acpi/aml-build.h" #include "hw/pci-host/gpex.h" +#include "hw/arm/virt.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/pcie_host.h" =20 static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq) { @@ -124,7 +128,57 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig = *cfg) { int nr_pcie_buses =3D cfg->ecam.size / PCIE_MMCFG_SIZE_MIN; Aml *method, *crs, *dev, *rbuf; + PCIBus *bus =3D cfg->bus; + CrsRangeSet crs_range_set; =20 + /* start to construct the tables for pxb */ + crs_range_set_init(&crs_range_set); + if (bus) { + QLIST_FOREACH(bus, &bus->child, sibling) { + uint8_t bus_num =3D pci_bus_num(bus); + uint8_t numa_node =3D pci_bus_numa_node(bus); + + if (!pci_bus_is_root(bus)) { + continue; + } + + /* + * 0 - (nr_pcie_buses - 1) is the bus range for the main + * host-bridge and it equals the MIN of the + * busNr defined for pxb-pcie. + */ + if (bus_num < nr_pcie_buses) { + nr_pcie_buses =3D bus_num; + } + + dev =3D aml_device("PC%.02X", bus_num); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); + aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device"= ))); + if (numa_node !=3D NUMA_NODE_UNASSIGNED) { + aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); + } + + acpi_dsdt_add_pci_route_table(dev, cfg->irq); + + /* + * Resources defined for PXBs are composed by the folling part= s: + * 1. The resources the pci-brige/pcie-root-port need. + * 2. The resources the devices behind pxb need. + */ + crs =3D build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_rang= e_set); + aml_append(dev, aml_name_decl("_CRS", crs)); + + acpi_dsdt_add_pci_osc(dev); + + aml_append(scope, dev); + } + } + crs_range_set_free(&crs_range_set); + + /* tables for the main */ dev =3D aml_device("%s", "PCI0"); aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index d52ea80d4e..d48a020a95 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -59,6 +59,7 @@ struct GPEXConfig { MemMapEntry mmio64; MemMapEntry pio; int irq; + PCIBus *bus; }; =20 int gpex_set_irq_num(GPEXHost *s, int index, int gsi); --=20 2.28.0 From nobody Mon May 6 05:32:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1605750765; cv=none; d=zohomail.com; s=zohoarc; b=S3/dhgtyeh2s61pWzjiLYdd5ipeiohgSDBCFz3mJ0fDCodSwPhnxW9B9sde+zz6mE5Wca742/9JLmnpjKvptnmsrVjlLLX2KmJJM02FF1rsEnaX5qqXsu7C1GIv3pxppZSLtHjOiY+EVocUzxUBICx/lDjf+jmjl6AwyfZ/n1gs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605750765; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=X1A3vbJYn+s1VBeOaq3j/Sd/+8YZO2RkwbKPjoihhLI=; b=kW5q/Zg4+R8l+pZXRTXi3r6h2H1eQGV0r8x1tLoxZzYrex1PZCMhTIt+U9ex+fTGeVdsUon8LhNYNdJEmpy85ciRMp0EAVzHDN03uoc7K5aeVkE1IO/eOt6a+jT2XzN0nEaY9yrU9DvqY/k8glNGBKHKuI6XkaT+0fAsZaLComY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605750765089594.315311470999; Wed, 18 Nov 2020 17:52:45 -0800 (PST) Received: from localhost ([::1]:35338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfZ7r-00011k-53 for importer@patchew.org; Wed, 18 Nov 2020 20:52:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45530) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfZ6D-0008FS-OS for qemu-devel@nongnu.org; Wed, 18 Nov 2020 20:51:01 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2460) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfZ6A-0003NT-Ug for qemu-devel@nongnu.org; Wed, 18 Nov 2020 20:51:01 -0500 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4Cc2gm3wjSzLlyS; Thu, 19 Nov 2020 09:50:28 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Thu, 19 Nov 2020 09:50:40 +0800 From: Jiahui Cen To: Subject: [PATCH v10 6/9] acpi: Align the size to 128k Date: Thu, 19 Nov 2020 09:48:38 +0800 Message-ID: <20201119014841.7298-7-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201119014841.7298-1-cenjiahui@huawei.com> References: <20201119014841.7298-1-cenjiahui@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=cenjiahui@huawei.com; helo=szxga05-in.huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/18 20:50:48 X-ACL-Warn: Detected OS = Linux 3.1-3.10 [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Peter Maydell , Jiahui Cen , berrange@redhat.com, Eduardo Habkost , "Michael S. Tsirkin" , Laszlo Ersek , Richard Henderson , Shannon Zhao , miaoyubo@huawei.com, Gerd Hoffmann , Paolo Bonzini , Igor Mammedov , philmd@redhat.com, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Yubo Miao If table size is changed between virt_acpi_build and virt_acpi_build_update, the table size would not be updated to UEFI, therefore, just align the size to 128kb, which is enough and same with x86. It would warn if 64k is not enough and the align size should be updated. Signed-off-by: Yubo Miao Signed-off-by: Jiahui Cen --- hw/arm/virt-acpi-build.c | 25 ++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index e0bed9037c..711cf2069f 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -57,6 +57,8 @@ =20 #define ARM_SPI_BASE 32 =20 +#define ACPI_BUILD_TABLE_SIZE 0x20000 + static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) { uint16_t i; @@ -656,6 +658,15 @@ struct AcpiBuildState { bool patched; } AcpiBuildState; =20 +static void acpi_align_size(GArray *blob, unsigned align) +{ + /* + * Align size to multiple of given size. This reduces the chance + * we need to change size in the future (breaking cross version migrat= ion). + */ + g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); +} + static void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) { @@ -743,6 +754,20 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildT= ables *tables) build_rsdp(tables->rsdp, tables->linker, &rsdp_data); } =20 + /* + * The align size is 128, warn if 64k is not enough therefore + * the align size could be resized. + */ + if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { + warn_report("ACPI table size %u exceeds %d bytes," + " migration may not work", + tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); + error_printf("Try removing CPUs, NUMA nodes, memory slots" + " or PCI bridges."); + } + acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); + + /* Cleanup memory that's no longer used. */ g_array_free(table_offsets, true); } --=20 2.28.0 From nobody Mon May 6 05:32:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1605751171; cv=none; d=zohomail.com; s=zohoarc; b=LYgbCwoe5Eg6cZYPYrxw/30+7MsacLuaYlRzES/Xgt3fbWN7CrfAZd14fk4xbZymW3QtnyJLMwfk9c76ft99Z5e7iVjdylxC+dGKlRAXfzoOvsqQ3e8e62jcPv/KekFPbP1hT3EzmwHBaJ9aZSNpTIAvZH57m2DlTbwjjYdL2dE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605751171; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UbyLXeOfrMgQxeSpa0ctxxXQANZASWYfjhddAPN1Fg0=; b=kZKp5AKMctV7diUzkmnI4pQf2s3Oe0ddtM3ejFXYKNel9WVkqu+AjU7bsYkn3xMj7m5sJ/wNyGQwKr+2DILQhrxhRcNSn1kCh/sRTAmLRzPTz27rbVFU3ndzCRNm8xfpRYTw9pXifVHXcNO5qpgCewIp82331ZWG+WfPjMGVJrc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605751171742441.4698264153716; Wed, 18 Nov 2020 17:59:31 -0800 (PST) Received: from localhost ([::1]:53192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kfZEQ-0008NM-Lc for importer@patchew.org; Wed, 18 Nov 2020 20:59:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45632) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfZ6I-0008M3-Sw for qemu-devel@nongnu.org; Wed, 18 Nov 2020 20:51:06 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2527) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfZ6B-0003NQ-3E for qemu-devel@nongnu.org; Wed, 18 Nov 2020 20:51:06 -0500 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4Cc2gs1cV7zhYN4; Thu, 19 Nov 2020 09:50:33 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 19 Nov 2020 09:50:40 +0800 From: Jiahui Cen To: Subject: [PATCH v10 7/9] unit-test: The files changed. Date: Thu, 19 Nov 2020 09:48:39 +0800 Message-ID: <20201119014841.7298-8-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201119014841.7298-1-cenjiahui@huawei.com> References: <20201119014841.7298-1-cenjiahui@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=cenjiahui@huawei.com; helo=szxga05-in.huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/18 20:50:48 X-ACL-Warn: Detected OS = Linux 3.1-3.10 [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Peter Maydell , Jiahui Cen , berrange@redhat.com, Eduardo Habkost , "Michael S. Tsirkin" , Laszlo Ersek , Richard Henderson , Shannon Zhao , miaoyubo@huawei.com, Gerd Hoffmann , Paolo Bonzini , Igor Mammedov , philmd@redhat.com, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Yubo Miao The unit-test is seperated into three patches: 1. The files changed and list in bios-tables-test-allowed-diff.h 2. The unit-test 3. The binary file and clear bios-tables-test-allowed-diff.h The ASL diff would also be listed. Sice there are 1000+lines diff, some changes would be omitted. * Original Table Header: * Signature "DSDT" - * Length 0x000014BB (5307) + * Length 0x00001E7A (7802) * Revision 0x02 - * Checksum 0xD1 + * Checksum 0x57 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) + Device (PC80) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_SEG, Zero) // _SEG: PCI Segment + Name (_BBN, 0x80) // _BBN: BIOS Bus Number + Name (_UID, 0x80) // _UID: Unique ID + Name (_STR, Unicode ("pxb Device")) // _STR: Description Stri= ng + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { + Package (0x04) + { + 0xFFFF, + Zero, + GSI0, + Zero + }, + Packages are omitted. + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSI2, + Zero + } + }) + Device (GSI0) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) //= _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resourc= e Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclus= ive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource= Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclus= ive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Set= tings + { + } + } GSI1,2,3 are omitted. + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDe= code, + 0x0000, // Granularity + 0x0080, // Range Minimum + 0x0080, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 =3D=3D ToUUID ("33db4d5b-1ff7-401c-9657-7441c03d= d766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP =3D CDW2 /* \_SB_.PC80._OSC.CDW2 */ + CTRL =3D CDW3 /* \_SB_.PC80._OSC.CDW3 */ + CTRL &=3D 0x1F + If ((Arg1 !=3D One)) + { + CDW1 |=3D 0x08 + } + + If ((CDW3 !=3D CTRL)) + { + CDW1 |=3D 0x10 + } + + CDW3 =3D CTRL /* \_SB_.PC80.CTRL */ + Return (Arg3) + } + Else + { + CDW1 |=3D 0x04 + Return (Arg3) + } + } DSM is are omitted Device (PCI0) { Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode, 0x0000, // Granularity 0x0000, // Range Minimum - 0x00FF, // Range Maximum + 0x007F, // Range Maximum 0x0000, // Translation Offset - 0x0100, // Length + 0x0080, // Length Signed-off-by: Yubo Miao Signed-off-by: Jiahui Cen --- tests/qtest/bios-tables-test-allowed-diff.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..90c53925fc 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,2 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/DSDT.pxb", --=20 2.28.0 From nobody Mon May 6 05:32:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 19 Nov 2020 09:50:41 +0800 From: Jiahui Cen To: Subject: [PATCH v10 8/9] unit-test: Add testcase for pxb Date: Thu, 19 Nov 2020 09:48:40 +0800 Message-ID: <20201119014841.7298-9-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201119014841.7298-1-cenjiahui@huawei.com> References: <20201119014841.7298-1-cenjiahui@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=cenjiahui@huawei.com; helo=szxga04-in.huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/18 20:50:47 X-ACL-Warn: Detected OS = Linux 3.1-3.10 [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Peter Maydell , Jiahui Cen , berrange@redhat.com, Eduardo Habkost , "Michael S. Tsirkin" , Laszlo Ersek , Richard Henderson , Shannon Zhao , miaoyubo@huawei.com, Gerd Hoffmann , Paolo Bonzini , Igor Mammedov , philmd@redhat.com, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Yubo Miao Add testcase for pxb to make sure the ACPI table is correct for guest. Signed-off-by: Yubo Miao Signed-off-by: Jiahui Cen --- tests/qtest/bios-tables-test.c | 58 ++++++++++++++++++-- 1 file changed, 52 insertions(+), 6 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index f23a5335a8..64a9a772ee 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -671,12 +671,21 @@ static void test_acpi_one(const char *params, test_da= ta *data) * TODO: convert '-drive if=3Dpflash' to new syntax (see e33763be7= cd3) * when arm/virt boad starts to support it. */ - args =3D g_strdup_printf("-machine %s %s -accel tcg -nodefaults -n= ographic " - "-drive if=3Dpflash,format=3Draw,file=3D%s,readonly " - "-drive if=3Dpflash,format=3Draw,file=3D%s,snapshot=3Don -cdro= m %s %s", - data->machine, data->tcg_only ? "" : "-accel kvm", - data->uefi_fl1, data->uefi_fl2, data->cd, params ? params : ""= ); - + if (data->cd) { + args =3D g_strdup_printf("-machine %s %s -accel tcg " + "-nodefaults -nographic " + "-drive if=3Dpflash,format=3Draw,file=3D%s,readonly " + "-drive if=3Dpflash,format=3Draw,file=3D%s,snapshot=3Don -= cdrom %s %s", + data->machine, data->tcg_only ? "" : "-accel kvm", + data->uefi_fl1, data->uefi_fl2, data->cd, params ? params = : ""); + } else { + args =3D g_strdup_printf("-machine %s %s -accel tcg " + "-nodefaults -nographic " + "-drive if=3Dpflash,format=3Draw,file=3D%s,readonly " + "-drive if=3Dpflash,format=3Draw,file=3D%s,snapshot=3Don %= s", + data->machine, data->tcg_only ? "" : "-accel kvm", + data->uefi_fl1, data->uefi_fl2, params ? params : ""); + } } else { args =3D g_strdup_printf("-machine %s %s -accel tcg " "-net none -display none %s " @@ -1176,6 +1185,40 @@ static void test_acpi_virt_tcg_numamem(void) =20 } =20 +#ifdef CONFIG_PXB +static void test_acpi_virt_tcg_pxb(void) +{ + test_data data =3D { + .machine =3D "virt", + .tcg_only =3D true, + .uefi_fl1 =3D "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 =3D "pc-bios/edk2-arm-vars.fd", + .ram_start =3D 0x40000000ULL, + .scan_len =3D 128ULL * 1024 * 1024, + }; + /* + * While using -cdrom, the cdrom would auto plugged into pxb-pcie, + * the reason is the bus of pxb-pcie is also root bus, it would lead + * to the error only PCI/PCIE bridge could plug onto pxb. + * Therefore,thr cdrom is defined and plugged onto the scsi controller + * to solve the conflicts. + */ + data.variant =3D ".pxb"; + test_acpi_one(" -device pcie-root-port,chassis=3D1,id=3Dpci.1" + " -device virtio-scsi-pci,id=3Dscsi0,bus=3Dpci.1" + " -drive file=3D" + "tests/data/uefi-boot-images/bios-tables-test.aarch64.is= o.qcow2," + "if=3Dnone,media=3Dcdrom,id=3Ddrive-scsi0-0-0-1,readonly= =3Don" + " -device scsi-cd,bus=3Dscsi0.0,scsi-id=3D0," + "drive=3Ddrive-scsi0-0-0-1,id=3Dscsi0-0-0-1,bootindex=3D= 1" + " -cpu cortex-a57" + " -device pxb-pcie,bus_nr=3D128", + &data); + + free_test_data(&data); +} +#endif + static void test_acpi_tcg_acpi_hmat(const char *machine) { test_data data; @@ -1287,6 +1330,9 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/virt", test_acpi_virt_tcg); qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem); qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); +#ifdef CONFIG_PXB + qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); +#endif } ret =3D g_test_run(); boot_sector_cleanup(disk); --=20 2.28.0 From nobody Mon May 6 05:32:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1605750863; cv=none; d=zohomail.com; s=zohoarc; b=fS9QRs6EN212Ya6GM7fDiVWYvYO0Zu7VpkaXL7aNapU3/8Pn8q2AoeQwT9ejnSgPl4Dl7NdQRIFvLPRa0trOinpE1Hkoupkk/fkXqj+06cX2wgbMsxoO9mOtPjnZCS0zkQz/FPcGu9Cgi7jBUH36cv9MCpjoisOD5eSNSPkIPiw= ARC-Message-Signature: i=1; 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Wed, 18 Nov 2020 20:54:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45580) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfZ6F-0008GP-Il for qemu-devel@nongnu.org; Wed, 18 Nov 2020 20:51:03 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2862) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfZ6A-0003NZ-V4 for qemu-devel@nongnu.org; Wed, 18 Nov 2020 20:51:03 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4Cc2gt2X6Dz15MZZ; Thu, 19 Nov 2020 09:50:34 +0800 (CST) Received: from localhost (10.174.184.155) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.487.0; Thu, 19 Nov 2020 09:50:41 +0800 From: Jiahui Cen To: Subject: [PATCH v10 9/9] unit-test: Add the binary file and clear diff.h Date: Thu, 19 Nov 2020 09:48:41 +0800 Message-ID: <20201119014841.7298-10-cenjiahui@huawei.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201119014841.7298-1-cenjiahui@huawei.com> References: <20201119014841.7298-1-cenjiahui@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.184.155] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=cenjiahui@huawei.com; helo=szxga04-in.huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/18 20:50:47 X-ACL-Warn: Detected OS = Linux 3.1-3.10 [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, Peter Maydell , Jiahui Cen , berrange@redhat.com, Eduardo Habkost , "Michael S. Tsirkin" , Laszlo Ersek , Richard Henderson , Shannon Zhao , miaoyubo@huawei.com, Gerd Hoffmann , Paolo Bonzini , Igor Mammedov , philmd@redhat.com, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Yubo Miao Add the binary file DSDT.pxb and clear bios-tables-test-allowed-diff.h Signed-off-by: Yubo Miao Signed-off-by: Jiahui Cen --- tests/data/acpi/virt/DSDT.pxb | Bin 0 -> 7802 bytes tests/qtest/bios-tables-test-allowed-diff.h | 1 - 2 files changed, 1 deletion(-) diff --git a/tests/data/acpi/virt/DSDT.pxb b/tests/data/acpi/virt/DSDT.pxb new file mode 100644 index 0000000000000000000000000000000000000000..d5f0533a02d62bc2ae2db9b9de9= 484e5c06652fe GIT binary patch literal 7802 zcmeI1%WoT16o;=3DLiS6+tw&OgUms2Pe&&rRcNlRN|kDbINPK+mQkW$GN2t>&y5*4DY z5GE1@x}%ZUunAHY{255B*s){5x*Prhb`0mvok@O&o()@MN3!S4-1E)-#wYff>!#D( zdAOidc(<`_Z#avMce{3z_Jx#EdRxC{zj_wB({~#Ey~7#1TrS7^8|`MgZg<-hEUS3` zR=3DcV84zJqVo#0rnvr#TrD*mx}-|jiN8EfisLTO+^WtIANRE0w4D0)D-m9e1W1K-`?I3=3D=3D%fJX5q(*jFqgf=3DxI;=3D+i!j2&*$h#YZ&sEUM@nAgr*&hytUE zjGD-ZNQ_Zn)R1vWWJD!K92l37u_Q7^B!&fyC1hL{8KV*-1&qtcSQZ&EiID-uGBQ>~ zMqFZKfw6*&DG%GO{fw77VxlVHu;{{;Uks;S< zUSgaFMgtjgosLV43&5~}QI+eoATeGBMiUuwolZ!MSAo$&hFqtU661AXtRX|L(Vw8cgfeg7$ixQ&>j5adlI-QXimw<5-8FHP@N{q|EcpDjVoz6*&6<};4 zL$1?#iE$Me9bnYtI$e+$*MPBw47pBA65|FiwtYtDhpxTi&!fB5E!WE{)VJ8wgqf&D zQN7vI`@BBFX|2AGs&X_uAR4$*c+C9j#H9`7}G}OzaP-oI?ys;54Gnhd{>C9kg#AMP?FOx!@Ni*^?sUtLF z{m6IphEmhyTLvL|jxf&=3D@0@|>h{+5lPa%4aGEZuLX$HYiYO>IiLiCI=3D&lvNJaZd`- zGtNBYUS@Dfs3}8F3ehvcJgIFrSI@g73GPWDdRolWVxH8*p(lmtnPi?x=3D9%Q46ryK} zd8U{rHGSwwA$q2nXPSAYxhI9_nPHw8=3D1EN=3DdQymU3el5po1kv9%#)f* z^rR3ybIdcxJagQWLiEft&ph*_CKNp>M9*>NInF%CxhI9_Szw+8=3D1EN}dQym<6U=3Djh zc}{Ro3ej_tc}_ARl0q^1}>DMZgA^DHvYBKM>a zJ!hEb4D+NW8a*jQ&spX<%RFbfCxz%a$2{klCpF#ZNg;a9GtYVEInO;QL{D1OFrQi8 zXZ!;5q$V9bDMZf_^DHsX68EIgcZYER-{LZqUNJz{O9IR6<1D|`%V{aWZ#O?fGWMl>9uyC1I^JJHH~_tpRAI8KF&Tp zx)=3DJKj#RwSmE*~$N5MF=3DJF5>K=3D)rpb$^MTSvtOU2a0Ek zp0J{OUnX^Ex184IVqw1Dy1kP)(81l~?9rpUmR_}c+}-Uptij%4QEy