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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt , Kito Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Frank Chang --- target/riscv/insn32-64.decode | 3 ++ target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvb.c.inc | 54 +++++++++++++++++++++++++ target/riscv/translate.c | 48 ++++++++++++++++++++++ 4 files changed, 108 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index cc6b7d63774..a1a4b12f7ca 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -100,9 +100,12 @@ sbinvw 0110100 .......... 001 ..... 0111011 @r sbextw 0100100 .......... 101 ..... 0111011 @r slow 0010000 .......... 001 ..... 0111011 @r srow 0010000 .......... 101 ..... 0111011 @r +rorw 0110000 .......... 101 ..... 0111011 @r +rolw 0110000 .......... 001 ..... 0111011 @r =20 sbsetiw 0010100 .......... 001 ..... 0011011 @sh5 sbclriw 0100100 .......... 001 ..... 0011011 @sh5 sbinviw 0110100 .......... 001 ..... 0011011 @sh5 sloiw 0010000 .......... 001 ..... 0011011 @sh5 sroiw 0010000 .......... 101 ..... 0011011 @sh5 +roriw 0110000 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6e3eef84144..01b8ebc4bee 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -617,6 +617,8 @@ sbinv 0110100 .......... 001 ..... 0110011 @r sbext 0100100 .......... 101 ..... 0110011 @r slo 0010000 .......... 001 ..... 0110011 @r sro 0010000 .......... 101 ..... 0110011 @r +ror 0110000 .......... 101 ..... 0110011 @r +rol 0110000 .......... 001 ..... 0110011 @r =20 sbseti 001010 ........... 001 ..... 0010011 @sh sbclri 010010 ........... 001 ..... 0010011 @sh @@ -624,3 +626,4 @@ sbinvi 011010 ........... 001 ..... 0010011 @sh sbexti 010010 ........... 101 ..... 0010011 @sh sloi 001000 ........... 001 ..... 0010011 @sh sroi 001000 ........... 101 ..... 0010011 @sh +rori 011000 ........... 101 ..... 0010011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index 4c93c5aab8b..ba8734203ac 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -189,7 +189,29 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a) return gen_arith_shamt_tl(ctx, a, &gen_sro); } =20 +static bool trans_ror(DisasContext *ctx, arg_ror *a) { + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &tcg_gen_rotr_tl); +} + +static bool trans_rori(DisasContext *ctx, arg_rori *a) +{ + REQUIRE_EXT(ctx, RVB); + + if (a->shamt >=3D TARGET_LONG_BITS) { + return false; + } + + return gen_arith_shamt_tl(ctx, a, &tcg_gen_rotr_tl); +} + +static bool trans_rol(DisasContext *ctx, arg_rol *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &tcg_gen_rotl_tl); +} + /* RV64-only instructions */ #ifdef TARGET_RISCV64 =20 @@ -289,4 +311,36 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *= a) return gen_arith_shamt_tl(ctx, a, &gen_srow); } =20 +static bool trans_rorw(DisasContext *ctx, arg_rorw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_rorw); +} + +static bool trans_roriw(DisasContext *ctx, arg_roriw *a) +{ + REQUIRE_EXT(ctx, RVB); + + if (a->shamt >=3D 32) { + return false; + } + + if (a->shamt =3D=3D 0) { + TCGv t =3D tcg_temp_new(); + gen_get_gpr(t, a->rs1); + tcg_gen_ext32s_tl(t, t); + gen_set_gpr(a->rd, t); + tcg_temp_free(t); + return true; + } + + return gen_arith_shamt_tl(ctx, a, &gen_rorw); +} + +static bool trans_rolw(DisasContext *ctx, arg_rolw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_rolw); +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8972e247bd7..68870bd9202 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1092,6 +1092,54 @@ static void gen_srow(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(t); } =20 +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv shamt; + TCGv_i32 t1, t2; + shamt =3D tcg_temp_new(); + t1 =3D tcg_temp_new_i32(); + t2 =3D tcg_temp_new_i32(); + + gen_sbopw_shamt(shamt, arg2); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, shamt); + + tcg_gen_rotr_i32(t1, t1, t2); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free(shamt); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv shamt; + TCGv_i32 t1, t2; + shamt =3D tcg_temp_new(); + t1 =3D tcg_temp_new_i32(); + t2 =3D tcg_temp_new_i32(); + + gen_sbopw_shamt(shamt, arg2); + + /* truncate to 32-bits */ + tcg_gen_trunc_tl_i32(t1, arg1); + tcg_gen_trunc_tl_i32(t2, shamt); + + tcg_gen_rotl_i32(t1, t1, t2); + + /* sign-extend 64-bits */ + tcg_gen_ext_i32_tl(ret, t1); + + tcg_temp_free(shamt); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); +} + #endif =20 static bool gen_arith(DisasContext *ctx, arg_r *a, --=20 2.17.1