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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt , Kito Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Kito Cheng Signed-off-by: Kito Cheng --- target/riscv/insn32-64.decode | 4 ++ target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvb.c.inc | 58 ++++++++++++++++++++ target/riscv/translate.c | 70 +++++++++++++++++++++++++ 4 files changed, 136 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 92f3aaac3b6..cc6b7d63774 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -98,7 +98,11 @@ sbsetw 0010100 .......... 001 ..... 0111011 @r sbclrw 0100100 .......... 001 ..... 0111011 @r sbinvw 0110100 .......... 001 ..... 0111011 @r sbextw 0100100 .......... 101 ..... 0111011 @r +slow 0010000 .......... 001 ..... 0111011 @r +srow 0010000 .......... 101 ..... 0111011 @r =20 sbsetiw 0010100 .......... 001 ..... 0011011 @sh5 sbclriw 0100100 .......... 001 ..... 0011011 @sh5 sbinviw 0110100 .......... 001 ..... 0011011 @sh5 +sloiw 0010000 .......... 001 ..... 0011011 @sh5 +sroiw 0010000 .......... 101 ..... 0011011 @sh5 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 69e542da19c..6e3eef84144 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -615,8 +615,12 @@ sbset 0010100 .......... 001 ..... 0110011 @r sbclr 0100100 .......... 001 ..... 0110011 @r sbinv 0110100 .......... 001 ..... 0110011 @r sbext 0100100 .......... 101 ..... 0110011 @r +slo 0010000 .......... 001 ..... 0110011 @r +sro 0010000 .......... 101 ..... 0110011 @r =20 sbseti 001010 ........... 001 ..... 0010011 @sh sbclri 010010 ........... 001 ..... 0010011 @sh sbinvi 011010 ........... 001 ..... 0010011 @sh sbexti 010010 ........... 101 ..... 0010011 @sh +sloi 001000 ........... 001 ..... 0010011 @sh +sroi 001000 ........... 101 ..... 0010011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index dabf8e09c3d..4c93c5aab8b 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -155,6 +155,40 @@ static bool trans_sbexti(DisasContext *ctx, arg_sbexti= *a) return gen_arith_shamt_tl(ctx, a, &gen_sbext); } =20 +static bool trans_slo(DisasContext *ctx, arg_slo *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_slo); +} + +static bool trans_sloi(DisasContext *ctx, arg_sloi *a) +{ + REQUIRE_EXT(ctx, RVB); + + if (a->shamt >=3D TARGET_LONG_BITS) { + return false; + } + + return gen_arith_shamt_tl(ctx, a, &gen_slo); +} + +static bool trans_sro(DisasContext *ctx, arg_sro *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_sro); +} + +static bool trans_sroi(DisasContext *ctx, arg_sroi *a) +{ + REQUIRE_EXT(ctx, RVB); + + if (a->shamt >=3D TARGET_LONG_BITS) { + return false; + } + + return gen_arith_shamt_tl(ctx, a, &gen_sro); +} + { /* RV64-only instructions */ #ifdef TARGET_RISCV64 @@ -231,4 +265,28 @@ static bool trans_sbextw(DisasContext *ctx, arg_sbextw= *a) return gen_arith(ctx, a, &gen_sbextw); } =20 +static bool trans_slow(DisasContext *ctx, arg_slow *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_slow); +} + +static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_slow); +} + +static bool trans_srow(DisasContext *ctx, arg_srow *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_srow); +} + +static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_shamt_tl(ctx, a, &gen_srow); +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e7d9e4a1abf..8972e247bd7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -887,6 +887,38 @@ static void gen_sbext(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(shamt); } =20 +static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv shamt, t; + shamt =3D tcg_temp_new(); + t =3D tcg_temp_new(); + + gen_sbop_shamt(shamt, arg2); + + tcg_gen_not_tl(t, arg1); + tcg_gen_shl_tl(t, t, arg2); + tcg_gen_not_tl(ret, t); + + tcg_temp_free(shamt); + tcg_temp_free(t); +} + +static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv shamt, t; + shamt =3D tcg_temp_new(); + t =3D tcg_temp_new(); + + gen_sbop_shamt(shamt, arg2); + + tcg_gen_not_tl(t, arg1); + tcg_gen_shr_tl(t, t, arg2); + tcg_gen_not_tl(ret, t); + + tcg_temp_free(shamt); + tcg_temp_free(t); +} + =20 #ifdef TARGET_RISCV64 =20 @@ -1022,6 +1054,44 @@ static void gen_sbextw(TCGv ret, TCGv arg1, TCGv arg= 2) tcg_temp_free(shamt); } =20 +static void gen_slow(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv shamt, t; + shamt =3D tcg_temp_new(); + t =3D tcg_temp_new(); + + tcg_gen_ext32u_tl(arg1, arg1); + + gen_sbopw_shamt(shamt, arg2); + tcg_gen_not_tl(t, arg1); + tcg_gen_shl_tl(t, t, shamt); + tcg_gen_not_tl(ret, t); + + tcg_gen_ext32s_tl(ret, ret); + + tcg_temp_free(shamt); + tcg_temp_free(t); +} + +static void gen_srow(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv shamt, t; + shamt =3D tcg_temp_new(); + t =3D tcg_temp_new(); + + tcg_gen_ext32u_tl(arg1, arg1); + + gen_sbopw_shamt(shamt, arg2); + tcg_gen_not_tl(t, arg1); + tcg_gen_shr_tl(t, t, shamt); + tcg_gen_not_tl(ret, t); + + tcg_gen_ext32s_tl(ret, ret); + + tcg_temp_free(shamt); + tcg_temp_free(t); +} + #endif =20 static bool gen_arith(DisasContext *ctx, arg_r *a, --=20 2.17.1