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bh=gJvNlMPcGTPAbFboGsstPpVzQRHGQSY2TQRLZKzwVck=; b=XrO2TNx/f/dyFJLZCudUmIaSCvQ+LQATZ1ZNcJFvD1ZbcqVOs36oE0nFT7QfTbSew/vr3l DaZ/zGYBuvRep3LP323U7MxRRkvgJL1la+qnhDd+W3N9gOWNVhE5Ry3lSUDWsi7cKrGwcl r63HLvpttE9pb6NAn9Lb7toZeSF8UqQ= X-MC-Unique: 215GnqueONmNXzO2cTIghg-1 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, alex.williamson@redhat.com Subject: [RFC v7 22/26] hw/arm/smmuv3: Pass stage 1 configurations to the host Date: Mon, 16 Nov 2020 19:13:45 +0100 Message-Id: <20201116181349.11908-23-eric.auger@redhat.com> In-Reply-To: <20201116181349.11908-1-eric.auger@redhat.com> References: <20201116181349.11908-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" In case PASID PciOps are set for the device we call the set_pasid_table() callback on each STE update. This allows to pass the guest stage 1 configuration to the host and apply it at physical level. Signed-off-by: Eric Auger --- v4 -> v5: - Use PciOps instead of config notifiers v3 -> v4: - fix compile issue with mingw v2 -> v3: - adapt to pasid_cfg field changes. Use local variable - add trace event - set version fields - use CONFIG_PASID v1 -> v2: - do not notify anymore on CD change. Anyway the smmuv3 linux driver is not sending any CD invalidation commands. If we were to propagate CD invalidation commands, we would use the CACHE_INVALIDATE VFIO ioctl. - notify a precise config flags to prepare for addition of new flags --- hw/arm/smmuv3.c | 78 +++++++++++++++++++++++++++++++++++---------- hw/arm/trace-events | 1 + 2 files changed, 62 insertions(+), 17 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index c314f9e4c9..2b36bb4e4f 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -16,6 +16,10 @@ * with this program; if not, see . */ =20 +#ifdef __linux__ +#include "linux/iommu.h" +#endif + #include "qemu/osdep.h" #include "qemu/bitops.h" #include "hw/irq.h" @@ -878,6 +882,61 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *c= md) smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl); } =20 +static void smmuv3_notify_config_change(SMMUState *bs, uint32_t sid) +{ +#ifdef __linux__ + IOMMUMemoryRegion *mr =3D smmu_iommu_mr(bs, sid); + SMMUEventInfo event =3D {.type =3D SMMU_EVT_NONE, .sid =3D sid, + .inval_ste_allowed =3D true}; + IOMMUConfig iommu_config =3D {}; + SMMUTransCfg *cfg; + SMMUDevice *sdev; + + if (!mr) { + return; + } + + sdev =3D container_of(mr, SMMUDevice, iommu); + + /* flush QEMU config cache */ + smmuv3_flush_config(sdev); + + if (!pci_device_is_pasid_ops_set(sdev->bus, sdev->devfn)) { + return; + } + + cfg =3D smmuv3_get_config(sdev, &event); + + if (!cfg) { + return; + } + + iommu_config.pasid_cfg.argsz =3D sizeof(struct iommu_pasid_table_confi= g); + iommu_config.pasid_cfg.version =3D PASID_TABLE_CFG_VERSION_1; + iommu_config.pasid_cfg.format =3D IOMMU_PASID_FORMAT_SMMUV3; + iommu_config.pasid_cfg.base_ptr =3D cfg->s1ctxptr; + iommu_config.pasid_cfg.pasid_bits =3D 0; + iommu_config.pasid_cfg.vendor_data.smmuv3.version =3D PASID_TABLE_SMMU= V3_CFG_VERSION_1; + + if (cfg->disabled || cfg->bypassed) { + iommu_config.pasid_cfg.config =3D IOMMU_PASID_CONFIG_BYPASS; + } else if (cfg->aborted) { + iommu_config.pasid_cfg.config =3D IOMMU_PASID_CONFIG_ABORT; + } else { + iommu_config.pasid_cfg.config =3D IOMMU_PASID_CONFIG_TRANSLATE; + } + + trace_smmuv3_notify_config_change(mr->parent_obj.name, + iommu_config.pasid_cfg.config, + iommu_config.pasid_cfg.base_ptr); + + if (pci_device_set_pasid_table(sdev->bus, sdev->devfn, &iommu_config))= { + error_report("Failed to pass PASID table to host for iommu mr %s (= %m)", + mr->parent_obj.name); + } +#endif +} + static int smmuv3_cmdq_consume(SMMUv3State *s) { SMMUState *bs =3D ARM_SMMU(s); @@ -928,22 +987,14 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) case SMMU_CMD_CFGI_STE: { uint32_t sid =3D CMD_SID(&cmd); - IOMMUMemoryRegion *mr =3D smmu_iommu_mr(bs, sid); - SMMUDevice *sdev; =20 if (CMD_SSEC(&cmd)) { cmd_error =3D SMMU_CERROR_ILL; break; } =20 - if (!mr) { - break; - } - trace_smmuv3_cmdq_cfgi_ste(sid); - sdev =3D container_of(mr, SMMUDevice, iommu); - smmuv3_flush_config(sdev); - + smmuv3_notify_config_change(bs, sid); break; } case SMMU_CMD_CFGI_STE_RANGE: /* same as SMMU_CMD_CFGI_ALL */ @@ -960,14 +1011,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) trace_smmuv3_cmdq_cfgi_ste_range(start, end); =20 for (i =3D start; i <=3D end; i++) { - IOMMUMemoryRegion *mr =3D smmu_iommu_mr(bs, i); - SMMUDevice *sdev; - - if (!mr) { - continue; - } - sdev =3D container_of(mr, SMMUDevice, iommu); - smmuv3_flush_config(sdev); + smmuv3_notify_config_change(bs, i); } break; } diff --git a/hw/arm/trace-events b/hw/arm/trace-events index a335ee891d..35e562ab74 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -52,4 +52,5 @@ smmuv3_config_cache_inv(uint32_t sid) "Config cache INV f= or sid %d" smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu= mr=3D%s" smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, = uint8_t tg, uint64_t num_pages) "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64"= tg=3D%d num_pages=3D0x%"PRIx64 +smmuv3_notify_config_change(const char *name, uint8_t config, uint64_t s1c= txptr) "iommu mr=3D%s config=3D%d s1ctxptr=3D0x%"PRIx64 =20 --=20 2.21.3