From nobody Tue May 7 08:08:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1605426932; cv=none; d=zohomail.com; s=zohoarc; b=Pd7vdgfaQIGka6xipSFs+uZUoiPaZ0pa3E/FmCgiuZ/La5IfUDQaZRyJhncuuHDNhfk/W7TxZ9yZ4iiN4YO+75bznT4oE1LN9aF1emwfosxJmJMJVV+FdhpaCkxFqZTE59tLq22TbluMwnSnC3ZvtQ8G/G84jAQyOLqGVDKkW4o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605426932; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=9ybLAm8v1RsSKAp3L7gXvHr4V9JDk/hOqsmC8qK64TA=; b=CLO+yL3lI/CfATgvesddSA8Iiw7BM2/86QsPGJ9lDlgVLQdufXCnoeHE5XEgvnpRsXp7JSGa9+OtJQOzOIhpDf+gHTFTXAUnJ559ajAmb61ZimiwWHNt/H5GN2DbndeE6DenOQkL+befarcfWWba1CVGx5zfkG9oBBddtN3KLoM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160542693294651.43201772622638; Sat, 14 Nov 2020 23:55:32 -0800 (PST) Received: from localhost ([::1]:52054 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1keCsl-0007VZ-JW for importer@patchew.org; Sun, 15 Nov 2020 02:55:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52760) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1keCrJ-0006mv-Oq; Sun, 15 Nov 2020 02:54:01 -0500 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:55499) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1keCrF-0006G0-Eo; Sun, 15 Nov 2020 02:54:01 -0500 Received: by mail-pj1-x1043.google.com with SMTP id r9so2371476pjl.5; Sat, 14 Nov 2020 23:53:56 -0800 (PST) Received: from vultr.guest ([141.164.41.4]) by smtp.gmail.com with ESMTPSA id x192sm14516879pgx.9.2020.11.14.23.53.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Nov 2020 23:53:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=9ybLAm8v1RsSKAp3L7gXvHr4V9JDk/hOqsmC8qK64TA=; b=GB8MBZiTm93mqJTtRh5vKtZSYZ+YSMCB6k9N17VNUhEwgdMSLL7fObgyYrux5fC12e eGDeErI3TvS8mYeEtn13NoyIDpsGhGiKnFEmQ/+p7M971WcbLzprTaDpCFwqfnbXyqWg Xo89gkFoj1lnXTkYqtQ2+VasqPzGzAF6QQWI3OVWEnSj0G4ATceWbQS6tQU1j22W+X7H pUdsTRrxvQlXaPm375vRl7vtqfW0w51H7D45YQ8eG7/xL854k7bTqDINM7NagxzYWckg ka3gSsUPiU7EthrQpgfJAHrnI7CyoiZGzErfLJYQ5U5nqiwSnGUt57IiakPdk2d7AP3N e2cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=9ybLAm8v1RsSKAp3L7gXvHr4V9JDk/hOqsmC8qK64TA=; b=nE2MM2jR9+pZQAOnFfuroPl0QFPxP0aX/hfOt+RnH1OIH3ukinwkI/mBvHECvOa4pi PMO+xdJAaXB7iuqw9PA8tCayjoVXCsg73ex472ds+OH4Oz+fKuqJ80n7K7iGVqJuZ6HS CXqHRSZEKBSJVqIMWU+YU66ipnfOG/YV1lyu4mCzLU+35W7rRgXTtJsNFmyDg1TcshUL DkfxRT2IO54QKa6y0TmrHRrv3GS7qPIIjRJojNFZ9tpA8Bz+RQxiFjHGwLO4T/anZkwU afdUlQupFxlDPzM2DTBYiskovJUg6lSFBIE7bStOflQutD3vQZ9owUFJUkBSngUgFIwh wSAQ== X-Gm-Message-State: AOAM530pCrL1z9kfXk8rn1r5AN0QLItTirwWhKeLc6afyFUYY/9XwpBA +PLoF6+Oi/CNfAA6YhYuMK0= X-Google-Smtp-Source: ABdhPJxJDnB5YCrP6lWUDMDQ72FsnRRWyi1pnR83oB4KsuMDxhBgm4oAkNoOkKiFwmho+kauDxk4Ew== X-Received: by 2002:a17:902:fe0f:b029:d6:9fa1:eee0 with SMTP id g15-20020a170902fe0fb02900d69fa1eee0mr8389315plj.24.1605426835517; Sat, 14 Nov 2020 23:53:55 -0800 (PST) From: Changbin Du To: "Dr. David Alan Gilbert" , Peter Maydell Subject: [PATCH v3] arm/monitor: Add support for 'info tlb' command Date: Sun, 15 Nov 2020 15:53:47 +0800 Message-Id: <20201115075347.74622-1-changbin.du@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=changbin.du@gmail.com; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Changbin Du Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This adds hmp 'info tlb' command support for the arm platform. The limitation is that this only implements a page walker for ARMv8-A AArch64 Long Descriptor format, 32bit addressing is not supported yet. To reuse existing code, this patch also extracts some APIs from helper.c, including regime_translation_disabled(), pt_start_level_stage1(), regime_ttbr(). (qemu) info tlb vaddr paddr size attr ---------------- ---------------- ---------------- ------------------------= ------ ffff800000000000 0000000040000000 0000000000001000 RW AF P= XN UXN ffff800000001000 0000000040001000 0000000000001000 RW AF P= XN UXN ffff800000002000 0000000040002000 0000000000001000 RW AF P= XN UXN ffff800000003000 0000000040003000 0000000000001000 RW AF P= XN UXN ffff800000004000 0000000040004000 0000000000001000 RW AF P= XN UXN ffff800000005000 0000000040005000 0000000000001000 RW AF P= XN UXN ffff800000006000 0000000040006000 0000000000001000 RW AF P= XN UXN Signed-off-by: Changbin Du --- v3: rebase to latest mainline. v2: o fix coding style o extract common code pt_start_level_stage1() --- hmp-commands-info.hx | 3 +- target/arm/helper.c | 30 +------ target/arm/internals.h | 33 ++++++++ target/arm/monitor.c | 183 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 220 insertions(+), 29 deletions(-) diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx index 117ba25f91..1b5b3f2616 100644 --- a/hmp-commands-info.hx +++ b/hmp-commands-info.hx @@ -222,7 +222,8 @@ SRST ERST =20 #if defined(TARGET_I386) || defined(TARGET_SH4) || defined(TARGET_SPARC) |= | \ - defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K) + defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K) = || \ + defined(TARGET_ARM) { .name =3D "tlb", .args_type =3D "", diff --git a/target/arm/helper.c b/target/arm/helper.c index 11b0803df7..e7f0f27c8e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9974,8 +9974,7 @@ static inline uint64_t regime_sctlr(CPUARMState *env,= ARMMMUIdx mmu_idx) #ifndef CONFIG_USER_ONLY =20 /* Return true if the specified stage of address translation is disabled */ -static inline bool regime_translation_disabled(CPUARMState *env, - ARMMMUIdx mmu_idx) +bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx) { if (arm_feature(env, ARM_FEATURE_M)) { switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & @@ -10021,20 +10020,6 @@ static inline bool regime_translation_big_endian(C= PUARMState *env, return (regime_sctlr(env, mmu_idx) & SCTLR_EE) !=3D 0; } =20 -/* Return the TTBR associated with this translation regime */ -static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, - int ttbrn) -{ - if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { - return env->cp15.vttbr_el2; - } - if (ttbrn =3D=3D 0) { - return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; - } else { - return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; - } -} - #endif /* !CONFIG_USER_ONLY */ =20 /* Convert a possible stage1+2 MMU index into the appropriate @@ -11077,18 +11062,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, t= arget_ulong address, } =20 if (mmu_idx !=3D ARMMMUIdx_Stage2) { - /* The starting level depends on the virtual address size (which c= an - * be up to 48 bits) and the translation granule size. It indicates - * the number of strides (stride bits at a time) needed to - * consume the bits of the input address. In the pseudocode this i= s: - * level =3D 4 - RoundUp((inputsize - grainsize) / stride) - * where their 'inputsize' is our 'inputsize', 'grainsize' is - * our 'stride + 3' and 'stride' is our 'stride'. - * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifyin= g: - * =3D 4 - (inputsize - stride - 3 + stride - 1) / stride - * =3D 4 - (inputsize - 4) / stride; - */ - level =3D 4 - (inputsize - 4) / stride; + level =3D pt_start_level_stage1(inputsize, stride); } else { /* For stage 2 translations the starting level is specified by the * VTCR_EL2.SL0 field (whose interpretation depends on the page si= ze) diff --git a/target/arm/internals.h b/target/arm/internals.h index 5460678756..69c21be774 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -949,6 +949,8 @@ static inline uint32_t regime_el(CPUARMState *env, ARMM= MUIdx mmu_idx) } } =20 +bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx); + /* Return the TCR controlling this translation regime */ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) { @@ -958,6 +960,20 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMU= Idx mmu_idx) return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; } =20 +/* Return the TTBR associated with this translation regime */ +static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, + int ttbrn) +{ + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + return env->cp15.vttbr_el2; + } + if (ttbrn =3D=3D 0) { + return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; + } else { + return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; + } +} + /* Return the FSR value for a debug exception (watchpoint, hardware * breakpoint or BKPT insn) targeting the specified exception level. */ @@ -1291,6 +1307,23 @@ typedef struct ARMCacheAttrs { unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PT= Es */ } ARMCacheAttrs; =20 +static inline int pt_start_level_stage1(int inputsize, int stride) +{ + /* + * The starting level depends on the virtual address size (which can + * be up to 48 bits) and the translation granule size. It indicates + * the number of strides (stride bits at a time) needed to + * consume the bits of the input address. In the pseudocode this is: + * level =3D 4 - RoundUp((inputsize - grainsize) / stride) + * where their 'inputsize' is our 'inputsize', 'grainsize' is + * our 'stride + 3' and 'stride' is our 'stride'. + * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying: + * =3D 4 - (inputsize - stride - 3 + stride - 1) / stride + * =3D 4 - (inputsize - 4) / stride; + */ + return 4 - (inputsize - 4) / stride; +} + bool get_phys_addr(CPUARMState *env, target_ulong address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, diff --git a/target/arm/monitor.c b/target/arm/monitor.c index 169d8a64b6..6991533a07 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -31,6 +31,9 @@ #include "qapi/qmp/qerror.h" #include "qapi/qmp/qdict.h" #include "qom/qom-qobject.h" +#include "monitor/monitor.h" +#include "monitor/hmp-target.h" +#include "internals.h" =20 static GICCapability *gic_cap_new(int version) { @@ -236,3 +239,183 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(= CpuModelExpansionType type, =20 return expansion_info; } + +/* Perform linear address sign extension */ +static target_ulong addr_canonical(int va_bits, target_ulong addr) +{ +#ifdef TARGET_AARCH64 + if (addr & (1UL << (va_bits - 1))) { + addr |=3D (hwaddr)-(1L << va_bits); + } +#endif + + return addr; +} + +#define PTE_HEADER_FIELDS "vaddr paddr "\ + "size attr\n" +#define PTE_HEADER_DELIMITER "---------------- ---------------- "\ + "---------------- ------------------------= ------\n" + +static void print_pte_header(Monitor *mon) +{ + monitor_printf(mon, PTE_HEADER_FIELDS); + monitor_printf(mon, PTE_HEADER_DELIMITER); +} + +static void +print_pte_lpae(Monitor *mon, uint32_t tableattrs, int va_bits, + target_ulong vaddr, hwaddr paddr, target_ulong size, + target_ulong pte) +{ + uint32_t ns =3D extract64(pte, 5, 1) | extract32(tableattrs, 4, 1); + uint32_t ap =3D extract64(pte, 6, 2) & ~extract32(tableattrs, 2, 2); + uint32_t af =3D extract64(pte, 10, 1); + uint32_t ng =3D extract64(pte, 11, 1); + uint32_t gp =3D extract64(pte, 50, 1); + uint32_t con =3D extract64(pte, 52, 1); + uint32_t pxn =3D extract64(pte, 53, 1) | extract32(tableattrs, 0, 1); + uint32_t uxn =3D extract64(pte, 54, 1) | extract32(tableattrs, 1, 1); + + monitor_printf(mon, TARGET_FMT_lx " " TARGET_FMT_plx " " TARGET_FMT_lx + " %s %s %s %s %s %s %s %s %s\n", + addr_canonical(va_bits, vaddr), paddr, size, + ap & 0x2 ? "ro" : "RW", + ap & 0x1 ? "USR" : " ", + ns ? "NS" : " ", + af ? "AF" : " ", + ng ? "nG" : " ", + gp ? "GP" : " ", + con ? "Con" : " ", + pxn ? "PXN" : " ", + uxn ? "UXN" : " "); +} + +static void +walk_pte_lpae(Monitor *mon, bool aarch64, uint32_t tableattrs, hwaddr pt_b= ase, + target_ulong vstart, int cur_level, int stride, int va_bits) +{ + int pg_shift =3D stride + 3; + int descaddr_high =3D aarch64 ? 47 : 39; + int max_level =3D 3; + int ptshift =3D pg_shift + (max_level - cur_level) * stride; + target_ulong pgsize =3D 1UL << ptshift; + int idx; + + for (idx =3D 0; idx < (1UL << stride) && vstart < (1UL << va_bits); + idx++, vstart +=3D pgsize) { + hwaddr pte_addr =3D pt_base + idx * 8; + target_ulong pte =3D 0; + hwaddr paddr; + + cpu_physical_memory_read(pte_addr, &pte, 8); + + if (!extract64(pte, 0, 1)) { + /* invalid entry */ + continue; + } + + if (cur_level =3D=3D max_level) { + /* leaf entry */ + paddr =3D (hwaddr)extract64(pte, pg_shift, + descaddr_high - pg_shift + 1) << pg_shift; + print_pte_lpae(mon, tableattrs, va_bits, vstart, paddr, + pgsize, pte); + } else { + if (extract64(pte, 1, 1)) { + /* table entry */ + paddr =3D (hwaddr)extract64(pte, pg_shift, + descaddr_high - pg_shift + 1) << pg_sh= ift; + tableattrs |=3D extract64(pte, 59, 5); + + walk_pte_lpae(mon, aarch64, tableattrs, paddr, vstart, + cur_level + 1, stride, va_bits); + } else { + /* block entry */ + if ((pg_shift =3D=3D 12 && (cur_level !=3D 1 && cur_level = !=3D 2)) || + (pg_shift =3D=3D 14 && (cur_level !=3D 2)) || + (pg_shift =3D=3D 16 && (cur_level !=3D 0 && cur_level = !=3D 1))) { + monitor_printf(mon, "illegal block entry at level%d\n", + cur_level); + continue; + } + paddr =3D (hwaddr)extract64(pte, ptshift, + descaddr_high - ptshift + 1) << ptshif= t; + print_pte_lpae(mon, tableattrs, va_bits, vstart, paddr, + pgsize, pte); + } + } + } +} + +/* ARMv8-A AArch64 Long Descriptor format */ +static void tlb_info_vmsav8_64(Monitor *mon, CPUArchState *env) +{ + ARMMMUIdx mmu_idx =3D arm_stage1_mmu_idx(env); + uint64_t ttbr[2]; + uint64_t tcr; + int tsz[2]; + bool using16k, using64k; + int stride; + + ttbr[0] =3D regime_ttbr(env, mmu_idx, 0); + ttbr[1] =3D regime_ttbr(env, mmu_idx, 1); + + tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; + using64k =3D extract32(tcr, 14, 1); + using16k =3D extract32(tcr, 15, 1); + tsz[0] =3D extract32(tcr, 0, 6); + tsz[1] =3D extract32(tcr, 16, 6); + + if (using64k) { + stride =3D 13; + } else if (using16k) { + stride =3D 11; + } else { + stride =3D 9; + } + + /* print header */ + print_pte_header(mon); + + for (unsigned int i =3D 0; i < 2; i++) { + if (ttbr[i]) { + hwaddr base =3D extract64(ttbr[i], 1, 47) << 1; + int va_bits =3D 64 - tsz[i]; + target_ulong vstart =3D (target_ulong)i << (va_bits - 1); + int startlevel =3D pt_start_level_stage1(va_bits, stride); + + /* walk ttbrx page tables, starting from address @vstart */ + walk_pte_lpae(mon, true, 0, base, vstart, startlevel, + stride, va_bits); + } + } +} + +void hmp_info_tlb(Monitor *mon, const QDict *qdict) +{ + CPUArchState *env; + + env =3D mon_get_cpu_env(mon); + if (!env) { + monitor_printf(mon, "No CPU available\n"); + return; + } + + if (arm_feature(env, ARM_FEATURE_PMSA)) { + monitor_printf(mon, "No MMU\n"); + return; + } + + if (regime_translation_disabled(env, arm_stage1_mmu_idx(env))) { + monitor_printf(mon, "MMU disabled\n"); + return; + } + + if (!arm_el_is_aa64(env, 1)) { + monitor_printf(mon, "Only AArch64 Long Descriptor is supported\n"); + return; + } + + tlb_info_vmsav8_64(mon, env); +} --=20 2.25.1