From nobody Sat Nov 16 16:23:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1605112531; cv=none; d=zohomail.com; s=zohoarc; b=gtY1kb7oqveZjvHznbwyfT6HcotXFpAlZi3dOIUlTndyfNC7gXwC/qo1NEpaSbXOvugnteRi6BoaOajPS/UHmQGjIVKo2GGqc1JaYuwn5AkPwQ4veDG+DQCg7pT+lnDs7w7cU/iQNLu0fC0FHO7n3VSWyVOz5GSio5xgDNLSr9o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605112531; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9W8Lxyo7LjQbds7RRvpJL7/LGEGRKcbvZzwFoi75cW4=; b=lX5frAdhL5ufc8Gq5oZWZyxCUp/mXJ62Cd/3ILKwg6CnmS7J5n00xHRq1vqry6e66J502yUsCNVmbvci7KCIROkPeM9mP4CUgpXCozRQcKcQ3KXM6bskpzcEkf92BfHRKKRe60C+Gh3VJld6nSQSEiKcL5UpvOZJfGc8uYFjm6M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1605112531810245.7259206050337; Wed, 11 Nov 2020 08:35:31 -0800 (PST) Received: from localhost ([::1]:50592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kct5m-0007qr-BW for importer@patchew.org; Wed, 11 Nov 2020 11:35:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37252) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kcspH-0000qd-Pg for qemu-devel@nongnu.org; Wed, 11 Nov 2020 11:18:27 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:51486) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kcspC-00080O-AL for qemu-devel@nongnu.org; Wed, 11 Nov 2020 11:18:27 -0500 Received: by mail-wm1-x343.google.com with SMTP id 19so2791440wmf.1 for ; Wed, 11 Nov 2020 08:18:21 -0800 (PST) Received: from cmiranda-laptop.localdomain (bl19-104-46.dsl.telepac.pt. [2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9W8Lxyo7LjQbds7RRvpJL7/LGEGRKcbvZzwFoi75cW4=; b=njlb+t6whuVLzTtVk/0nqrscdBtbj+X50tMafxzParZN45bXjcb4OvHtdu+vNQJgmF l6ZCHdTGZj8NWm0yp/jcGz0IVnWORGiAmsG1o0Y5+DGx6tGnF14BXDdUkxoMg7Dv1zOU bmWFFo1BNE5sn74jGtfsA2GVK/0DfdqbN1WqUurh8xTwSpMWHYIoyCeShA/aYZyUC76S MGny3luvzkEbthc42236pYoylBD6BFJQ9Hy9R9YHA5rnZHF41zjLL8iHXcOldzshiRlZ hEGEYziPkeV4lk3zr0eSuVYRCyOW5zH1enyYTLphwmtDwOLsLxBqtXvPQ9B7oNoqSTiw LymQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9W8Lxyo7LjQbds7RRvpJL7/LGEGRKcbvZzwFoi75cW4=; b=EhMrrABvf8K77IqE3q5Wg+OV0iHGSVZTzUvRugVa0Af0JVVWB9Bt8jdPFCQOYcx973 eN8lRId19qIycbVyq/iG5FXmNXu5Z+KMbAD2VPSuVyUGXYcDUr2NFBYdRLxrD5VivVlW NOpy0bO4RvcXYRGemuhbkEB3TnGSg3ddOfhFTBG6qs7yiQgBh1JQIiWR9Yxr/OL7aXgY pvEB7bCJbxVL2HKgKL5pZsZNvgG3esP3EA/gA7MoMuTgww0+m0sZ4RXkCTvqBRd7FdRu uuOy/kxVN03tpsTkqkE3AKUVyMfPTKgicdbx+yHnsKWLlK5Nl4fKuzMVnYndHAf+8Le6 iA8w== X-Gm-Message-State: AOAM53267F43maj5dpEUqWREFx9fiLZW7GKYXzCCv31VPA6dPt5bzcq/ 7Ojm6/G+ibH2jgPnkRoyW52nFd5OwCFw2A== X-Google-Smtp-Source: ABdhPJwFDkgRTwwcb0YvJWgtI6jmRXVJz7rH4kqsrxtB+CI7x2DbWp3b5oyWbtUABlDO4KYwNizsxg== X-Received: by 2002:a1c:e087:: with SMTP id x129mr4816457wmg.2.1605111500003; Wed, 11 Nov 2020 08:18:20 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 11/15] arc: Add gdbstub and XML for debugging support Date: Wed, 11 Nov 2020 16:17:54 +0000 Message-Id: <20201111161758.9636-12-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=cupertinomiranda@gmail.com; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Shahab Vahedi Register layout for the target and the mechanisms to read and set them. Signed-off-by: Shahab Vahedi --- gdb-xml/arc-v2-aux.xml | 32 +++ gdb-xml/arc-v2-core.xml | 45 +++++ gdb-xml/arc-v2-other.xml | 235 ++++++++++++++++++++++ target/arc/gdbstub.c | 420 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 732 insertions(+) create mode 100644 gdb-xml/arc-v2-aux.xml create mode 100644 gdb-xml/arc-v2-core.xml create mode 100644 gdb-xml/arc-v2-other.xml create mode 100644 target/arc/gdbstub.c diff --git a/gdb-xml/arc-v2-aux.xml b/gdb-xml/arc-v2-aux.xml new file mode 100644 index 0000000000..e18168ad05 --- /dev/null +++ b/gdb-xml/arc-v2-aux.xml @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/arc-v2-core.xml b/gdb-xml/arc-v2-core.xml new file mode 100644 index 0000000000..c925a6994c --- /dev/null +++ b/gdb-xml/arc-v2-core.xml @@ -0,0 +1,45 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb-xml/arc-v2-other.xml b/gdb-xml/arc-v2-other.xml new file mode 100644 index 0000000000..9824f518cc --- /dev/null +++ b/gdb-xml/arc-v2-other.xml @@ -0,0 +1,235 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/arc/gdbstub.c b/target/arc/gdbstub.c new file mode 100644 index 0000000000..5f12935216 --- /dev/null +++ b/target/arc/gdbstub.c @@ -0,0 +1,420 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "exec/gdbstub.h" +#include "arc-common.h" +#include "target/arc/regs.h" +#include "internals.h" +#include "irq.h" + +/* gets the register address for a particular processor */ +#define REG_ADDR(reg, processor_type) \ + arc_aux_reg_address_for((reg), (processor_type)) + +int arc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) +{ + ARCCPU *cpu =3D ARC_CPU(cs); + CPUARCState *env =3D &cpu->env; + uint32_t regval =3D 0; + + switch (n) { + case 0 ... 31: + regval =3D env->r[n]; + break; + case GDB_REG_58: + regval =3D env->r[58]; + break; + case GDB_REG_59: + regval =3D env->r[59]; + break; + case GDB_REG_60: + regval =3D env->r[60]; + break; + case GDB_REG_63: + regval =3D env->r[63]; + break; + default: + assert(!"Unsupported register is being read."); + } + + return gdb_get_reg32(mem_buf, regval); +} + +int arc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + ARCCPU *cpu =3D ARC_CPU(cs); + CPUARCState *env =3D &cpu->env; + uint32_t regval =3D ldl_p(mem_buf); + + switch (n) { + case 0 ... 31: + env->r[n] =3D regval; + break; + case GDB_REG_58: + env->r[58] =3D regval; + break; + case GDB_REG_59: + env->r[59] =3D regval; + break; + case GDB_REG_60: + env->r[60] =3D regval; + break; + case GDB_REG_63: + env->r[63] =3D regval; + break; + default: + assert(!"Unsupported register is being written."); + } + + return 4; +} + + +static int +arc_aux_minimal_gdb_get_reg(CPUARCState *env, GByteArray *mem_buf, int reg= num) +{ + /* TODO: processor type must be set according to configuration */ + static const int processor =3D ARC_OPCODE_ARCv2HS; + uint32_t regval =3D 0; + + switch (regnum) { + case GDB_AUX_MIN_REG_PC: + regval =3D env->pc & 0xfffffffe; + break; + case GDB_AUX_MIN_REG_LPS: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_lp_start, processor)); + break; + case GDB_AUX_MIN_REG_LPE: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_lp_end, processor)); + break; + case GDB_AUX_MIN_REG_STATUS: + regval =3D pack_status32(&env->stat); + break; + default: + assert(!"Unsupported minimal auxiliary register is being read."); + } + return gdb_get_reg32(mem_buf, regval); +} + + +static int +arc_aux_minimal_gdb_set_reg(CPUARCState *env, uint8_t *mem_buf, int regnum) +{ + /* TODO: processor type must be set according to configuration */ + static const int processor =3D ARC_OPCODE_ARCv2HS; + uint32_t regval =3D ldl_p(mem_buf); + switch (regnum) { + case GDB_AUX_MIN_REG_PC: + env->pc =3D regval & 0xfffffffe; + break; + case GDB_AUX_MIN_REG_LPS: + helper_sr(env, regval, REG_ADDR(AUX_ID_lp_start, processor)); + break; + case GDB_AUX_MIN_REG_LPE: + helper_sr(env, regval, REG_ADDR(AUX_ID_lp_end, processor)); + break; + case GDB_AUX_MIN_REG_STATUS: + unpack_status32(&env->stat, regval); + break; + default: + assert(!"Unsupported minimal auxiliary register is being written."= ); + } + return 4; +} + + +static int +arc_aux_other_gdb_get_reg(CPUARCState *env, GByteArray *mem_buf, int regnu= m) +{ + /* TODO: processor type must be set according to configuration */ + static const int processor =3D ARC_OPCODE_ARCv2HS; + uint32_t regval =3D 0; + switch (regnum) { + case GDB_AUX_OTHER_REG_TIMER_BUILD: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_timer_build, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_BUILD: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_irq_build, processor)); + break; + case GDB_AUX_OTHER_REG_MPY_BUILD: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_mpy_build, processor)); + break; + case GDB_AUX_OTHER_REG_VECBASE_BUILD: + regval =3D env->vecbase_build; + break; + case GDB_AUX_OTHER_REG_ISA_CONFIG: + regval =3D env->isa_config; + break; + case GDB_AUX_OTHER_REG_TIMER_CNT0: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_count0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CTRL0: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_control0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_LIM0: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_limit0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CNT1: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_count1, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CTRL1: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_control1, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_LIM1: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_limit1, processor)); + break; + case GDB_AUX_OTHER_REG_PID: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_pid, processor)); + break; + case GDB_AUX_OTHER_REG_TLBPD0: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_tlbpd0, processor)); + break; + case GDB_AUX_OTHER_REG_TLBPD1: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_tlbpd1, processor)); + break; + case GDB_AUX_OTHER_REG_TLB_INDEX: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_tlbindex, processor)); + break; + case GDB_AUX_OTHER_REG_TLB_CMD: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_tlbcommand, processor)); + break; + /* MPU */ + case GDB_AUX_OTHER_REG_MPU_BUILD: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_mpu_build, processor)); + break; + case GDB_AUX_OTHER_REG_MPU_EN: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_mpuen, processor)); + break; + case GDB_AUX_OTHER_REG_MPU_ECR: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_mpuic, processor)); + break; + case GDB_AUX_OTHER_REG_MPU_BASE0 ... GDB_AUX_OTHER_REG_MPU_BASE15: { + const uint8_t index =3D regnum - GDB_AUX_OTHER_REG_MPU_BASE0; + regval =3D helper_lr(env, REG_ADDR(AUX_ID_mpurdb0 + index, process= or)); + break; + } + case GDB_AUX_OTHER_REG_MPU_PERM0 ... GDB_AUX_OTHER_REG_MPU_PERM15: { + const uint8_t index =3D regnum - GDB_AUX_OTHER_REG_MPU_PERM0; + regval =3D helper_lr(env, REG_ADDR(AUX_ID_mpurdp0 + index, process= or)); + break; + } + /* exceptions */ + case GDB_AUX_OTHER_REG_ERSTATUS: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_erstatus, processor)); + break; + case GDB_AUX_OTHER_REG_ERBTA: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_erbta, processor)); + break; + case GDB_AUX_OTHER_REG_ECR: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_ecr, processor)); + break; + case GDB_AUX_OTHER_REG_ERET: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_eret, processor)); + break; + case GDB_AUX_OTHER_REG_EFA: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_efa, processor)); + break; + /* interrupt */ + case GDB_AUX_OTHER_REG_ICAUSE: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_icause, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_CTRL: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_aux_irq_ctrl, processor)= ); + break; + case GDB_AUX_OTHER_REG_IRQ_ACT: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_aux_irq_act, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_PRIO_PEND: + regval =3D env->irq_priority_pending; + break; + case GDB_AUX_OTHER_REG_IRQ_HINT: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_aux_irq_hint, processor)= ); + break; + case GDB_AUX_OTHER_REG_IRQ_SELECT: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_irq_select, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_ENABLE: + regval =3D env->irq_bank[env->irq_select & 0xff].enable; + break; + case GDB_AUX_OTHER_REG_IRQ_TRIGGER: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_irq_trigger, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_STATUS: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_irq_status, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_PULSE: + regval =3D 0; /* write only for clearing the pulse triggered inter= rupt */ + break; + case GDB_AUX_OTHER_REG_IRQ_PENDING: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_irq_pending, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_PRIO: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_irq_priority, processor)= ); + break; + case GDB_AUX_OTHER_REG_BTA: + regval =3D helper_lr(env, REG_ADDR(AUX_ID_bta, processor)); + break; + default: + assert(!"Unsupported other auxiliary register is being read."); + } + return gdb_get_reg32(mem_buf, regval); +} + + +static int +arc_aux_other_gdb_set_reg(CPUARCState *env, uint8_t *mem_buf, int regnum) +{ + /* TODO: processor type must be set according to configuration */ + static const int processor =3D ARC_OPCODE_ARCv2HS; + uint32_t regval =3D ldl_p(mem_buf); + switch (regnum) { + case GDB_AUX_OTHER_REG_TIMER_BUILD: + case GDB_AUX_OTHER_REG_IRQ_BUILD: + case GDB_AUX_OTHER_REG_MPY_BUILD: + case GDB_AUX_OTHER_REG_VECBASE_BUILD: + case GDB_AUX_OTHER_REG_ISA_CONFIG: + case GDB_AUX_OTHER_REG_MPU_BUILD: + case GDB_AUX_OTHER_REG_MPU_ECR: + case GDB_AUX_OTHER_REG_ICAUSE: + case GDB_AUX_OTHER_REG_IRQ_PRIO_PEND: + case GDB_AUX_OTHER_REG_IRQ_STATUS: + case GDB_AUX_OTHER_REG_IRQ_PENDING: + /* builds/configs/exceptions/irqs cannot be changed */ + break; + case GDB_AUX_OTHER_REG_TIMER_CNT0: + helper_sr(env, regval, REG_ADDR(AUX_ID_count0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CTRL0: + helper_sr(env, regval, REG_ADDR(AUX_ID_control0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_LIM0: + helper_sr(env, regval, REG_ADDR(AUX_ID_limit0, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CNT1: + helper_sr(env, regval, REG_ADDR(AUX_ID_count1, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_CTRL1: + helper_sr(env, regval, REG_ADDR(AUX_ID_control1, processor)); + break; + case GDB_AUX_OTHER_REG_TIMER_LIM1: + helper_sr(env, regval, REG_ADDR(AUX_ID_limit1, processor)); + break; + case GDB_AUX_OTHER_REG_PID: + helper_sr(env, regval, REG_ADDR(AUX_ID_pid, processor)); + break; + case GDB_AUX_OTHER_REG_TLBPD0: + helper_sr(env, regval, REG_ADDR(AUX_ID_tlbpd0, processor)); + break; + case GDB_AUX_OTHER_REG_TLBPD1: + helper_sr(env, regval, REG_ADDR(AUX_ID_tlbpd1, processor)); + break; + case GDB_AUX_OTHER_REG_TLB_INDEX: + helper_sr(env, regval, REG_ADDR(AUX_ID_tlbindex, processor)); + break; + case GDB_AUX_OTHER_REG_TLB_CMD: + helper_sr(env, regval, REG_ADDR(AUX_ID_tlbcommand, processor)); + break; + /* MPU */ + case GDB_AUX_OTHER_REG_MPU_EN: + helper_sr(env, regval, REG_ADDR(AUX_ID_mpuen, processor)); + break; + case GDB_AUX_OTHER_REG_MPU_BASE0 ... GDB_AUX_OTHER_REG_MPU_BASE15: { + const uint8_t index =3D regnum - GDB_AUX_OTHER_REG_MPU_BASE0; + helper_sr(env, regval, REG_ADDR(AUX_ID_mpurdb0 + index, processor)= ); + break; + } + case GDB_AUX_OTHER_REG_MPU_PERM0 ... GDB_AUX_OTHER_REG_MPU_PERM15: { + const uint8_t index =3D regnum - GDB_AUX_OTHER_REG_MPU_PERM0; + helper_sr(env, regval, REG_ADDR(AUX_ID_mpurdp0 + index, processor)= ); + break; + } + /* exceptions */ + case GDB_AUX_OTHER_REG_ERSTATUS: + helper_sr(env, regval, REG_ADDR(AUX_ID_erstatus, processor)); + break; + case GDB_AUX_OTHER_REG_ERBTA: + helper_sr(env, regval, REG_ADDR(AUX_ID_erbta, processor)); + break; + case GDB_AUX_OTHER_REG_ECR: + helper_sr(env, regval, REG_ADDR(AUX_ID_ecr, processor)); + break; + case GDB_AUX_OTHER_REG_ERET: + helper_sr(env, regval, REG_ADDR(AUX_ID_eret, processor)); + break; + case GDB_AUX_OTHER_REG_EFA: + helper_sr(env, regval, REG_ADDR(AUX_ID_efa, processor)); + break; + /* interrupt */ + case GDB_AUX_OTHER_REG_IRQ_CTRL: + helper_sr(env, regval, REG_ADDR(AUX_ID_aux_irq_ctrl, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_ACT: + helper_sr(env, regval, REG_ADDR(AUX_ID_aux_irq_act, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_HINT: + helper_sr(env, regval, REG_ADDR(AUX_ID_aux_irq_hint, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_SELECT: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_select, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_ENABLE: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_enable, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_TRIGGER: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_trigger, processor)); + break; + case GDB_AUX_OTHER_REG_IRQ_PULSE: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_pulse_cancel, processor= )); + break; + case GDB_AUX_OTHER_REG_IRQ_PRIO: + helper_sr(env, regval, REG_ADDR(AUX_ID_irq_priority, processor)); + break; + case GDB_AUX_OTHER_REG_BTA: + helper_sr(env, regval, REG_ADDR(AUX_ID_bta, processor)); + break; + default: + assert(!"Unsupported other auxiliary register is being written."); + } + return 4; +} + + +void arc_cpu_register_gdb_regs_for_features(ARCCPU *cpu) +{ + CPUState *cs =3D CPU(cpu); + + gdb_register_coprocessor(cs, + arc_aux_minimal_gdb_get_reg, /* getter */ + arc_aux_minimal_gdb_set_reg, /* setter */ + GDB_AUX_MIN_REG_LAST, /* number of reg= isters */ + "arc-v2-aux.xml", /* feature file = */ + 0); /* position in g= packet */ + + gdb_register_coprocessor(cs, + arc_aux_other_gdb_get_reg, + arc_aux_other_gdb_set_reg, + GDB_AUX_OTHER_REG_LAST, + "arc-v2-other.xml", + 0); +} + +/*-*-indent-tabs-mode:nil;tab-width:4;indent-line-function:'insert-tab'-*-= */ +/* vim: set ts=3D4 sw=3D4 et: */ --=20 2.20.1