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[2.80.104.46]) by smtp.gmail.com with ESMTPSA id s188sm3115178wmf.45.2020.11.11.08.18.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 08:18:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0dH6iTiEiDaNoVcjOK9D9d222s0bNd7S/gGGqMEYyFE=; b=V9hJ4RhQdkFJZd0BfiZKdKHcw4a9wKTD+qt3RJdxmr8FZdBliBHCfYRUnHuMfEztf2 AVarpDwo/VjsZCgmizmWvEvdZuViNjYgoZ3JVm4T4WRvl7Vtk4ZJWBgZj2DxmL6SzJ6x 66ymR+p8qZYcSTP/X/MP2wnwMothRJcHS8fivfvXbwGG251bLgdk2bEpxNUZtfGDxD6U tKTsZ20efZDK6UzyObMlteqqWu7Mel7d4OpduSk94DLgulnbpuWFX53MIcvycSg/je2R 9wgIye1jB9cXpkIcC9gd3FSDZML5SjUEurQC0ytdmZ1fbuZ8JSnJOhSJeIMnotuAmesy gd2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0dH6iTiEiDaNoVcjOK9D9d222s0bNd7S/gGGqMEYyFE=; b=Jk5Fh+cBewPQTu7ykt2vA1sVafXPaUKFb16Lge5NduDElenGULhohh0/ktvQdmcCRd rg/d9CoZlOyOf00BXjzUvKY2120tyKT7M95Bc28Wcyw/pu+pfeH9S//PjILiF2cvmLeG w5r9BvjCuOEK/4yM9uFcVPyTnNZbfA6bqTe4E2Hjtas+xVnaE2z1zPTwMbLuwu0rSCPb v34Z/f0JKCu2ecro3Yc3mDPzgxL7D4s1UnHP7rYViPZAbN7RPHsWnv4jM6gwucOmeVRE lkhKjDHPeu9Iu/pueJotJMmLHe4kwudhq1LL7kHfnMvFNHjVSmOIy0F5nEtf29eF4HHD Na3w== X-Gm-Message-State: AOAM532AUYalE3UfXWfKGCZQFDFEZoDNRtIgR2IjxKdmbjcv7abhRPE7 8/UnSGMLL+LVDREJ70w6Bttzq3ve0w0g+Q== X-Google-Smtp-Source: ABdhPJwu9Aj8Sh1SZJHfOth73U6AOQtU02QtB5FI99Uup8lLi6aF41ih343QGw+9G6X6brfwtPl22w== X-Received: by 2002:adf:ead0:: with SMTP id o16mr32612013wrn.292.1605111497519; Wed, 11 Nov 2020 08:18:17 -0800 (PST) From: cupertinomiranda@gmail.com To: qemu-devel@nongnu.org Subject: [PATCH 09/15] arc: Add memory management unit (MMU) support Date: Wed, 11 Nov 2020 16:17:52 +0000 Message-Id: <20201111161758.9636-10-cupertinomiranda@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201111161758.9636-1-cupertinomiranda@gmail.com> References: <20201111161758.9636-1-cupertinomiranda@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=cupertinomiranda@gmail.com; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Claudiu Zissulescu , Cupertino Miranda , Shahab Vahedi , Shahab Vahedi , Cupertino Miranda , linux-snps-arc@lists.infradead.org, Claudiu Zissulescu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Cupertino Miranda Add Synopsys ARC MMU version 4 support. The implementation is restricted to 8K page size support. Signed-off-by: Cupertino Miranda --- target/arc/mmu.c | 777 +++++++++++++++++++++++++++++++++++++++++++++++ target/arc/mmu.h | 166 ++++++++++ 2 files changed, 943 insertions(+) create mode 100644 target/arc/mmu.c create mode 100644 target/arc/mmu.h diff --git a/target/arc/mmu.c b/target/arc/mmu.c new file mode 100644 index 0000000000..3d50489b15 --- /dev/null +++ b/target/arc/mmu.c @@ -0,0 +1,777 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * Contributed by Cupertino Miranda + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#include "qemu/osdep.h" +#include "mmu.h" +#include "target/arc/regs.h" +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" + + +uint32_t +arc_mmu_aux_get(const struct arc_aux_reg_detail *aux_reg_detail, void *dat= a) +{ + CPUARCState *env =3D (CPUARCState *) data; + struct arc_mmu *mmu =3D &env->mmu; + uint32_t reg =3D 0; + + switch (aux_reg_detail->id) { + case AUX_ID_mmu_build: + /* + * For now hardcode the TLB geometry and canonical page sizes + * MMUv4: 2M Super Page, 8k Page, 4 way set associative, + * 1K entries (256x4), 4 uITLB, 8 uDTLB + */ + reg =3D 0x04e21a4a; + break; + case AUX_ID_tlbindex: + reg =3D mmu->tlbindex; + break; + case AUX_ID_tlbpd0: + reg =3D mmu->tlbpd0; + break; + case AUX_ID_tlbpd1: + reg =3D mmu->tlbpd1; + break; + case AUX_ID_tlbpd1_hi: + reg =3D mmu->tlbpd1_hi; + break; + case AUX_ID_scratch_data0: + reg =3D mmu->scratch_data0; + break; + case AUX_ID_tlbcommand: + reg =3D mmu->tlbcmd; + break; + case AUX_ID_pid: + reg =3D (mmu->enabled << 31) | mmu->pid_asid; + break; + case AUX_ID_sasid0: + reg =3D mmu->sasid0; + break; + case AUX_ID_sasid1: + reg =3D mmu->sasid1; + break; + default: + break; + } + + return reg; +} + +void +arc_mmu_aux_set(const struct arc_aux_reg_detail *aux_reg_detail, + uint32_t val, void *data) +{ + CPUARCState *env =3D (CPUARCState *) data; + CPUState *cs =3D env_cpu(env); + struct arc_mmu *mmu =3D &env->mmu; + + switch (aux_reg_detail->id) { + /* AUX_ID_tlbcommand is more involved and handled seperately */ + case AUX_ID_tlbindex: + mmu->tlbindex =3D val; + break; + case AUX_ID_tlbpd0: + mmu->tlbpd0 =3D val; + break; + case AUX_ID_tlbpd1: + mmu->tlbpd1 =3D val; + break; + case AUX_ID_tlbpd1_hi: + mmu->tlbpd1_hi =3D val; + break; + case AUX_ID_scratch_data0: + mmu->scratch_data0 =3D val; + break; + case AUX_ID_pid: + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Writing PID_ASID with value 0x%08x at 0x%08x\= n", + val, env->pc); + mmu->enabled =3D (val >> 31); + mmu->pid_asid =3D val & 0xff; + tlb_flush(cs); + break; + case AUX_ID_sasid0: + mmu->sasid0 =3D val; + break; + case AUX_ID_sasid1: + mmu->sasid1 =3D val; + break; + default: + break; + } +} + +/* vaddr can't have top bit */ +#define VPN(addr) ((addr) & (PAGE_MASK & (~0x80000000))) +#define PFN(addr) ((addr) & PAGE_MASK) + +static void +arc_mmu_debug_tlb_for_set(CPUARCState *env, int set) +{ + int j; + bool set_printed =3D false; + + for (j =3D 0; j < N_WAYS; j++) { + struct arc_tlb_e *tlb =3D &env->mmu.nTLB[set][j]; + + if ((tlb->pd0 & PD0_V) !=3D 0) { + if (set_printed =3D=3D false) { + printf("set %d\n", set); + set_printed =3D true; + } + if (set_printed =3D=3D true) { + printf(" way %d\n", j); + } + printf(" tlppd0: %08x: vaddr=3D\t%08x %s %s%s asid=3D%02x\n", + (unsigned int) tlb->pd0, (unsigned int) VPN(tlb->pd0), + (char *) ((tlb->pd0 & PD0_SZ) !=3D 0 ? "sz1" : "sz0"), + (char *) ((tlb->pd0 & PD0_V) !=3D 0 ? "V" : ""), + (char *) ((tlb->pd0 & PD0_G) !=3D 0 ? "g" : ""), + tlb->pd0 & PD0_ASID); + + printf(" tlppd1: %08x: paddr=3D\t%08x k:%s%s%s u:%s%s%s f:%s\= n", + (unsigned int) tlb->pd1, (unsigned int) PFN(tlb->pd1), + (char *) ((tlb->pd1 & PD1_RK) !=3D 0 ? "R" : "r"), + (char *) ((tlb->pd1 & PD1_WK) !=3D 0 ? "W" : "w"), + (char *) ((tlb->pd1 & PD1_XK) !=3D 0 ? "X" : "x"), + (char *) ((tlb->pd1 & PD1_RU) !=3D 0 ? "R" : "r"), + (char *) ((tlb->pd1 & PD1_WU) !=3D 0 ? "W" : "w"), + (char *) ((tlb->pd1 & PD1_XU) !=3D 0 ? "X" : "x"), + (char *) ((tlb->pd1 & PD1_FC) !=3D 0 ? "C" : "c")); + } + } +} + +void +arc_mmu_debug_tlb(CPUARCState *env) +{ + int i; + + for (i =3D 0; i < N_SETS; i++) { + arc_mmu_debug_tlb_for_set(env, i); + } +} + +void +arc_mmu_debug_tlb_for_vaddr(CPUARCState *env, uint32_t vaddr) +{ + uint32_t set =3D (vaddr >> PAGE_SHIFT) & (N_SETS - 1); + arc_mmu_debug_tlb_for_set(env, set); +} + + +static struct arc_tlb_e * +arc_mmu_get_tlb_at_index(uint32_t index, struct arc_mmu *mmu) +{ + uint32_t set =3D index / N_WAYS; + uint32_t bank =3D index % N_WAYS; + return &mmu->nTLB[set][bank]; +} + +static inline bool +match_sasid(struct arc_tlb_e *tlb, struct arc_mmu *mmu) +{ + /* Match to a shared library. */ + uint8_t position =3D tlb->pd0 & PD0_ASID_MATCH; + uint64_t pos =3D 1ULL << position; + uint64_t sasid =3D ((uint64_t) mmu->sasid1 << 32) | mmu->sasid0; + if ((pos & sasid) =3D=3D 0) { + return false; + } + return true; +} + +static struct arc_tlb_e * +arc_mmu_lookup_tlb(uint32_t vaddr, uint32_t compare_mask, struct arc_mmu *= mmu, + int *num_finds, uint32_t *index) +{ + struct arc_tlb_e *ret =3D NULL; + uint32_t set =3D (vaddr >> PAGE_SHIFT) & (N_SETS - 1); + struct arc_tlb_e *tlb =3D &mmu->nTLB[set][0]; + int w; + + if (num_finds !=3D NULL) { + *num_finds =3D 0; + } + + bool general_match =3D true; + for (w =3D 0; w < N_WAYS; w++, tlb++) { + uint32_t match =3D vaddr & compare_mask; + uint32_t final_compare_mask =3D compare_mask; + + if ((tlb->pd0 & PD0_G) =3D=3D 0) { + if ((tlb->pd0 & PD0_S) !=3D 0) { + /* Match to a shared library. */ + if (match_sasid(tlb, mmu) =3D=3D false) { + general_match =3D false; + } + } else { + /* Match to a process. */ + match |=3D mmu->pid_asid & PD0_PID_MATCH; + final_compare_mask |=3D PD0_PID_MATCH; + } + } + + if (match =3D=3D (tlb->pd0 & final_compare_mask) && general_match)= { + ret =3D tlb; + if (num_finds !=3D NULL) { + *num_finds +=3D 1; + } + if (index !=3D NULL) { + *index =3D (set * N_WAYS) + w; + } + } + } + + if (ret =3D=3D NULL) { + uint32_t way =3D mmu->way_sel[set]; + ret =3D &mmu->nTLB[set][way]; + + /* TODO: Replace by something more significant. */ + if (index !=3D NULL) { + *index =3D (set * N_WAYS) + way; + } + + mmu->way_sel[set] =3D (mmu->way_sel[set] + 1) & (N_WAYS - 1); + } + + return ret; +} + +/* + * TLB Insert/Delete triggered by writing the cmd to TLBCommand Aux + * - Requires PD0 and PD1 be setup apriori + */ +void +arc_mmu_aux_set_tlbcmd(const struct arc_aux_reg_detail *aux_reg_detail, + uint32_t val, void *data) +{ + CPUARCState *env =3D (CPUARCState *) data; + CPUState *cs =3D env_cpu(env); + struct arc_mmu *mmu =3D &env->mmu; + uint32_t pd0 =3D mmu->tlbpd0; + uint32_t pd1 =3D mmu->tlbpd1; + int num_finds =3D 4; + uint32_t index; + struct arc_tlb_e *tlb; + + mmu->tlbcmd =3D val; + uint32_t matching_mask =3D (PD0_VPN | PD0_SZ | PD0_G | PD0_S | PD0_ASI= D); + + if ((pd0 & PD0_G) !=3D 0) { + /* + * When Global do not check for asid match. + */ + matching_mask &=3D ~(PD0_S | PD0_ASID); + } + + /* + * NOTE: Write and WriteNI commands are the same because we do not mod= el + * uTLBs in QEMU. + */ + if (val =3D=3D TLB_CMD_WRITE || val =3D=3D TLB_CMD_WRITENI) { + /* + * TODO: Include index verification. We are always clearing the in= dex as + * we assume it is always valid. + */ + tlb =3D arc_mmu_get_tlb_at_index(mmu->tlbindex & TLBINDEX_INDEX, m= mu); + tlb->pd0 =3D mmu->tlbpd0; + tlb->pd1 =3D mmu->tlbpd1; + } + if (val =3D=3D TLB_CMD_READ) { + /* + * TODO: Include index verification. We are always clearing the in= dex as + * we assume it is always valid. + */ + + tlb =3D arc_mmu_get_tlb_at_index(mmu->tlbindex & TLBINDEX_INDEX, m= mu); + mmu->tlbpd0 =3D tlb->pd0; + mmu->tlbpd1 =3D tlb->pd1; + + mmu->tlbindex &=3D ~(TLBINDEX_E | TLBINDEX_RC); + } + if (val =3D=3D TLB_CMD_DELETE || val =3D=3D TLB_CMD_INSERT) { + tlb_flush_page_by_mmuidx(cs, VPN(pd0), 3); + + if ((pd0 & PD0_G) !=3D 0) { + /* + * When Global do not check for asid match. + */ + matching_mask &=3D ~(PD0_S | PD0_ASID); + } + + matching_mask &=3D (VPN(PD0_VPN) | (~PD0_VPN)) ; + tlb =3D arc_mmu_lookup_tlb(pd0, + matching_mask | PD0_V, + &env->mmu, &num_finds, &index); + + if (num_finds =3D=3D 0) { + mmu->tlbindex =3D 0x80000000; /* No entry to delete */ + } else if (num_finds =3D=3D 1) { + mmu->tlbindex =3D index; /* Entry is deleted set index */ + tlb->pd0 &=3D ~PD0_V; + num_finds--; + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Delete at 0x%08x, pd0 =3D 0x%08x, pd1 =3D= 0x%08x\n", + env->pc, tlb->pd0, tlb->pd1); + } else { + while (num_finds > 0) { + tlb->pd0 &=3D ~PD0_V; + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Delete at 0x%08x, pd0 =3D 0x%08x, pd1= =3D 0x%08x\n", + env->pc, tlb->pd0, tlb->pd1); + tlb =3D arc_mmu_lookup_tlb(pd0, + (VPN(PD0_VPN) | PD0_V + | PD0_SZ | PD0_G | PD0_S), + mmu, &num_finds, NULL); + } + } + } + + if (val =3D=3D TLB_CMD_INSERT) { + if ((pd0 & PD0_V) =3D=3D 0) { + mmu->tlbindex =3D 0x80000000; + } else { + tlb->pd0 =3D pd0; + tlb->pd1 =3D pd1; + + /* Set index for latest inserted element. */ + mmu->tlbindex |=3D index; + + /* TODO: More verifications needed. */ + + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Insert at 0x%08x, PID =3D %d, VPN =3D 0x%= 08x, " + "PFN =3D 0x%08x, pd0 =3D 0x%08x, pd1 =3D 0x%08x\= n", + env->pc, + pd0 & 0xff, + VPN(pd0), PFN(pd1), + pd0, pd1); + } + } + + /* NOTE: We do not implement IVUTLB as we do not model uTLBs. */ + assert(val =3D=3D TLB_CMD_INSERT + || val =3D=3D TLB_CMD_DELETE + || val =3D=3D TLB_CMD_WRITE + || val =3D=3D TLB_CMD_READ + || val =3D=3D TLB_CMD_WRITENI + || val =3D=3D TLB_CMD_IVUTLB + ); +} + +/* Function to verify if we have permission to use MMU TLB entry. */ +static bool +arc_mmu_have_permission(CPUARCState *env, + struct arc_tlb_e *tlb, + enum mmu_access_type type) +{ + bool ret =3D false; + bool in_kernel_mode =3D !env->stat.Uf; /* Read status for user mode. */ + switch (type) { + case MMU_MEM_READ: + ret =3D in_kernel_mode ? tlb->pd1 & PD1_RK : tlb->pd1 & PD1_RU; + break; + case MMU_MEM_WRITE: + ret =3D in_kernel_mode ? tlb->pd1 & PD1_WK : tlb->pd1 & PD1_WU; + break; + case MMU_MEM_FETCH: + ret =3D in_kernel_mode ? tlb->pd1 & PD1_XK : tlb->pd1 & PD1_XU; + break; + case MMU_MEM_ATTOMIC: + ret =3D in_kernel_mode ? tlb->pd1 & PD1_RK : tlb->pd1 & PD1_RU; + ret =3D ret & (in_kernel_mode ? tlb->pd1 & PD1_WK : tlb->pd1 & PD1= _WU); + break; + case MMU_MEM_IRRELEVANT_TYPE: + ret =3D true; + break; + } + + return ret; +} + +#define SET_MMU_EXCEPTION(ENV, N, C, P) { \ + ENV->mmu.exception.number =3D N; \ + ENV->mmu.exception.causecode =3D C; \ + ENV->mmu.exception.parameter =3D P; \ +} + +/* Translation function to get physical address from virtual address. */ +uint32_t +arc_mmu_translate(struct CPUARCState *env, + uint32_t vaddr, enum mmu_access_type rwe, + uint32_t *index) +{ + struct arc_mmu *mmu =3D &(env->mmu); + struct arc_tlb_e *tlb =3D NULL; + int num_matching_tlb =3D 0; + + SET_MMU_EXCEPTION(env, EXCP_NO_EXCEPTION, 0, 0); + + if (rwe !=3D MMU_MEM_IRRELEVANT_TYPE + && env->stat.Uf !=3D 0 && vaddr >=3D 0x80000000) { + goto protv_exception; + } + + /* + * Check that we are not addressing an address above 0x80000000. + * Return the same address in that case. + */ + if ((vaddr >=3D 0x80000000) || mmu->enabled =3D=3D false) { + return vaddr; + } + + if (rwe !=3D MMU_MEM_IRRELEVANT_TYPE) { + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Translate at 0x%08x, vaddr 0x%08x, pid %d, rw= e =3D %s\n", + env->pc, vaddr, mmu->pid_asid, RWE_STRING(rwe)); + } + + uint32_t match_pd0 =3D (VPN(vaddr) | PD0_V); + tlb =3D arc_mmu_lookup_tlb(match_pd0, (VPN(PD0_VPN) | PD0_V), mmu, + &num_matching_tlb, index); + + /* + * Check for multiple matches in nTLB, and return machine check + * exception. + */ + if (num_matching_tlb > 1) { + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Machine Check exception. num_matching_tlb =3D= %d\n", + num_matching_tlb); + SET_MMU_EXCEPTION(env, EXCP_MACHINE_CHECK, 0x01, 0x00); + return 0; + } + + + bool match =3D true; + + if (num_matching_tlb =3D=3D 0) { + match =3D false; + } + + /* Check if entry if related to this address */ + if (VPN(vaddr) !=3D VPN(tlb->pd0) || (tlb->pd0 & PD0_V) =3D=3D 0) { + /* Call the interrupt. */ + match =3D false; + } + + if (match =3D=3D true) { + if ((tlb->pd0 & PD0_G) =3D=3D 0) { + if ((tlb->pd0 & PD0_S) !=3D 0) { + /* Match to a shared library. */ + if (match_sasid(tlb, mmu) =3D=3D false) { + match =3D false; + } + } else if ((tlb->pd0 & PD0_PID_MATCH) !=3D + (mmu->pid_asid & PD0_PID_MATCH)) { + /* Match to a process. */ + match =3D false; + } + } + } + + if (match =3D=3D true && !arc_mmu_have_permission(env, tlb, rwe)) { + protv_exception: + qemu_log_mask(CPU_LOG_MMU, + "[MMU] ProtV exception at 0x%08x for 0x%08x. rwe =3D= %s, " + "tlb->pd0 =3D %08x, tlb->pd1 =3D %08x\n", + env->pc, + vaddr, + RWE_STRING(rwe), + tlb->pd0, tlb->pd1); + + SET_MMU_EXCEPTION(env, EXCP_PROTV, CAUSE_CODE(rwe), 0x08); + return 0; + } + + if (match =3D=3D true) { + if (rwe !=3D MMU_MEM_IRRELEVANT_TYPE) { + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Translated to 0x%08x, pd0=3D0x%08x, pd1= =3D0x%08x\n", + (tlb->pd1 & PAGE_MASK) | (vaddr & (~PAGE_MASK)), + tlb->pd0, tlb->pd1); + } + return (tlb->pd1 & PAGE_MASK) | (vaddr & (~PAGE_MASK)); + } else { + if (rwe !=3D MMU_MEM_IRRELEVANT_TYPE) { + /* To remove eventually, just fail safe to check kernel. */ + if (mmu->sasid0 !=3D 0 || mmu->sasid1 !=3D 0) { + assert(0); + } else { + mmu->tlbpd0 =3D (vaddr & (VPN(PD0_VPN))) + | PD0_V | (mmu->pid_asid & PD0_ASID); + } + if (rwe =3D=3D MMU_MEM_FETCH) { + qemu_log_mask(CPU_LOG_MMU, + "[MMU] TLB_MissI exception at 0x%08x. rwe = =3D %s, " + "vaddr =3D %08x, tlb->pd0 =3D %08x, tlb->pd1= =3D %08x\n", + env->pc, + RWE_STRING(rwe), + vaddr, tlb->pd0, tlb->pd1); + SET_MMU_EXCEPTION(env, EXCP_TLB_MISS_I, 0x00, 0x00); + } else { + qemu_log_mask(CPU_LOG_MMU, + "[MMU] TLB_MissD exception at 0x%08x. rwe = =3D %s, " + "vaddr =3D %08x, tlb->pd0 =3D %08x, tlb->pd1= =3D %08x\n", + env->pc, + RWE_STRING(rwe), + vaddr, tlb->pd0, tlb->pd1); + SET_MMU_EXCEPTION(env, EXCP_TLB_MISS_D, CAUSE_CODE(rwe), + 0x00); + } + } else if (rwe !=3D MMU_MEM_IRRELEVANT_TYPE) { + qemu_log_mask(CPU_LOG_MMU, + "[MMU] Failed to translate to 0x%08x\n", + vaddr); + } + return 0; + } +} + +uint32_t arc_mmu_page_address_for(uint32_t vaddr) +{ + uint32_t ret =3D VPN(vaddr); + if (vaddr >=3D 0x80000000) { + ret |=3D 0x80000000; + } + return ret; +} + +void arc_mmu_init(struct arc_mmu *mmu) +{ + mmu->enabled =3D 0; + mmu->pid_asid =3D 0; + mmu->sasid0 =3D 0; + mmu->sasid1 =3D 0; + + mmu->tlbpd0 =3D 0; + mmu->tlbpd1 =3D 0; + mmu->tlbpd1_hi =3D 0; + mmu->tlbindex =3D 0; + mmu->tlbcmd =3D 0; + mmu->scratch_data0 =3D 0; + + memset(mmu->nTLB, 0, sizeof(mmu->nTLB)); +} + +static int +arc_mmu_get_prot_for_index(uint32_t index, CPUARCState *env) +{ + struct arc_tlb_e *tlb; + int ret =3D 0; + bool in_kernel_mode =3D !env->stat.Uf; /* Read status for user mode. */ + + tlb =3D arc_mmu_get_tlb_at_index( + index, + &env->mmu); + + if ((in_kernel_mode && (tlb->pd1 & PD1_RK) !=3D 0) + || (!in_kernel_mode && (tlb->pd1 & PD1_RU) !=3D 0)) { + ret |=3D PAGE_READ; + } + + if ((in_kernel_mode && (tlb->pd1 & PD1_WK) !=3D 0) + || (!in_kernel_mode && (tlb->pd1 & PD1_WU) !=3D 0)) { + ret |=3D PAGE_WRITE; + } + + if ((in_kernel_mode && (tlb->pd1 & PD1_XK) !=3D 0) + || (!in_kernel_mode && (tlb->pd1 & PD1_XU) !=3D 0)) { + ret |=3D PAGE_EXEC; + } + + return ret; +} + +static void QEMU_NORETURN raise_mem_exception( + CPUState *cs, target_ulong addr, uintptr_t host_pc, + int32_t excp_idx, uint8_t excp_cause_code, uint8_t excp_param) +{ + CPUARCState *env =3D &(ARC_CPU(cs)->env); + if (excp_idx !=3D EXCP_TLB_MISS_I) { + cpu_restore_state(cs, host_pc, true); + } + + env->efa =3D addr; + env->eret =3D env->pc; + env->erbta =3D env->bta; + + cs->exception_index =3D excp_idx; + env->causecode =3D excp_cause_code; + env->param =3D excp_param; + cpu_loop_exit(cs); +} + +/* MMU range */ +static const uint32_t MMU_VA_START =3D 0x00000000; /* inclusive */ +static const uint32_t MMU_VA_END =3D 0x80000000; /* exclusive */ + +typedef enum { + DIRECT_ACTION, + MPU_ACTION, + MMU_ACTION, + EXCEPTION_ACTION +} ACTION; + +/* + * Applying the following logic + * ,-----.-----.-----------.---------.---------------. + * | MMU | MPU | MMU range | mmu_idx | action | + * |-----+-----+-----------+---------+---------------| + * | dis | dis | x | x | phys =3D virt | + * |-----+-----+-----------+---------+---------------| + * | dis | ena | x | x | mpu_translate | + * |-----+-----+-----------+---------+---------------| + * | ena | dis | true | x | mmu_translate | + * |-----+-----+-----------+---------+---------------| + * | ena | dis | false | 0 | phys =3D virt | + * |-----+-----+-----------+---------+---------------| + * | ena | dis | false | 1 | exception | + * |-----+-----+-----------+---------+---------------| + * | ena | ena | false | x | mpu_translate | + * |-----+-----+-----------+---------+---------------| + * | ena | ena | true | x | mmu_translate | + * `-----^-----^-----------^---------^---------------' + */ +static int decide_action(const CPUARCState *env, + target_ulong addr, + int mmu_idx) +{ + static ACTION table[2][2][2][2] =3D { }; + static bool is_initialized =3D false; + const bool is_user =3D (mmu_idx =3D=3D 1); + const bool is_mmu_range =3D ((addr >=3D MMU_VA_START) && (addr < MMU_V= A_END)); + + if (!is_initialized) { + /* Both MMU and MPU disabled */ +#define T true +#define F false + + table[F][F][F][F] =3D DIRECT_ACTION; + table[F][F][F][T] =3D DIRECT_ACTION; + table[F][F][T][F] =3D DIRECT_ACTION; + table[F][F][T][T] =3D DIRECT_ACTION; + + /* Only MPU */ + table[F][T][F][F] =3D MPU_ACTION; + table[F][T][F][T] =3D MPU_ACTION; + table[F][T][T][F] =3D MPU_ACTION; + table[F][T][T][T] =3D MPU_ACTION; + + /* Only MMU; non-mmu range; kernel access */ + table[T][F][F][F] =3D DIRECT_ACTION; + /* Only MMU; non-mmu range; user access */ + table[T][F][F][T] =3D EXCEPTION_ACTION; + + /* Only MMU; mmu range; both modes access */ + table[T][F][T][F] =3D MMU_ACTION; + table[T][F][T][T] =3D MMU_ACTION; + + /* Both MMU and MPU enabled; non-mmu range */ + table[T][T][F][F] =3D MPU_ACTION; + table[T][T][F][T] =3D MPU_ACTION; + + /* Both MMU and MPU enabled; mmu range */ + table[T][T][T][F] =3D MMU_ACTION; + table[T][T][T][T] =3D MMU_ACTION; + +#undef T +#undef F + + is_initialized =3D true; + } + + return table[env->mmu.enabled][env->mpu.enabled][is_mmu_range][is_user= ]; +} + + +#ifndef CONFIG_USER_ONLY +/* Softmmu support function for MMU. */ +bool arc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + /* TODO: this rwe should go away when the TODO below is done */ + enum mmu_access_type rwe =3D (char) access_type; + CPUARCState *env =3D &((ARC_CPU(cs))->env); + int action =3D decide_action(env, address, mmu_idx); + + switch (action) { + case DIRECT_ACTION: + tlb_set_page(cs, address & PAGE_MASK, address & PAGE_MASK, + PAGE_READ | PAGE_WRITE | PAGE_EXEC, + mmu_idx, TARGET_PAGE_SIZE); + break; + case MPU_ACTION: + if (arc_mpu_translate(env, address, access_type, mmu_idx)) { + if (probe) { + return false; + } + MPUException *mpu_excp =3D &env->mpu.exception; + raise_mem_exception(cs, address, retaddr, + mpu_excp->number, mpu_excp->code, mpu_excp->param); + } + break; + case MMU_ACTION: { + /* + * TODO: these lines must go inside arc_mmu_translate and it + * should only signal a failure or success --> generate an + * exception or not + */ + uint32_t index; + target_ulong paddr =3D arc_mmu_translate(env, address, rwe, &index= ); + if ((enum exception_code_list) env->mmu.exception.number !=3D + EXCP_NO_EXCEPTION) { + if (probe) { + return false; + } + const struct mmu_exception *mmu_excp =3D &env->mmu.exception; + raise_mem_exception(cs, address, retaddr, + mmu_excp->number, mmu_excp->causecode, mmu_excp->param= eter); + } else { + int prot =3D arc_mmu_get_prot_for_index(index, env); + address =3D arc_mmu_page_address_for(address); + tlb_set_page(cs, address, paddr & PAGE_MASK, prot, + mmu_idx, TARGET_PAGE_SIZE); + } + break; + } + case EXCEPTION_ACTION: + if (probe) { + return false; + } + /* TODO: like TODO above, this must move inside mmu */ + qemu_log_mask(CPU_LOG_MMU, "[MMU_TLB_FILL] ProtV " + "exception at 0x%08x. rwe =3D %s\n", + env->pc, RWE_STRING(rwe)); + raise_mem_exception(cs, address, retaddr, + EXCP_PROTV, CAUSE_CODE(rwe), 0x08); + break; + default: + g_assert_not_reached(); + } + + return true; +} +#endif /* ifndef CONFIG_USER_ONLY */ diff --git a/target/arc/mmu.h b/target/arc/mmu.h new file mode 100644 index 0000000000..0afc9af3eb --- /dev/null +++ b/target/arc/mmu.h @@ -0,0 +1,166 @@ +/* + * QEMU ARC CPU + * + * Copyright (c) 2020 Synppsys Inc. + * Contributed by Cupertino Miranda + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * http://www.gnu.org/licenses/lgpl-2.1.html + */ + +#ifndef ARC_MMU_H +#define ARC_MMU_H + +#include "target/arc/regs.h" + +/* PD0 flags */ +#define PD0_VPN 0x7ffff000 +#define PD0_ASID 0x000000ff +#define PD0_G 0x00000100 /* Global */ +#define PD0_V 0x00000200 /* Valid */ +#define PD0_SZ 0x00000400 /* Size: Normal or Super Page */ +#define PD0_L 0x00000800 /* Lock */ +#define PD0_S 0x80000000 /* Shared Library ASID */ +#define PD0_FLG (PD0_G | PD0_V | PD0_SZ | PD0_L) + +#define PD0_ASID_MATCH 0x0000003f +#define PD0_PID_MATCH 0x000000ff + +/* PD1 permission bits */ +#define PD1_PPN 0xfffff000 /* Cached */ +#define PD1_FC 0x00000001 /* Cached */ +#define PD1_XU 0x00000002 /* User Execute */ +#define PD1_WU 0x00000004 /* User Write */ +#define PD1_RU 0x00000008 /* User Read */ +#define PD1_XK 0x00000010 /* Kernel Execute */ +#define PD1_WK 0x00000020 /* Kernel Write */ +#define PD1_RK 0x00000040 /* Kernel Read */ +#define PD1_FLG (PD1_FC | PD1_XU | PD1_WU | PD1_RU | PD1_XK | PD1_WK | PD1= _RK) + +#define TLBINDEX_INDEX 0x00001fff +#define TLBINDEX_E 0x80000000 +#define TLBINDEX_RC 0x70000000 + +#define TLB_CMD_WRITE 0x1 +#define TLB_CMD_WRITENI 0x5 +#define TLB_CMD_READ 0x2 +#define TLB_CMD_INSERT 0x7 +#define TLB_CMD_DELETE 0x8 +#define TLB_CMD_IVUTLB 0x6 + +#define N_SETS 256 +#define N_WAYS 4 +#define TLB_ENTRIES (N_SETS * N_WAYS) + +#define PAGE_SHIFT TARGET_PAGE_BITS +#define PAGE_SIZE (1 << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE - 1)) + +/* NOTE: Do not reorder, this is casted in tbl_fill function. */ +enum mmu_access_type { + MMU_MEM_READ =3D 0, + MMU_MEM_WRITE, + MMU_MEM_FETCH, /* Read for execution. */ + MMU_MEM_ATTOMIC, + MMU_MEM_IRRELEVANT_TYPE, +}; + +#define RWE_STRING(RWE) \ + (RWE =3D=3D MMU_MEM_READ ? "MEM_READ" : \ + (RWE =3D=3D MMU_MEM_WRITE ? "MEM_WRITE" : \ + (RWE =3D=3D MMU_MEM_ATTOMIC ? "MEM_ATTOMIC" : \ + (RWE =3D=3D MMU_MEM_FETCH ? "MEM_FETCH" : \ + (RWE =3D=3D MMU_MEM_IRRELEVANT_TYPE ? "MEM_IRRELEVANT" \ + : "NOT_VALID_RWE"))))) + + +#define CAUSE_CODE(ENUM) \ + ((ENUM =3D=3D MMU_MEM_FETCH) ? 0 : \ + ((ENUM =3D=3D MMU_MEM_READ) ? 1 : \ + ((ENUM =3D=3D MMU_MEM_WRITE) ? 2 : 3))) + + +struct arc_tlb_e { + /* + * TLB entry is {PD0,PD1} tuple, kept "unpacked" to avoid bit fiddling + * flags includes both PD0 flags and PD1 permissions. + */ + uint32_t pd0, pd1; +}; + +#define RAISE_MMU_EXCEPTION(ENV) { \ + do_exception_no_delayslot(ENV, \ + ENV->mmu.exception.number, \ + ENV->mmu.exception.causecode, \ + ENV->mmu.exception.parameter); \ +} + +struct arc_mmu { + uint32_t enabled; + struct mmu_exception { + int32_t number; + uint8_t causecode; + uint8_t parameter; + } exception; + + struct arc_tlb_e nTLB[N_SETS][N_WAYS]; + + /* insert uses vaddr to find set; way selection could be random/rr/lru= */ + uint32_t way_sel[N_SETS]; + + /* + * Current Address Space ID (in whose context mmu lookups done) + * Note that it is actually present in AUX PID reg, which we don't + * explicitly maintain, but {re,de}construct as needed by LR/SR insns + * respectively. + */ + uint32_t pid_asid; + uint32_t sasid0; + uint32_t sasid1; + + uint32_t tlbpd0; + uint32_t tlbpd1; + uint32_t tlbpd1_hi; + uint32_t tlbindex; + uint32_t tlbcmd; + uint32_t scratch_data0; +}; + + +struct CPUARCState; + + +extern void +arc_mmu_aux_set_tlbcmd(const struct arc_aux_reg_detail *aux_reg_detail, + uint32_t val, void *data); +extern void +arc_mmu_aux_set(const struct arc_aux_reg_detail *aux_reg_detail, + uint32_t val, void *data) ; + +extern uint32_t +arc_mmu_aux_get(const struct arc_aux_reg_detail *aux_reg_detail, void *dat= a); + +uint32_t +arc_mmu_translate(struct CPUARCState *env, + uint32_t vaddr, enum mmu_access_type rwe, + uint32_t *index); + +void arc_mmu_debug_tlb(struct CPUARCState *env); +void arc_mmu_debug_tlb_for_vaddr(struct CPUARCState *env, uint32_t vaddr); + +uint32_t arc_mmu_page_address_for(uint32_t vaddr); + +void arc_mmu_init(struct arc_mmu *mmu); + +#endif /* ARC_MMU_H */ --=20 2.20.1