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from mx2.suse.de ([195.135.220.15]:48708) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kcVLY-0003In-Ny for qemu-devel@nongnu.org; Tue, 10 Nov 2020 10:14:15 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 2308EADEC; Tue, 10 Nov 2020 15:14:10 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/7] i386: move kvm accel files into kvm/ Date: Tue, 10 Nov 2020 16:14:00 +0100 Message-Id: <20201110151406.25648-2-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201110151406.25648-1-cfontana@suse.de> References: <20201110151406.25648-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/09 23:19:25 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x (no timestamps) [generic] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana --- MAINTAINERS | 2 +- hw/i386/fw_cfg.c | 2 +- hw/i386/intel_iommu.c | 2 +- hw/i386/kvm/apic.c | 2 +- hw/i386/kvm/clock.c | 2 +- hw/i386/microvm.c | 2 +- hw/i386/pc.c | 2 +- hw/i386/x86.c | 2 +- meson.build | 1 + target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 +- target/i386/helper.c | 2 +- target/i386/{ =3D> kvm}/hyperv-proto.h | 0 target/i386/{ =3D> kvm}/hyperv-stub.c | 0 target/i386/{ =3D> kvm}/hyperv.c | 0 target/i386/{ =3D> kvm}/hyperv.h | 0 target/i386/{ =3D> kvm}/kvm-stub.c | 0 target/i386/{ =3D> kvm}/kvm.c | 0 target/i386/{ =3D> kvm}/kvm_i386.h | 0 target/i386/kvm/meson.build | 3 +++ target/i386/kvm/trace-events | 7 +++++++ target/i386/kvm/trace.h | 1 + target/i386/machine.c | 4 ++-- target/i386/meson.build | 4 +--- target/i386/trace-events | 6 ------ 25 files changed, 26 insertions(+), 22 deletions(-) rename target/i386/{ =3D> kvm}/hyperv-proto.h (100%) rename target/i386/{ =3D> kvm}/hyperv-stub.c (100%) rename target/i386/{ =3D> kvm}/hyperv.c (100%) rename target/i386/{ =3D> kvm}/hyperv.h (100%) rename target/i386/{ =3D> kvm}/kvm-stub.c (100%) rename target/i386/{ =3D> kvm}/kvm.c (100%) rename target/i386/{ =3D> kvm}/kvm_i386.h (100%) create mode 100644 target/i386/kvm/meson.build create mode 100644 target/i386/kvm/trace-events create mode 100644 target/i386/kvm/trace.h diff --git a/MAINTAINERS b/MAINTAINERS index 63223e1183..dc888edf16 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -420,7 +420,7 @@ M: Paolo Bonzini M: Marcelo Tosatti L: kvm@vger.kernel.org S: Supported -F: target/i386/kvm.c +F: target/i386/kvm/ F: scripts/kvm/vmxcap =20 Guest CPU Cores (other accelerators) diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index e06579490c..fae1bb380f 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -21,7 +21,7 @@ #include "hw/timer/hpet.h" #include "hw/nvram/fw_cfg.h" #include "e820_memory_layout.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include CONFIG_DEVICES =20 struct hpet_fw_config hpet_cfg =3D {.count =3D UINT8_MAX}; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 70ac837733..361b6cd238 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -37,7 +37,7 @@ #include "sysemu/kvm.h" #include "sysemu/sysemu.h" #include "hw/i386/apic_internal.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "trace.h" =20 diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c index dd29906061..07bebc1282 100644 --- a/hw/i386/kvm/apic.c +++ b/hw/i386/kvm/apic.c @@ -17,7 +17,7 @@ #include "hw/pci/msi.h" #include "sysemu/hw_accel.h" #include "sysemu/kvm.h" -#include "target/i386/kvm_i386.h" +#include "kvm/kvm_i386.h" =20 static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic, int reg_id, uint32_t val) diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index 24fe5091b6..2d8a366369 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -20,7 +20,7 @@ #include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "sysemu/hw_accel.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "hw/sysbus.h" #include "hw/kvm/clock.h" diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 5428448b70..3ed6adff83 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -51,7 +51,7 @@ =20 #include "cpu.h" #include "elf.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "hw/xen/start_info.h" =20 #define MICROVM_QBOOT_FILENAME "qboot.rom" diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 5e6c0023e0..fd91213391 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -61,7 +61,7 @@ #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "hw/xen/xen.h" #include "hw/xen/start_info.h" #include "ui/qemu-spice.h" diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 5944fc44ed..88d0c70e12 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -52,7 +52,7 @@ #include "elf.h" #include "standard-headers/asm-x86/bootparam.h" #include CONFIG_DEVICES -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" =20 #define BIOS_FILENAME "bios.bin" =20 diff --git a/meson.build b/meson.build index 39ac5cf6d8..b76bb41731 100644 --- a/meson.build +++ b/meson.build @@ -1442,6 +1442,7 @@ trace_events_subdirs +=3D [ 'target/arm', 'target/hppa', 'target/i386', + 'target/i386/kvm', 'target/mips', 'target/ppc', 'target/riscv', diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0d8606958e..695153bd3e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -30,7 +30,7 @@ #include "sysemu/hvf.h" #include "sysemu/cpus.h" #include "sysemu/xen.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #include "sev_i386.h" =20 #include "qemu/error-report.h" diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 51c1d5f60a..2d02bcddff 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -22,7 +22,7 @@ =20 #include "sysemu/tcg.h" #include "cpu-qom.h" -#include "hyperv-proto.h" +#include "kvm/hyperv-proto.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" =20 diff --git a/target/i386/helper.c b/target/i386/helper.c index 32fa21a7bb..85748f8e8c 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -24,7 +24,7 @@ #include "qemu/qemu-print.h" #include "sysemu/kvm.h" #include "sysemu/runstate.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY #include "sysemu/tcg.h" #include "sysemu/hw_accel.h" diff --git a/target/i386/hyperv-proto.h b/target/i386/kvm/hyperv-proto.h similarity index 100% rename from target/i386/hyperv-proto.h rename to target/i386/kvm/hyperv-proto.h diff --git a/target/i386/hyperv-stub.c b/target/i386/kvm/hyperv-stub.c similarity index 100% rename from target/i386/hyperv-stub.c rename to target/i386/kvm/hyperv-stub.c diff --git a/target/i386/hyperv.c b/target/i386/kvm/hyperv.c similarity index 100% rename from target/i386/hyperv.c rename to target/i386/kvm/hyperv.c diff --git a/target/i386/hyperv.h b/target/i386/kvm/hyperv.h similarity index 100% rename from target/i386/hyperv.h rename to target/i386/kvm/hyperv.h diff --git a/target/i386/kvm-stub.c b/target/i386/kvm/kvm-stub.c similarity index 100% rename from target/i386/kvm-stub.c rename to target/i386/kvm/kvm-stub.c diff --git a/target/i386/kvm.c b/target/i386/kvm/kvm.c similarity index 100% rename from target/i386/kvm.c rename to target/i386/kvm/kvm.c diff --git a/target/i386/kvm_i386.h b/target/i386/kvm/kvm_i386.h similarity index 100% rename from target/i386/kvm_i386.h rename to target/i386/kvm/kvm_i386.h diff --git a/target/i386/kvm/meson.build b/target/i386/kvm/meson.build new file mode 100644 index 0000000000..1d66559187 --- /dev/null +++ b/target/i386/kvm/meson.build @@ -0,0 +1,3 @@ +i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) +i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) +i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_= false: files('hyperv-stub.c')) diff --git a/target/i386/kvm/trace-events b/target/i386/kvm/trace-events new file mode 100644 index 0000000000..b4e2d9e4ea --- /dev/null +++ b/target/i386/kvm/trace-events @@ -0,0 +1,7 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# kvm.c +kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for = GSI %" PRIu32 +kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d" +kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d" +kvm_x86_update_msi_routes(int num) "Updated %d MSI routes" diff --git a/target/i386/kvm/trace.h b/target/i386/kvm/trace.h new file mode 100644 index 0000000000..46b75c6942 --- /dev/null +++ b/target/i386/kvm/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_i386_kvm.h" diff --git a/target/i386/machine.c b/target/i386/machine.c index 233e46bb70..1614e8c2f8 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -3,9 +3,9 @@ #include "exec/exec-all.h" #include "hw/isa/isa.h" #include "migration/cpu.h" -#include "hyperv.h" +#include "kvm/hyperv.h" #include "hw/i386/x86.h" -#include "kvm_i386.h" +#include "kvm/kvm_i386.h" =20 #include "sysemu/kvm.h" #include "sysemu/tcg.h" diff --git a/target/i386/meson.build b/target/i386/meson.build index a1a02f3e99..0209542a8a 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -18,7 +18,6 @@ i386_ss.add(when: 'CONFIG_TCG', if_true: files( 'smm_helper.c', 'svm_helper.c', 'translate.c'), if_false: files('tcg-stub.c')) -i386_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) =20 i386_softmmu_ss =3D ss.source_set() @@ -28,8 +27,6 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_HYPERV', if_true: files('hyperv.c'), if_= false: files('hyperv-stub.c')) -i386_softmmu_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( 'whpx-all.c', 'whpx-cpus.c', @@ -42,6 +39,7 @@ i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('= hax-posix.c')) i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) =20 +subdir('kvm') subdir('hvf') =20 target_arch +=3D {'i386': i386_ss} diff --git a/target/i386/trace-events b/target/i386/trace-events index 789c700d4a..d166f9d5e0 100644 --- a/target/i386/trace-events +++ b/target/i386/trace-events @@ -1,11 +1,5 @@ # See docs/devel/tracing.txt for syntax documentation. =20 -# kvm.c -kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for = GSI %" PRIu32 -kvm_x86_add_msi_route(int virq) "Adding route entry for virq %d" -kvm_x86_remove_msi_route(int virq) "Removing route entry for virq %d" -kvm_x86_update_msi_routes(int num) "Updated %d MSI routes" - # sev.c kvm_sev_init(void) "" kvm_memcrypt_register_region(void *addr, size_t len) "addr %p len 0x%zu" --=20 2.26.2 From nobody Wed May 1 22:13:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1605021794; cv=none; d=zohomail.com; s=zohoarc; b=NsjCjddtCB5hayPqct53UYNyiwJ9Y+qKLJrd4dcF9wVb6eschR2BvFlUN3DE87v9ekwtgeRHNPKVZ1F8gG/cD7smhEkeVaGqmPEltaSLqEYCqgaajvslj2Y51BwqYjEdVEDGUJZoJZygXHkDCVrhuiCnrE1gwOvHplAwyEjZY3E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605021794; 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eggs.gnu.org ([2001:470:142:3::10]:47206) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kcVLa-0007xt-MF for qemu-devel@nongnu.org; Tue, 10 Nov 2020 10:14:14 -0500 Received: from mx2.suse.de ([195.135.220.15]:48752) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kcVLY-0003IW-N0 for qemu-devel@nongnu.org; Tue, 10 Nov 2020 10:14:14 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id F374FAE08; Tue, 10 Nov 2020 15:14:10 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 2/7] i386: move whpx accel files to whpx/ Date: Tue, 10 Nov 2020 16:14:01 +0100 Message-Id: <20201110151406.25648-3-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201110151406.25648-1-cfontana@suse.de> References: <20201110151406.25648-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/09 23:19:25 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x (no timestamps) [generic] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana --- MAINTAINERS | 5 +---- target/i386/meson.build | 5 +---- target/i386/whpx/meson.build | 4 ++++ target/i386/{ =3D> whpx}/whp-dispatch.h | 0 target/i386/{ =3D> whpx}/whpx-all.c | 0 target/i386/{ =3D> whpx}/whpx-cpus.c | 0 target/i386/{ =3D> whpx}/whpx-cpus.h | 0 7 files changed, 6 insertions(+), 8 deletions(-) create mode 100644 target/i386/whpx/meson.build rename target/i386/{ =3D> whpx}/whp-dispatch.h (100%) rename target/i386/{ =3D> whpx}/whpx-all.c (100%) rename target/i386/{ =3D> whpx}/whpx-cpus.c (100%) rename target/i386/{ =3D> whpx}/whpx-cpus.h (100%) diff --git a/MAINTAINERS b/MAINTAINERS index dc888edf16..c08042b4da 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -446,10 +446,7 @@ F: include/sysemu/hvf.h WHPX CPUs M: Sunil Muthuswamy S: Supported -F: target/i386/whpx-all.c -F: target/i386/whpx-cpus.c -F: target/i386/whp-dispatch.h -F: accel/stubs/whpx-stub.c +F: target/i386/whpx/ F: include/sysemu/whpx.h =20 Guest CPU Cores (Xen) diff --git a/target/i386/meson.build b/target/i386/meson.build index 0209542a8a..62cd042915 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -27,10 +27,6 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( - 'whpx-all.c', - 'whpx-cpus.c', -)) i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( 'hax-all.c', 'hax-mem.c', @@ -40,6 +36,7 @@ i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'],= if_true: files('hax-po i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) =20 subdir('kvm') +subdir('whpx') subdir('hvf') =20 target_arch +=3D {'i386': i386_ss} diff --git a/target/i386/whpx/meson.build b/target/i386/whpx/meson.build new file mode 100644 index 0000000000..94a72c8efc --- /dev/null +++ b/target/i386/whpx/meson.build @@ -0,0 +1,4 @@ +i386_softmmu_ss.add(when: 'CONFIG_WHPX', if_true: files( + 'whpx-all.c', + 'whpx-cpus.c', +)) diff --git a/target/i386/whp-dispatch.h b/target/i386/whpx/whp-dispatch.h similarity index 100% rename from target/i386/whp-dispatch.h rename to target/i386/whpx/whp-dispatch.h diff --git a/target/i386/whpx-all.c b/target/i386/whpx/whpx-all.c similarity index 100% rename from target/i386/whpx-all.c rename to target/i386/whpx/whpx-all.c diff --git a/target/i386/whpx-cpus.c b/target/i386/whpx/whpx-cpus.c similarity index 100% rename from target/i386/whpx-cpus.c rename to target/i386/whpx/whpx-cpus.c diff --git a/target/i386/whpx-cpus.h b/target/i386/whpx/whpx-cpus.h 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from mx2.suse.de ([195.135.220.15]:48776) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kcVLZ-0003Iv-3m for qemu-devel@nongnu.org; Tue, 10 Nov 2020 10:14:16 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id DA342AE0C; Tue, 10 Nov 2020 15:14:11 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 3/7] i386: move hax accel files to accel/hax Date: Tue, 10 Nov 2020 16:14:02 +0100 Message-Id: <20201110151406.25648-4-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201110151406.25648-1-cfontana@suse.de> References: <20201110151406.25648-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass 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, Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana --- MAINTAINERS | 2 +- target/i386/{ =3D> hax}/hax-all.c | 0 target/i386/{ =3D> hax}/hax-cpus.c | 0 target/i386/{ =3D> hax}/hax-cpus.h | 0 target/i386/{ =3D> hax}/hax-i386.h | 6 +++--- target/i386/{ =3D> hax}/hax-interface.h | 0 target/i386/{ =3D> hax}/hax-mem.c | 0 target/i386/{ =3D> hax}/hax-posix.c | 0 target/i386/{ =3D> hax}/hax-posix.h | 0 target/i386/{ =3D> hax}/hax-windows.c | 0 target/i386/{ =3D> hax}/hax-windows.h | 0 target/i386/hax/meson.build | 7 +++++++ target/i386/meson.build | 8 +------- 13 files changed, 12 insertions(+), 11 deletions(-) rename target/i386/{ =3D> hax}/hax-all.c (100%) rename target/i386/{ =3D> hax}/hax-cpus.c (100%) rename target/i386/{ =3D> hax}/hax-cpus.h (100%) rename target/i386/{ =3D> hax}/hax-i386.h (95%) rename target/i386/{ =3D> hax}/hax-interface.h (100%) rename target/i386/{ =3D> hax}/hax-mem.c (100%) rename target/i386/{ =3D> hax}/hax-posix.c (100%) rename target/i386/{ =3D> hax}/hax-posix.h (100%) rename target/i386/{ =3D> hax}/hax-windows.c (100%) rename target/i386/{ =3D> hax}/hax-windows.h (100%) create mode 100644 target/i386/hax/meson.build diff --git a/MAINTAINERS b/MAINTAINERS index c08042b4da..8af01750ba 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -486,7 +486,7 @@ W: https://github.com/intel/haxm/issues S: Maintained F: accel/stubs/hax-stub.c F: include/sysemu/hax.h -F: target/i386/hax-* +F: target/i386/hax/ =20 Hosts ----- diff --git a/target/i386/hax-all.c b/target/i386/hax/hax-all.c similarity index 100% rename from target/i386/hax-all.c rename to target/i386/hax/hax-all.c diff --git a/target/i386/hax-cpus.c b/target/i386/hax/hax-cpus.c similarity index 100% rename from target/i386/hax-cpus.c rename to target/i386/hax/hax-cpus.c diff --git a/target/i386/hax-cpus.h b/target/i386/hax/hax-cpus.h similarity index 100% rename from target/i386/hax-cpus.h rename to target/i386/hax/hax-cpus.h diff --git a/target/i386/hax-i386.h b/target/i386/hax/hax-i386.h similarity index 95% rename from target/i386/hax-i386.h rename to target/i386/hax/hax-i386.h index 48c4abe14e..efbb346238 100644 --- a/target/i386/hax-i386.h +++ b/target/i386/hax/hax-i386.h @@ -84,13 +84,13 @@ void hax_memory_init(void); =20 =20 #ifdef CONFIG_POSIX -#include "target/i386/hax-posix.h" +#include "hax-posix.h" #endif =20 #ifdef CONFIG_WIN32 -#include "target/i386/hax-windows.h" +#include "hax-windows.h" #endif =20 -#include "target/i386/hax-interface.h" +#include "hax-interface.h" =20 #endif diff --git a/target/i386/hax-interface.h b/target/i386/hax/hax-interface.h similarity index 100% rename from target/i386/hax-interface.h rename to target/i386/hax/hax-interface.h diff --git a/target/i386/hax-mem.c b/target/i386/hax/hax-mem.c similarity index 100% rename from target/i386/hax-mem.c rename to target/i386/hax/hax-mem.c diff --git a/target/i386/hax-posix.c b/target/i386/hax/hax-posix.c similarity index 100% rename from target/i386/hax-posix.c rename to target/i386/hax/hax-posix.c diff --git a/target/i386/hax-posix.h b/target/i386/hax/hax-posix.h similarity index 100% rename from target/i386/hax-posix.h rename to target/i386/hax/hax-posix.h diff --git a/target/i386/hax-windows.c b/target/i386/hax/hax-windows.c similarity index 100% rename from target/i386/hax-windows.c rename to target/i386/hax/hax-windows.c diff --git a/target/i386/hax-windows.h b/target/i386/hax/hax-windows.h similarity index 100% rename from target/i386/hax-windows.h rename to target/i386/hax/hax-windows.h diff --git a/target/i386/hax/meson.build b/target/i386/hax/meson.build new file mode 100644 index 0000000000..77ea431b30 --- /dev/null +++ b/target/i386/hax/meson.build @@ -0,0 +1,7 @@ +i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( + 'hax-all.c', + 'hax-mem.c', + 'hax-cpus.c', +)) +i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('= hax-posix.c')) +i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) diff --git a/target/i386/meson.build b/target/i386/meson.build index 62cd042915..284d52ab81 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -27,15 +27,9 @@ i386_softmmu_ss.add(files( 'machine.c', 'monitor.c', )) -i386_softmmu_ss.add(when: 'CONFIG_HAX', if_true: files( - 'hax-all.c', - 'hax-mem.c', - 'hax-cpus.c', -)) -i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('= hax-posix.c')) -i386_softmmu_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('= hax-windows.c')) =20 subdir('kvm') +subdir('hax') subdir('whpx') subdir('hvf') =20 --=20 2.26.2 From nobody Wed May 1 22:13:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as 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ESMTP id BB0CFADFF; Tue, 10 Nov 2020 15:14:12 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 4/7] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs Date: Tue, 10 Nov 2020 16:14:03 +0100 Message-Id: <20201110151406.25648-5-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201110151406.25648-1-cfontana@suse.de> References: <20201110151406.25648-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de 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file changed, 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8af01750ba..ad4edade03 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -439,7 +439,6 @@ M: Cameron Esfahani M: Roman Bolshakov W: https://wiki.qemu.org/Features/HVF S: Maintained -F: accel/stubs/hvf-stub.c F: target/i386/hvf/ F: include/sysemu/hvf.h =20 --=20 2.26.2 From nobody Wed May 1 22:13:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1605021624; cv=none; d=zohomail.com; s=zohoarc; b=cBfk7AYVKqJTVFEpHNm9pw31lor84f6fvH45T+b3pPA4P1KIlzwk6ahY4GzugJ77/6sQ3g/m3oVxxEPmsByrJ7sucbOiPQqZn+fnAlkJJfEGEClrhmvBfCg52I1tz2JdEXMsfeouuFdMX7xpN9BoiMq7nn6+fL94H6a1IIOON5E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605021624; 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eggs.gnu.org ([2001:470:142:3::10]:47314) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kcVLh-0008CV-Bw for qemu-devel@nongnu.org; Tue, 10 Nov 2020 10:14:21 -0500 Received: from mx2.suse.de ([195.135.220.15]:48874) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kcVLb-0003Jr-EV for qemu-devel@nongnu.org; Tue, 10 Nov 2020 10:14:21 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id A1965AE0B; Tue, 10 Nov 2020 15:14:13 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 5/7] i386: move TCG accel files into accel/tcg Date: Tue, 10 Nov 2020 16:14:04 +0100 Message-Id: <20201110151406.25648-6-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201110151406.25648-1-cfontana@suse.de> References: <20201110151406.25648-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/09 23:19:25 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x (no timestamps) [generic] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana --- target/i386/meson.build | 14 +------------- target/i386/{ =3D> tcg}/bpt_helper.c | 0 target/i386/{ =3D> tcg}/cc_helper.c | 0 target/i386/{ =3D> tcg}/excp_helper.c | 0 target/i386/{ =3D> tcg}/fpu_helper.c | 0 target/i386/{ =3D> tcg}/int_helper.c | 0 target/i386/{ =3D> tcg}/mem_helper.c | 0 target/i386/tcg/meson.build | 13 +++++++++++++ target/i386/{ =3D> tcg}/misc_helper.c | 0 target/i386/{ =3D> tcg}/mpx_helper.c | 0 target/i386/{ =3D> tcg}/seg_helper.c | 0 target/i386/{ =3D> tcg}/smm_helper.c | 0 target/i386/{ =3D> tcg}/svm_helper.c | 0 target/i386/{ =3D> tcg}/tcg-stub.c | 0 target/i386/{ =3D> tcg}/translate.c | 0 15 files changed, 14 insertions(+), 13 deletions(-) rename target/i386/{ =3D> tcg}/bpt_helper.c (100%) rename target/i386/{ =3D> tcg}/cc_helper.c (100%) rename target/i386/{ =3D> tcg}/excp_helper.c (100%) rename target/i386/{ =3D> tcg}/fpu_helper.c (100%) rename target/i386/{ =3D> tcg}/int_helper.c (100%) rename target/i386/{ =3D> tcg}/mem_helper.c (100%) create mode 100644 target/i386/tcg/meson.build rename target/i386/{ =3D> tcg}/misc_helper.c (100%) rename target/i386/{ =3D> tcg}/mpx_helper.c (100%) rename target/i386/{ =3D> tcg}/seg_helper.c (100%) rename target/i386/{ =3D> tcg}/smm_helper.c (100%) rename target/i386/{ =3D> tcg}/svm_helper.c (100%) rename target/i386/{ =3D> tcg}/tcg-stub.c (100%) rename target/i386/{ =3D> tcg}/translate.c (100%) diff --git a/target/i386/meson.build b/target/i386/meson.build index 284d52ab81..750471c9f3 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -5,19 +5,6 @@ i386_ss.add(files( 'helper.c', 'xsave_helper.c', )) -i386_ss.add(when: 'CONFIG_TCG', if_true: files( - 'bpt_helper.c', - 'cc_helper.c', - 'excp_helper.c', - 'fpu_helper.c', - 'int_helper.c', - 'mem_helper.c', - 'misc_helper.c', - 'mpx_helper.c', - 'seg_helper.c', - 'smm_helper.c', - 'svm_helper.c', - 'translate.c'), if_false: files('tcg-stub.c')) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) =20 i386_softmmu_ss =3D ss.source_set() @@ -32,6 +19,7 @@ subdir('kvm') subdir('hax') subdir('whpx') subdir('hvf') +subdir('tcg') =20 target_arch +=3D {'i386': i386_ss} target_softmmu_arch +=3D {'i386': i386_softmmu_ss} diff --git a/target/i386/bpt_helper.c b/target/i386/tcg/bpt_helper.c similarity index 100% rename from target/i386/bpt_helper.c rename to target/i386/tcg/bpt_helper.c diff --git a/target/i386/cc_helper.c b/target/i386/tcg/cc_helper.c similarity index 100% rename from target/i386/cc_helper.c rename to target/i386/tcg/cc_helper.c diff --git a/target/i386/excp_helper.c b/target/i386/tcg/excp_helper.c similarity index 100% rename from target/i386/excp_helper.c rename to target/i386/tcg/excp_helper.c diff --git a/target/i386/fpu_helper.c b/target/i386/tcg/fpu_helper.c similarity index 100% rename from target/i386/fpu_helper.c rename to target/i386/tcg/fpu_helper.c diff --git a/target/i386/int_helper.c b/target/i386/tcg/int_helper.c similarity index 100% rename from target/i386/int_helper.c rename to target/i386/tcg/int_helper.c diff --git a/target/i386/mem_helper.c b/target/i386/tcg/mem_helper.c similarity index 100% rename from target/i386/mem_helper.c rename to target/i386/tcg/mem_helper.c diff --git a/target/i386/tcg/meson.build b/target/i386/tcg/meson.build new file mode 100644 index 0000000000..02794226c2 --- /dev/null +++ b/target/i386/tcg/meson.build @@ -0,0 +1,13 @@ +i386_ss.add(when: 'CONFIG_TCG', if_true: files( + 'bpt_helper.c', + 'cc_helper.c', + 'excp_helper.c', + 'fpu_helper.c', + 'int_helper.c', + 'mem_helper.c', + 'misc_helper.c', + 'mpx_helper.c', + 'seg_helper.c', + 'smm_helper.c', + 'svm_helper.c', + 'translate.c'), if_false: files('tcg-stub.c')) diff --git a/target/i386/misc_helper.c b/target/i386/tcg/misc_helper.c similarity index 100% rename from target/i386/misc_helper.c rename to target/i386/tcg/misc_helper.c diff --git a/target/i386/mpx_helper.c b/target/i386/tcg/mpx_helper.c similarity index 100% rename from target/i386/mpx_helper.c rename to target/i386/tcg/mpx_helper.c diff --git a/target/i386/seg_helper.c b/target/i386/tcg/seg_helper.c similarity index 100% rename from target/i386/seg_helper.c rename to target/i386/tcg/seg_helper.c diff --git a/target/i386/smm_helper.c b/target/i386/tcg/smm_helper.c similarity index 100% rename from target/i386/smm_helper.c rename to target/i386/tcg/smm_helper.c diff --git a/target/i386/svm_helper.c b/target/i386/tcg/svm_helper.c similarity index 100% rename from target/i386/svm_helper.c rename to target/i386/tcg/svm_helper.c diff --git a/target/i386/tcg-stub.c b/target/i386/tcg/tcg-stub.c similarity index 100% rename from target/i386/tcg-stub.c rename to target/i386/tcg/tcg-stub.c diff --git a/target/i386/translate.c b/target/i386/tcg/translate.c similarity index 100% rename from target/i386/translate.c rename to target/i386/tcg/translate.c --=20 2.26.2 From nobody Wed May 1 22:13:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1605021504; cv=none; d=zohomail.com; s=zohoarc; b=eva1j3tRj9R6PyCYFuP/6GkBYvvRieeZz3R1mtO5HRFhrUCeMb9SbuEkbwYyTYK5Yz5E0EyKhd5cxxttxqceRedry73oTkz8oCpkrpfFockYIV7h2nehSBAK4tfxfKvsJrq7ggXQGvIcLtSwJUpi93FpKi5pNNbrHXlPCvtxtz8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1605021504; 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eggs.gnu.org ([2001:470:142:3::10]:47304) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kcVLg-00089w-3K for qemu-devel@nongnu.org; Tue, 10 Nov 2020 10:14:20 -0500 Received: from mx2.suse.de ([195.135.220.15]:48886) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kcVLb-0003KO-UE for qemu-devel@nongnu.org; Tue, 10 Nov 2020 10:14:19 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 944F9AE0D; Tue, 10 Nov 2020 15:14:14 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 6/7] i386: move cpu dump out of helper.c into cpu-dump.c Date: Tue, 10 Nov 2020 16:14:05 +0100 Message-Id: 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qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Eduardo Habkost , Paul Durrant , Jason Wang , Marcelo Tosatti , qemu-devel@nongnu.org, Peter Xu , Dario Faggioli , Cameron Esfahani , haxm-team@intel.com, Claudio Fontana , Anthony Perard , Bruce Rogers , Colin Xu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Claudio Fontana --- target/i386/cpu-dump.c | 538 ++++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 1 + target/i386/helper.c | 514 -------------------------------------- target/i386/meson.build | 1 + 4 files changed, 540 insertions(+), 514 deletions(-) create mode 100644 target/i386/cpu-dump.c diff --git a/target/i386/cpu-dump.c b/target/i386/cpu-dump.c new file mode 100644 index 0000000000..1ddc47fb0c --- /dev/null +++ b/target/i386/cpu-dump.c @@ -0,0 +1,538 @@ +/* + * i386 CPU dump to FILE + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "qemu/qemu-print.h" +#ifndef CONFIG_USER_ONLY +#include "hw/i386/apic_internal.h" +#endif + +/***********************************************************/ +/* x86 debug */ + +static const char *cc_op_str[CC_OP_NB] =3D { + "DYNAMIC", + "EFLAGS", + + "MULB", + "MULW", + "MULL", + "MULQ", + + "ADDB", + "ADDW", + "ADDL", + "ADDQ", + + "ADCB", + "ADCW", + "ADCL", + "ADCQ", + + "SUBB", + "SUBW", + "SUBL", + "SUBQ", + + "SBBB", + "SBBW", + "SBBL", + "SBBQ", + + "LOGICB", + "LOGICW", + "LOGICL", + "LOGICQ", + + "INCB", + "INCW", + "INCL", + "INCQ", + + "DECB", + "DECW", + "DECL", + "DECQ", + + "SHLB", + "SHLW", + "SHLL", + "SHLQ", + + "SARB", + "SARW", + "SARL", + "SARQ", + + "BMILGB", + "BMILGW", + "BMILGL", + "BMILGQ", + + "ADCX", + "ADOX", + "ADCOX", + + "CLR", +}; + +static void +cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, + const char *name, struct SegmentCache *sc) +{ +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "%-3s=3D%04x %016" PRIx64 " %08x %08x", name, + sc->selector, sc->base, sc->limit, + sc->flags & 0x00ffff00); + } else +#endif + { + qemu_fprintf(f, "%-3s=3D%04x %08x %08x %08x", name, sc->selector, + (uint32_t)sc->base, sc->limit, + sc->flags & 0x00ffff00); + } + + if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK)) + goto done; + + qemu_fprintf(f, " DPL=3D%d ", + (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT); + if (sc->flags & DESC_S_MASK) { + if (sc->flags & DESC_CS_MASK) { + qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" : + ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16")); + qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-= ', + (sc->flags & DESC_R_MASK) ? 'R' : '-'); + } else { + qemu_fprintf(f, (sc->flags & DESC_B_MASK + || env->hflags & HF_LMA_MASK) + ? "DS " : "DS16"); + qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-= ', + (sc->flags & DESC_W_MASK) ? 'W' : '-'); + } + qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-'); + } else { + static const char *sys_type_name[2][16] =3D { + { /* 32 bit mode */ + "Reserved", "TSS16-avl", "LDT", "TSS16-busy", + "CallGate16", "TaskGate", "IntGate16", "TrapGate16", + "Reserved", "TSS32-avl", "Reserved", "TSS32-busy", + "CallGate32", "Reserved", "IntGate32", "TrapGate32" + }, + { /* 64 bit mode */ + "", "Reserved", "LDT", "Reserved", "Reserved", + "Reserved", "Reserved", "Reserved", "Reserved", + "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64", + "Reserved", "IntGate64", "TrapGate64" + } + }; + qemu_fprintf(f, "%s", + sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0] + [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]); + } +done: + qemu_fprintf(f, "\n"); +} + +#ifndef CONFIG_USER_ONLY + +/* ARRAY_SIZE check is not required because + * DeliveryMode(dm) has a size of 3 bit. + */ +static inline const char *dm2str(uint32_t dm) +{ + static const char *str[] =3D { + "Fixed", + "...", + "SMI", + "...", + "NMI", + "INIT", + "...", + "ExtINT" + }; + return str[dm]; +} + +static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer) +{ + uint32_t dm =3D (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT; + qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s", + name, lvt, + lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi", + lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge", + lvt & APIC_LVT_MASKED ? "masked" : "", + lvt & APIC_LVT_DELIV_STS ? "pending" : "", + !is_timer ? + "" : lvt & APIC_LVT_TIMER_PERIODIC ? + "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ? + "tsc-deadline" : "one-shot", + dm2str(dm)); + if (dm !=3D APIC_DM_NMI) { + qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK); + } else { + qemu_printf("\n"); + } +} + +/* ARRAY_SIZE check is not required because + * destination shorthand has a size of 2 bit. + */ +static inline const char *shorthand2str(uint32_t shorthand) +{ + const char *str[] =3D { + "no-shorthand", "self", "all-self", "all" + }; + return str[shorthand]; +} + +static inline uint8_t divider_conf(uint32_t divide_conf) +{ + uint8_t divide_val =3D ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3= ); + + return divide_val =3D=3D 7 ? 1 : 2 << divide_val; +} + +static inline void mask2str(char *str, uint32_t val, uint8_t size) +{ + while (size--) { + *str++ =3D (val >> size) & 1 ? '1' : '0'; + } + *str =3D 0; +} + +#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16 + +static void dump_apic_icr(APICCommonState *s, CPUX86State *env) +{ + uint32_t icr =3D s->icr[0], icr2 =3D s->icr[1]; + uint8_t dest_shorthand =3D \ + (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT; + bool logical_mod =3D icr & APIC_ICR_DEST_MOD; + char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1]; + uint32_t dest_field; + bool x2apic; + + qemu_printf("ICR\t 0x%08x %s %s %s %s\n", + icr, + logical_mod ? "logical" : "physical", + icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge", + icr & APIC_ICR_LEVEL ? "assert" : "de-assert", + shorthand2str(dest_shorthand)); + + qemu_printf("ICR2\t 0x%08x", icr2); + if (dest_shorthand !=3D 0) { + qemu_printf("\n"); + return; + } + x2apic =3D env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC; + dest_field =3D x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT; + + if (!logical_mod) { + if (x2apic) { + qemu_printf(" cpu %u (X2APIC ID)\n", dest_field); + } else { + qemu_printf(" cpu %u (APIC ID)\n", + dest_field & APIC_LOGDEST_XAPIC_ID); + } + return; + } + + if (s->dest_mode =3D=3D 0xf) { /* flat mode */ + mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8); + qemu_printf(" mask %s (APIC ID)\n", apic_id_str); + } else if (s->dest_mode =3D=3D 0) { /* cluster mode */ + if (x2apic) { + mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16); + qemu_printf(" cluster %u mask %s (X2APIC ID)\n", + dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_s= tr); + } else { + mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4); + qemu_printf(" cluster %u mask %s (APIC ID)\n", + dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_st= r); + } + } +} + +static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab, + uint32_t *tmr_tab) +{ + int i, empty =3D true; + + qemu_printf("%s\t ", name); + for (i =3D 0; i < 256; i++) { + if (apic_get_bit(ireg_tab, i)) { + qemu_printf("%u%s ", i, + apic_get_bit(tmr_tab, i) ? "(level)" : ""); + empty =3D false; + } + } + qemu_printf("%s\n", empty ? "(none)" : ""); +} + +void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) +{ + X86CPU *cpu =3D X86_CPU(cs); + APICCommonState *s =3D APIC_COMMON(cpu->apic_state); + if (!s) { + qemu_printf("local apic state not available\n"); + return; + } + uint32_t *lvt =3D s->lvt; + + qemu_printf("dumping local APIC state for CPU %-2u\n\n", + CPU(cpu)->cpu_index); + dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false); + dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false); + dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false); + dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false); + dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false); + dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true); + + qemu_printf("Timer\t DCR=3D0x%x (divide by %u) initial_count =3D %u" + " current_count =3D %u\n", + s->divide_conf & APIC_DCR_MASK, + divider_conf(s->divide_conf), + s->initial_count, apic_get_current_count(s)); + + qemu_printf("SPIV\t 0x%08x APIC %s, focus=3D%s, spurious vec %u\n", + s->spurious_vec, + s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disab= led", + s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off", + s->spurious_vec & APIC_VECTOR_MASK); + + dump_apic_icr(s, &cpu->env); + + qemu_printf("ESR\t 0x%08x\n", s->esr); + + dump_apic_interrupt("ISR", s->isr, s->tmr); + dump_apic_interrupt("IRR", s->irr, s->tmr); + + qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x", + s->arb_id, s->tpr, s->dest_mode, s->log_dest); + if (s->dest_mode =3D=3D 0) { + qemu_printf("(cluster %u: id %u)", + s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT, + s->log_dest & APIC_LOGDEST_XAPIC_ID); + } + qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s)); +} +#else +void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) +{ +} +#endif /* !CONFIG_USER_ONLY */ + +#define DUMP_CODE_BYTES_TOTAL 50 +#define DUMP_CODE_BYTES_BACKWARD 20 + +void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + int eflags, i, nb; + char cc_op_name[32]; + static const char *seg_name[6] =3D { "ES", "CS", "SS", "DS", "FS", "GS= " }; + + eflags =3D cpu_compute_eflags(env); +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "RAX=3D%016" PRIx64 " RBX=3D%016" PRIx64 " RCX=3D%= 016" PRIx64 " RDX=3D%016" PRIx64 "\n" + "RSI=3D%016" PRIx64 " RDI=3D%016" PRIx64 " RBP=3D%016= " PRIx64 " RSP=3D%016" PRIx64 "\n" + "R8 =3D%016" PRIx64 " R9 =3D%016" PRIx64 " R10=3D%016= " PRIx64 " R11=3D%016" PRIx64 "\n" + "R12=3D%016" PRIx64 " R13=3D%016" PRIx64 " R14=3D%016= " PRIx64 " R15=3D%016" PRIx64 "\n" + "RIP=3D%016" PRIx64 " RFL=3D%08x [%c%c%c%c%c%c%c] CPL= =3D%d II=3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", + env->regs[R_EAX], + env->regs[R_EBX], + env->regs[R_ECX], + env->regs[R_EDX], + env->regs[R_ESI], + env->regs[R_EDI], + env->regs[R_EBP], + env->regs[R_ESP], + env->regs[8], + env->regs[9], + env->regs[10], + env->regs[11], + env->regs[12], + env->regs[13], + env->regs[14], + env->regs[15], + env->eip, eflags, + eflags & DF_MASK ? 'D' : '-', + eflags & CC_O ? 'O' : '-', + eflags & CC_S ? 'S' : '-', + eflags & CC_Z ? 'Z' : '-', + eflags & CC_A ? 'A' : '-', + eflags & CC_P ? 'P' : '-', + eflags & CC_C ? 'C' : '-', + env->hflags & HF_CPL_MASK, + (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, + (env->a20_mask >> 20) & 1, + (env->hflags >> HF_SMM_SHIFT) & 1, + cs->halted); + } else +#endif + { + qemu_fprintf(f, "EAX=3D%08x EBX=3D%08x ECX=3D%08x EDX=3D%08x\n" + "ESI=3D%08x EDI=3D%08x EBP=3D%08x ESP=3D%08x\n" + "EIP=3D%08x EFL=3D%08x [%c%c%c%c%c%c%c] CPL=3D%d II= =3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", + (uint32_t)env->regs[R_EAX], + (uint32_t)env->regs[R_EBX], + (uint32_t)env->regs[R_ECX], + (uint32_t)env->regs[R_EDX], + (uint32_t)env->regs[R_ESI], + (uint32_t)env->regs[R_EDI], + (uint32_t)env->regs[R_EBP], + (uint32_t)env->regs[R_ESP], + (uint32_t)env->eip, eflags, + eflags & DF_MASK ? 'D' : '-', + eflags & CC_O ? 'O' : '-', + eflags & CC_S ? 'S' : '-', + eflags & CC_Z ? 'Z' : '-', + eflags & CC_A ? 'A' : '-', + eflags & CC_P ? 'P' : '-', + eflags & CC_C ? 'C' : '-', + env->hflags & HF_CPL_MASK, + (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, + (env->a20_mask >> 20) & 1, + (env->hflags >> HF_SMM_SHIFT) & 1, + cs->halted); + } + + for(i =3D 0; i < 6; i++) { + cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]); + } + cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt); + cpu_x86_dump_seg_cache(env, f, "TR", &env->tr); + +#ifdef TARGET_X86_64 + if (env->hflags & HF_LMA_MASK) { + qemu_fprintf(f, "GDT=3D %016" PRIx64 " %08x\n", + env->gdt.base, env->gdt.limit); + qemu_fprintf(f, "IDT=3D %016" PRIx64 " %08x\n", + env->idt.base, env->idt.limit); + qemu_fprintf(f, "CR0=3D%08x CR2=3D%016" PRIx64 " CR3=3D%016" PRIx6= 4 " CR4=3D%08x\n", + (uint32_t)env->cr[0], + env->cr[2], + env->cr[3], + (uint32_t)env->cr[4]); + for(i =3D 0; i < 4; i++) + qemu_fprintf(f, "DR%d=3D%016" PRIx64 " ", i, env->dr[i]); + qemu_fprintf(f, "\nDR6=3D%016" PRIx64 " DR7=3D%016" PRIx64 "\n", + env->dr[6], env->dr[7]); + } else +#endif + { + qemu_fprintf(f, "GDT=3D %08x %08x\n", + (uint32_t)env->gdt.base, env->gdt.limit); + qemu_fprintf(f, "IDT=3D %08x %08x\n", + (uint32_t)env->idt.base, env->idt.limit); + qemu_fprintf(f, "CR0=3D%08x CR2=3D%08x CR3=3D%08x CR4=3D%08x\n", + (uint32_t)env->cr[0], + (uint32_t)env->cr[2], + (uint32_t)env->cr[3], + (uint32_t)env->cr[4]); + for(i =3D 0; i < 4; i++) { + qemu_fprintf(f, "DR%d=3D" TARGET_FMT_lx " ", i, env->dr[i]); + } + qemu_fprintf(f, "\nDR6=3D" TARGET_FMT_lx " DR7=3D" TARGET_FMT_lx "= \n", + env->dr[6], env->dr[7]); + } + if (flags & CPU_DUMP_CCOP) { + if ((unsigned)env->cc_op < CC_OP_NB) + snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->= cc_op]); + else + snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); +#ifdef TARGET_X86_64 + if (env->hflags & HF_CS64_MASK) { + qemu_fprintf(f, "CCS=3D%016" PRIx64 " CCD=3D%016" PRIx64 " CCO= =3D%-8s\n", + env->cc_src, env->cc_dst, + cc_op_name); + } else +#endif + { + qemu_fprintf(f, "CCS=3D%08x CCD=3D%08x CCO=3D%-8s\n", + (uint32_t)env->cc_src, (uint32_t)env->cc_dst, + cc_op_name); + } + } + qemu_fprintf(f, "EFER=3D%016" PRIx64 "\n", env->efer); + if (flags & CPU_DUMP_FPU) { + int fptag; + fptag =3D 0; + for(i =3D 0; i < 8; i++) { + fptag |=3D ((!env->fptags[i]) << i); + } + update_mxcsr_from_sse_status(env); + qemu_fprintf(f, "FCW=3D%04x FSW=3D%04x [ST=3D%d] FTW=3D%02x MXCSR= =3D%08x\n", + env->fpuc, + (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11, + env->fpstt, + fptag, + env->mxcsr); + for(i=3D0;i<8;i++) { + CPU_LDoubleU u; + u.d =3D env->fpregs[i].d; + qemu_fprintf(f, "FPR%d=3D%016" PRIx64 " %04x", + i, u.l.lower, u.l.upper); + if ((i & 1) =3D=3D 1) + qemu_fprintf(f, "\n"); + else + qemu_fprintf(f, " "); + } + if (env->hflags & HF_CS64_MASK) + nb =3D 16; + else + nb =3D 8; + for(i=3D0;ixmm_regs[i].ZMM_L(3), + env->xmm_regs[i].ZMM_L(2), + env->xmm_regs[i].ZMM_L(1), + env->xmm_regs[i].ZMM_L(0)); + if ((i & 1) =3D=3D 1) + qemu_fprintf(f, "\n"); + else + qemu_fprintf(f, " "); + } + } + if (flags & CPU_DUMP_CODE) { + target_ulong base =3D env->segs[R_CS].base + env->eip; + target_ulong offs =3D MIN(env->eip, DUMP_CODE_BYTES_BACKWARD); + uint8_t code; + char codestr[3]; + + qemu_fprintf(f, "Code=3D"); + for (i =3D 0; i < DUMP_CODE_BYTES_TOTAL; i++) { + if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) =3D= =3D 0) { + snprintf(codestr, sizeof(codestr), "%02x", code); + } else { + snprintf(codestr, sizeof(codestr), "??"); + } + qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "", + i =3D=3D offs ? "<" : "", codestr, i =3D=3D offs = ? ">" : ""); + } + qemu_fprintf(f, "\n"); + } +} + diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 2d02bcddff..943bbdebd7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2232,6 +2232,7 @@ void enable_compat_apic_id_mode(void); #define APIC_DEFAULT_ADDRESS 0xfee00000 #define APIC_SPACE_SIZE 0x100000 =20 +/* cpu-dump.c */ void x86_cpu_dump_local_apic_state(CPUState *cs, int flags); =20 /* cpu.c */ diff --git a/target/i386/helper.c b/target/i386/helper.c index 85748f8e8c..3974fb63b1 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -21,8 +21,6 @@ #include "qapi/qapi-events-run-state.h" #include "cpu.h" #include "exec/exec-all.h" -#include "qemu/qemu-print.h" -#include "sysemu/kvm.h" #include "sysemu/runstate.h" #include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY @@ -88,518 +86,6 @@ int cpu_x86_support_mca_broadcast(CPUX86State *env) return 0; } =20 -/***********************************************************/ -/* x86 debug */ - -static const char *cc_op_str[CC_OP_NB] =3D { - "DYNAMIC", - "EFLAGS", - - "MULB", - "MULW", - "MULL", - "MULQ", - - "ADDB", - "ADDW", - "ADDL", - "ADDQ", - - "ADCB", - "ADCW", - "ADCL", - "ADCQ", - - "SUBB", - "SUBW", - "SUBL", - "SUBQ", - - "SBBB", - "SBBW", - "SBBL", - "SBBQ", - - "LOGICB", - "LOGICW", - "LOGICL", - "LOGICQ", - - "INCB", - "INCW", - "INCL", - "INCQ", - - "DECB", - "DECW", - "DECL", - "DECQ", - - "SHLB", - "SHLW", - "SHLL", - "SHLQ", - - "SARB", - "SARW", - "SARL", - "SARQ", - - "BMILGB", - "BMILGW", - "BMILGL", - "BMILGQ", - - "ADCX", - "ADOX", - "ADCOX", - - "CLR", -}; - -static void -cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f, - const char *name, struct SegmentCache *sc) -{ -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "%-3s=3D%04x %016" PRIx64 " %08x %08x", name, - sc->selector, sc->base, sc->limit, - sc->flags & 0x00ffff00); - } else -#endif - { - qemu_fprintf(f, "%-3s=3D%04x %08x %08x %08x", name, sc->selector, - (uint32_t)sc->base, sc->limit, - sc->flags & 0x00ffff00); - } - - if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK)) - goto done; - - qemu_fprintf(f, " DPL=3D%d ", - (sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT); - if (sc->flags & DESC_S_MASK) { - if (sc->flags & DESC_CS_MASK) { - qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" : - ((sc->flags & DESC_B_MASK) ? "CS32" : "CS16")); - qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-= ', - (sc->flags & DESC_R_MASK) ? 'R' : '-'); - } else { - qemu_fprintf(f, (sc->flags & DESC_B_MASK - || env->hflags & HF_LMA_MASK) - ? "DS " : "DS16"); - qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-= ', - (sc->flags & DESC_W_MASK) ? 'W' : '-'); - } - qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-'); - } else { - static const char *sys_type_name[2][16] =3D { - { /* 32 bit mode */ - "Reserved", "TSS16-avl", "LDT", "TSS16-busy", - "CallGate16", "TaskGate", "IntGate16", "TrapGate16", - "Reserved", "TSS32-avl", "Reserved", "TSS32-busy", - "CallGate32", "Reserved", "IntGate32", "TrapGate32" - }, - { /* 64 bit mode */ - "", "Reserved", "LDT", "Reserved", "Reserved", - "Reserved", "Reserved", "Reserved", "Reserved", - "TSS64-avl", "Reserved", "TSS64-busy", "CallGate64", - "Reserved", "IntGate64", "TrapGate64" - } - }; - qemu_fprintf(f, "%s", - sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0] - [(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]); - } -done: - qemu_fprintf(f, "\n"); -} - -#ifndef CONFIG_USER_ONLY - -/* ARRAY_SIZE check is not required because - * DeliveryMode(dm) has a size of 3 bit. - */ -static inline const char *dm2str(uint32_t dm) -{ - static const char *str[] =3D { - "Fixed", - "...", - "SMI", - "...", - "NMI", - "INIT", - "...", - "ExtINT" - }; - return str[dm]; -} - -static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer) -{ - uint32_t dm =3D (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT; - qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s", - name, lvt, - lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi", - lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge", - lvt & APIC_LVT_MASKED ? "masked" : "", - lvt & APIC_LVT_DELIV_STS ? "pending" : "", - !is_timer ? - "" : lvt & APIC_LVT_TIMER_PERIODIC ? - "periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ? - "tsc-deadline" : "one-shot", - dm2str(dm)); - if (dm !=3D APIC_DM_NMI) { - qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK); - } else { - qemu_printf("\n"); - } -} - -/* ARRAY_SIZE check is not required because - * destination shorthand has a size of 2 bit. - */ -static inline const char *shorthand2str(uint32_t shorthand) -{ - const char *str[] =3D { - "no-shorthand", "self", "all-self", "all" - }; - return str[shorthand]; -} - -static inline uint8_t divider_conf(uint32_t divide_conf) -{ - uint8_t divide_val =3D ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3= ); - - return divide_val =3D=3D 7 ? 1 : 2 << divide_val; -} - -static inline void mask2str(char *str, uint32_t val, uint8_t size) -{ - while (size--) { - *str++ =3D (val >> size) & 1 ? '1' : '0'; - } - *str =3D 0; -} - -#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16 - -static void dump_apic_icr(APICCommonState *s, CPUX86State *env) -{ - uint32_t icr =3D s->icr[0], icr2 =3D s->icr[1]; - uint8_t dest_shorthand =3D \ - (icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT; - bool logical_mod =3D icr & APIC_ICR_DEST_MOD; - char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1]; - uint32_t dest_field; - bool x2apic; - - qemu_printf("ICR\t 0x%08x %s %s %s %s\n", - icr, - logical_mod ? "logical" : "physical", - icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge", - icr & APIC_ICR_LEVEL ? "assert" : "de-assert", - shorthand2str(dest_shorthand)); - - qemu_printf("ICR2\t 0x%08x", icr2); - if (dest_shorthand !=3D 0) { - qemu_printf("\n"); - return; - } - x2apic =3D env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC; - dest_field =3D x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT; - - if (!logical_mod) { - if (x2apic) { - qemu_printf(" cpu %u (X2APIC ID)\n", dest_field); - } else { - qemu_printf(" cpu %u (APIC ID)\n", - dest_field & APIC_LOGDEST_XAPIC_ID); - } - return; - } - - if (s->dest_mode =3D=3D 0xf) { /* flat mode */ - mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8); - qemu_printf(" mask %s (APIC ID)\n", apic_id_str); - } else if (s->dest_mode =3D=3D 0) { /* cluster mode */ - if (x2apic) { - mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16); - qemu_printf(" cluster %u mask %s (X2APIC ID)\n", - dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_s= tr); - } else { - mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4); - qemu_printf(" cluster %u mask %s (APIC ID)\n", - dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_st= r); - } - } -} - -static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab, - uint32_t *tmr_tab) -{ - int i, empty =3D true; - - qemu_printf("%s\t ", name); - for (i =3D 0; i < 256; i++) { - if (apic_get_bit(ireg_tab, i)) { - qemu_printf("%u%s ", i, - apic_get_bit(tmr_tab, i) ? "(level)" : ""); - empty =3D false; - } - } - qemu_printf("%s\n", empty ? "(none)" : ""); -} - -void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) -{ - X86CPU *cpu =3D X86_CPU(cs); - APICCommonState *s =3D APIC_COMMON(cpu->apic_state); - if (!s) { - qemu_printf("local apic state not available\n"); - return; - } - uint32_t *lvt =3D s->lvt; - - qemu_printf("dumping local APIC state for CPU %-2u\n\n", - CPU(cpu)->cpu_index); - dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false); - dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false); - dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false); - dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false); - dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false); - dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true); - - qemu_printf("Timer\t DCR=3D0x%x (divide by %u) initial_count =3D %u" - " current_count =3D %u\n", - s->divide_conf & APIC_DCR_MASK, - divider_conf(s->divide_conf), - s->initial_count, apic_get_current_count(s)); - - qemu_printf("SPIV\t 0x%08x APIC %s, focus=3D%s, spurious vec %u\n", - s->spurious_vec, - s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disab= led", - s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off", - s->spurious_vec & APIC_VECTOR_MASK); - - dump_apic_icr(s, &cpu->env); - - qemu_printf("ESR\t 0x%08x\n", s->esr); - - dump_apic_interrupt("ISR", s->isr, s->tmr); - dump_apic_interrupt("IRR", s->irr, s->tmr); - - qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x", - s->arb_id, s->tpr, s->dest_mode, s->log_dest); - if (s->dest_mode =3D=3D 0) { - qemu_printf("(cluster %u: id %u)", - s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT, - s->log_dest & APIC_LOGDEST_XAPIC_ID); - } - qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s)); -} -#else -void x86_cpu_dump_local_apic_state(CPUState *cs, int flags) -{ -} -#endif /* !CONFIG_USER_ONLY */ - -#define DUMP_CODE_BYTES_TOTAL 50 -#define DUMP_CODE_BYTES_BACKWARD 20 - -void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - int eflags, i, nb; - char cc_op_name[32]; - static const char *seg_name[6] =3D { "ES", "CS", "SS", "DS", "FS", "GS= " }; - - eflags =3D cpu_compute_eflags(env); -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "RAX=3D%016" PRIx64 " RBX=3D%016" PRIx64 " RCX=3D%= 016" PRIx64 " RDX=3D%016" PRIx64 "\n" - "RSI=3D%016" PRIx64 " RDI=3D%016" PRIx64 " RBP=3D%016= " PRIx64 " RSP=3D%016" PRIx64 "\n" - "R8 =3D%016" PRIx64 " R9 =3D%016" PRIx64 " R10=3D%016= " PRIx64 " R11=3D%016" PRIx64 "\n" - "R12=3D%016" PRIx64 " R13=3D%016" PRIx64 " R14=3D%016= " PRIx64 " R15=3D%016" PRIx64 "\n" - "RIP=3D%016" PRIx64 " RFL=3D%08x [%c%c%c%c%c%c%c] CPL= =3D%d II=3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", - env->regs[R_EAX], - env->regs[R_EBX], - env->regs[R_ECX], - env->regs[R_EDX], - env->regs[R_ESI], - env->regs[R_EDI], - env->regs[R_EBP], - env->regs[R_ESP], - env->regs[8], - env->regs[9], - env->regs[10], - env->regs[11], - env->regs[12], - env->regs[13], - env->regs[14], - env->regs[15], - env->eip, eflags, - eflags & DF_MASK ? 'D' : '-', - eflags & CC_O ? 'O' : '-', - eflags & CC_S ? 'S' : '-', - eflags & CC_Z ? 'Z' : '-', - eflags & CC_A ? 'A' : '-', - eflags & CC_P ? 'P' : '-', - eflags & CC_C ? 'C' : '-', - env->hflags & HF_CPL_MASK, - (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, - (env->a20_mask >> 20) & 1, - (env->hflags >> HF_SMM_SHIFT) & 1, - cs->halted); - } else -#endif - { - qemu_fprintf(f, "EAX=3D%08x EBX=3D%08x ECX=3D%08x EDX=3D%08x\n" - "ESI=3D%08x EDI=3D%08x EBP=3D%08x ESP=3D%08x\n" - "EIP=3D%08x EFL=3D%08x [%c%c%c%c%c%c%c] CPL=3D%d II= =3D%d A20=3D%d SMM=3D%d HLT=3D%d\n", - (uint32_t)env->regs[R_EAX], - (uint32_t)env->regs[R_EBX], - (uint32_t)env->regs[R_ECX], - (uint32_t)env->regs[R_EDX], - (uint32_t)env->regs[R_ESI], - (uint32_t)env->regs[R_EDI], - (uint32_t)env->regs[R_EBP], - (uint32_t)env->regs[R_ESP], - (uint32_t)env->eip, eflags, - eflags & DF_MASK ? 'D' : '-', - eflags & CC_O ? 'O' : '-', - eflags & CC_S ? 'S' : '-', - eflags & CC_Z ? 'Z' : '-', - eflags & CC_A ? 'A' : '-', - eflags & CC_P ? 'P' : '-', - eflags & CC_C ? 'C' : '-', - env->hflags & HF_CPL_MASK, - (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1, - (env->a20_mask >> 20) & 1, - (env->hflags >> HF_SMM_SHIFT) & 1, - cs->halted); - } - - for(i =3D 0; i < 6; i++) { - cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]); - } - cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt); - cpu_x86_dump_seg_cache(env, f, "TR", &env->tr); - -#ifdef TARGET_X86_64 - if (env->hflags & HF_LMA_MASK) { - qemu_fprintf(f, "GDT=3D %016" PRIx64 " %08x\n", - env->gdt.base, env->gdt.limit); - qemu_fprintf(f, "IDT=3D %016" PRIx64 " %08x\n", - env->idt.base, env->idt.limit); - qemu_fprintf(f, "CR0=3D%08x CR2=3D%016" PRIx64 " CR3=3D%016" PRIx6= 4 " CR4=3D%08x\n", - (uint32_t)env->cr[0], - env->cr[2], - env->cr[3], - (uint32_t)env->cr[4]); - for(i =3D 0; i < 4; i++) - qemu_fprintf(f, "DR%d=3D%016" PRIx64 " ", i, env->dr[i]); - qemu_fprintf(f, "\nDR6=3D%016" PRIx64 " DR7=3D%016" PRIx64 "\n", - env->dr[6], env->dr[7]); - } else -#endif - { - qemu_fprintf(f, "GDT=3D %08x %08x\n", - (uint32_t)env->gdt.base, env->gdt.limit); - qemu_fprintf(f, "IDT=3D %08x %08x\n", - (uint32_t)env->idt.base, env->idt.limit); - qemu_fprintf(f, "CR0=3D%08x CR2=3D%08x CR3=3D%08x CR4=3D%08x\n", - (uint32_t)env->cr[0], - (uint32_t)env->cr[2], - (uint32_t)env->cr[3], - (uint32_t)env->cr[4]); - for(i =3D 0; i < 4; i++) { - qemu_fprintf(f, "DR%d=3D" TARGET_FMT_lx " ", i, env->dr[i]); - } - qemu_fprintf(f, "\nDR6=3D" TARGET_FMT_lx " DR7=3D" TARGET_FMT_lx "= \n", - env->dr[6], env->dr[7]); - } - if (flags & CPU_DUMP_CCOP) { - if ((unsigned)env->cc_op < CC_OP_NB) - snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->= cc_op]); - else - snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op); -#ifdef TARGET_X86_64 - if (env->hflags & HF_CS64_MASK) { - qemu_fprintf(f, "CCS=3D%016" PRIx64 " CCD=3D%016" PRIx64 " CCO= =3D%-8s\n", - env->cc_src, env->cc_dst, - cc_op_name); - } else -#endif - { - qemu_fprintf(f, "CCS=3D%08x CCD=3D%08x CCO=3D%-8s\n", - (uint32_t)env->cc_src, (uint32_t)env->cc_dst, - cc_op_name); - } - } - qemu_fprintf(f, "EFER=3D%016" PRIx64 "\n", env->efer); - if (flags & CPU_DUMP_FPU) { - int fptag; - fptag =3D 0; - for(i =3D 0; i < 8; i++) { - fptag |=3D ((!env->fptags[i]) << i); - } - update_mxcsr_from_sse_status(env); - qemu_fprintf(f, "FCW=3D%04x FSW=3D%04x [ST=3D%d] FTW=3D%02x MXCSR= =3D%08x\n", - env->fpuc, - (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11, - env->fpstt, - fptag, - env->mxcsr); - for(i=3D0;i<8;i++) { - CPU_LDoubleU u; - u.d =3D env->fpregs[i].d; - qemu_fprintf(f, "FPR%d=3D%016" PRIx64 " %04x", - i, u.l.lower, u.l.upper); - if ((i & 1) =3D=3D 1) - qemu_fprintf(f, "\n"); - else - qemu_fprintf(f, " "); - } - if (env->hflags & HF_CS64_MASK) - nb =3D 16; - else - nb =3D 8; - for(i=3D0;ixmm_regs[i].ZMM_L(3), - env->xmm_regs[i].ZMM_L(2), - env->xmm_regs[i].ZMM_L(1), - env->xmm_regs[i].ZMM_L(0)); - if ((i & 1) =3D=3D 1) - qemu_fprintf(f, "\n"); - else - qemu_fprintf(f, " "); - } - } - if (flags & CPU_DUMP_CODE) { - target_ulong base =3D env->segs[R_CS].base + env->eip; - target_ulong offs =3D MIN(env->eip, DUMP_CODE_BYTES_BACKWARD); - uint8_t code; - char codestr[3]; - - qemu_fprintf(f, "Code=3D"); - for (i =3D 0; i < DUMP_CODE_BYTES_TOTAL; i++) { - if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) =3D= =3D 0) { - snprintf(codestr, sizeof(codestr), "%02x", code); - } else { - snprintf(codestr, sizeof(codestr), "??"); - } - qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "", - i =3D=3D offs ? "<" : "", codestr, i =3D=3D offs = ? ">" : ""); - } - qemu_fprintf(f, "\n"); - } -} - /***********************************************************/ /* x86 mmu */ /* XXX: add PGE support */ diff --git a/target/i386/meson.build b/target/i386/meson.build index 750471c9f3..c4bf20b319 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -4,6 +4,7 @@ i386_ss.add(files( 'gdbstub.c', 'helper.c', 'xsave_helper.c', + 'cpu-dump.c', )) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) =20 --=20 2.26.2 From nobody Wed May 1 22:13:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1605022154; cv=none; d=zohomail.com; s=zohoarc; b=Vq40ozfkJg/nHrC94vFyDXvErSmhqGMHzCSUOb7jUXycvD58frzE+GMizyC5YONxPBfn8eIC5qYg20FoqD0jltsSEYYoDm9Pd65qif/JDK+9amJ/N/V5iEr0l17Ic3TFaiLXHwLQtPyLjeNhGNzMxMf9A/cY4r1BF9szwCT0wUQ= ARC-Message-Signature: i=1; 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Tue, 10 Nov 2020 10:29:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:47348) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kcVLj-0008GZ-1M for qemu-devel@nongnu.org; Tue, 10 Nov 2020 10:14:23 -0500 Received: from mx2.suse.de ([195.135.220.15]:48942) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kcVLc-0003Kn-S7 for qemu-devel@nongnu.org; Tue, 10 Nov 2020 10:14:22 -0500 Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 8682CAF43; Tue, 10 Nov 2020 15:14:15 +0000 (UTC) X-Virus-Scanned: by amavisd-new at test-mx.suse.de From: Claudio Fontana To: Paolo Bonzini , Thomas Huth , Richard Henderson , Stefano Stabellini , Wenchao Wang , Roman Bolshakov , Sunil Muthuswamy , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 7/7] i386: move TCG cpu class initialization out of helper.c Date: Tue, 10 Nov 2020 16:14:06 +0100 Message-Id: <20201110151406.25648-8-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201110151406.25648-1-cfontana@suse.de> References: <20201110151406.25648-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Signed-off-by: Claudio Fontana --- target/i386/cpu.c | 33 ++++------ target/i386/cpu.h | 97 ++--------------------------- target/i386/helper-tcg.h | 112 ++++++++++++++++++++++++++++++++++ target/i386/helper.c | 23 ------- target/i386/meson.build | 1 + target/i386/tcg-cpu.c | 71 +++++++++++++++++++++ target/i386/tcg-cpu.h | 15 +++++ target/i386/tcg/bpt_helper.c | 1 + target/i386/tcg/cc_helper.c | 1 + target/i386/tcg/excp_helper.c | 1 + target/i386/tcg/fpu_helper.c | 33 +++++----- target/i386/tcg/int_helper.c | 1 + target/i386/tcg/mem_helper.c | 1 + target/i386/tcg/misc_helper.c | 1 + target/i386/tcg/mpx_helper.c | 1 + target/i386/tcg/seg_helper.c | 1 + target/i386/tcg/smm_helper.c | 2 + target/i386/tcg/svm_helper.c | 1 + target/i386/tcg/translate.c | 1 + 19 files changed, 244 insertions(+), 153 deletions(-) create mode 100644 target/i386/helper-tcg.h create mode 100644 target/i386/tcg-cpu.c create mode 100644 target/i386/tcg-cpu.h diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 695153bd3e..742a2cd522 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -24,6 +24,8 @@ #include "qemu/qemu-print.h" =20 #include "cpu.h" +#include "tcg-cpu.h" +#include "helper-tcg.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" @@ -1495,7 +1497,8 @@ static inline uint64_t x86_cpu_xsave_components(X86CP= U *cpu) cpu->env.features[FEAT_XSAVE_COMP_LO]; } =20 -const char *get_register_name_32(unsigned int reg) +/* Return name of 32-bit register, from a R_* constant */ +static const char *get_register_name_32(unsigned int reg) { if (reg >=3D CPU_NB_REGS32) { return NULL; @@ -7012,13 +7015,6 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.eip =3D value; } =20 -static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) -{ - X86CPU *cpu =3D X86_CPU(cs); - - cpu->env.eip =3D tb->pc - tb->cs_base; -} - int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu =3D X86_CPU(cs); @@ -7252,17 +7248,18 @@ static void x86_cpu_common_class_init(ObjectClass *= oc, void *data) cc->class_by_name =3D x86_cpu_class_by_name; cc->parse_features =3D x86_cpu_parse_featurestr; cc->has_work =3D x86_cpu_has_work; + #ifdef CONFIG_TCG - cc->do_interrupt =3D x86_cpu_do_interrupt; - cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; -#endif + tcg_cpu_common_class_init(cc); +#endif /* CONFIG_TCG */ + cc->dump_state =3D x86_cpu_dump_state; cc->set_pc =3D x86_cpu_set_pc; - cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; cc->gdb_read_register =3D x86_cpu_gdb_read_register; cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; + #ifndef CONFIG_USER_ONLY cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; @@ -7273,7 +7270,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->vmsd =3D &vmstate_x86_cpu; -#endif +#endif /* !CONFIG_USER_ONLY */ + cc->gdb_arch_name =3D x86_gdb_arch_name; #ifdef TARGET_X86_64 cc->gdb_core_xml_file =3D "i386-64bit.xml"; @@ -7281,15 +7279,6 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) #else cc->gdb_core_xml_file =3D "i386-32bit.xml"; cc->gdb_num_core_regs =3D 50; -#endif -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - cc->debug_excp_handler =3D breakpoint_handler; -#endif - cc->cpu_exec_enter =3D x86_cpu_exec_enter; - cc->cpu_exec_exit =3D x86_cpu_exec_exit; -#ifdef CONFIG_TCG - cc->tcg_initialize =3D tcg_x86_init; - cc->tlb_fill =3D x86_cpu_tlb_fill; #endif cc->disas_set_info =3D x86_disas_set_info; =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 943bbdebd7..dc228bf5e3 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -31,9 +31,6 @@ =20 #define KVM_HAVE_MCE_INJECTION 1 =20 -/* Maximum instruction code size */ -#define TARGET_MAX_INSN_SIZE 16 - /* support for self modifying code even if the modified instruction is close to the modifying instruction */ #define TARGET_HAS_PRECISE_SMC @@ -1037,6 +1034,12 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; * using this information. Condition codes are not generated if they * are only needed for conditional branches. */ + +#define CC_DST (env->cc_dst) +#define CC_SRC (env->cc_src) +#define CC_SRC2 (env->cc_src2) +#define CC_OP (env->cc_op) + typedef enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC =3D flags */ @@ -1765,12 +1768,6 @@ struct X86CPU { extern VMStateDescription vmstate_x86_cpu; #endif =20 -/** - * x86_cpu_do_interrupt: - * @cpu: vCPU the interrupt is to be handled by. - */ -void x86_cpu_do_interrupt(CPUState *cpu); -bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); =20 int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -1793,9 +1790,6 @@ hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cp= u, vaddr addr, int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 -void x86_cpu_exec_enter(CPUState *cpu); -void x86_cpu_exec_exit(CPUState *cpu); - void x86_cpu_list(void); int cpu_x86_support_mca_broadcast(CPUX86State *env); =20 @@ -1920,9 +1914,6 @@ void host_cpuid(uint32_t function, uint32_t count, void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); =20 /* helper.c */ -bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); void x86_cpu_set_a20(X86CPU *cpu, int a20_state); =20 #ifndef CONFIG_USER_ONLY @@ -1947,8 +1938,6 @@ void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t= val); void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val); #endif =20 -void breakpoint_handler(CPUState *cs); - /* will be suppressed */ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0); void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3); @@ -1958,16 +1947,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t n= ew_dr7); /* hw/pc.c */ uint64_t cpu_get_tsc(CPUX86State *env); =20 -/* XXX: This value should match the one returned by CPUID - * and in exec.c */ -# if defined(TARGET_X86_64) -# define TCG_PHYS_ADDR_BITS 40 -# else -# define TCG_PHYS_ADDR_BITS 36 -# endif - -#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) - #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_X86_CPU @@ -1999,30 +1978,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *= env) ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; } =20 -#define CC_DST (env->cc_dst) -#define CC_SRC (env->cc_src) -#define CC_SRC2 (env->cc_src2) -#define CC_OP (env->cc_op) - -/* n must be a constant to be efficient */ -static inline target_long lshift(target_long x, int n) -{ - if (n >=3D 0) { - return x << n; - } else { - return x >> (-n); - } -} - -/* float macros */ -#define FT0 (env->ft0) -#define ST0 (env->fpregs[env->fpstt].d) -#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) -#define ST1 ST(1) - -/* translate.c */ -void tcg_x86_init(void); - typedef CPUX86State CPUArchState; typedef X86CPU ArchCPU; =20 @@ -2052,19 +2007,6 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, i= nt bank, uint64_t status, uint64_t mcg_status, uint64_t add= r, uint64_t misc, int flags); =20 -/* excp_helper.c */ -void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); -void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_inde= x, - uintptr_t retaddr); -void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_ind= ex, - int error_code); -void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_= index, - int error_code, uintptr_t retadd= r); -void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_in= t, - int error_code, int next_eip_addend); - -/* cc_helper.c */ -extern const uint8_t parity_table[256]; uint32_t cpu_cc_compute_all(CPUX86State *env1, int op); =20 static inline uint32_t cpu_compute_eflags(CPUX86State *env) @@ -2076,18 +2018,6 @@ static inline uint32_t cpu_compute_eflags(CPUX86Stat= e *env) return eflags; } =20 -/* NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS - * after generating a call to a helper that uses this. - */ -static inline void cpu_load_eflags(CPUX86State *env, int eflags, - int update_mask) -{ - CC_SRC =3D eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - CC_OP =3D CC_OP_EFLAGS; - env->df =3D 1 - (2 * ((eflags >> 10) & 1)); - env->eflags =3D (env->eflags & ~update_mask) | - (eflags & update_mask) | 0x2; -} =20 /* load efer and update the corresponding hflags. XXX: do consistency checks with cpuid bits? */ @@ -2176,16 +2106,6 @@ void helper_lock_init(void); /* svm_helper.c */ void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type, uint64_t param, uintptr_t retaddr); -void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, - uint64_t exit_info_1, uintptr_t retaddr); -void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); - -/* seg_helper.c */ -void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); - -/* smm_helper.c */ -void do_smm_enter(X86CPU *cpu); - /* apic.c */ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, @@ -2224,11 +2144,6 @@ typedef int X86CPUVersion; */ void x86_cpu_set_default_version(X86CPUVersion version); =20 -/* Return name of 32-bit register, from a R_* constant */ -const char *get_register_name_32(unsigned int reg); - -void enable_compat_apic_id_mode(void); - #define APIC_DEFAULT_ADDRESS 0xfee00000 #define APIC_SPACE_SIZE 0x100000 =20 diff --git a/target/i386/helper-tcg.h b/target/i386/helper-tcg.h new file mode 100644 index 0000000000..57b4391a7d --- /dev/null +++ b/target/i386/helper-tcg.h @@ -0,0 +1,112 @@ +/* + * TCG specific prototypes for helpers + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef I386_HELPER_TCG_H +#define I386_HELPER_TCG_H + +#include "exec/exec-all.h" + +/* Maximum instruction code size */ +#define TARGET_MAX_INSN_SIZE 16 + +/* + * XXX: This value should match the one returned by CPUID + * and in exec.c + */ +# if defined(TARGET_X86_64) +# define TCG_PHYS_ADDR_BITS 40 +# else +# define TCG_PHYS_ADDR_BITS 36 +# endif + +#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS) + +/** + * x86_cpu_do_interrupt: + * @cpu: vCPU the interrupt is to be handled by. + */ +void x86_cpu_do_interrupt(CPUState *cpu); +bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); + +/* helper.c */ +bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); + +void breakpoint_handler(CPUState *cs); + +/* n must be a constant to be efficient */ +static inline target_long lshift(target_long x, int n) +{ + if (n >=3D 0) { + return x << n; + } else { + return x >> (-n); + } +} + +/* float macros */ +#define FT0 (env->ft0) +#define ST0 (env->fpregs[env->fpstt].d) +#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d) +#define ST1 ST(1) + +/* translate.c */ +void tcg_x86_init(void); + +/* excp_helper.c */ +void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index); +void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_inde= x, + uintptr_t retaddr); +void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_ind= ex, + int error_code); +void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_= index, + int error_code, uintptr_t retadd= r); +void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_in= t, + int error_code, int next_eip_addend); + +/* cc_helper.c */ +extern const uint8_t parity_table[256]; + +/* + * NOTE: the translator must set DisasContext.cc_op to CC_OP_EFLAGS + * after generating a call to a helper that uses this. + */ +static inline void cpu_load_eflags(CPUX86State *env, int eflags, + int update_mask) +{ + CC_SRC =3D eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + CC_OP =3D CC_OP_EFLAGS; + env->df =3D 1 - (2 * ((eflags >> 10) & 1)); + env->eflags =3D (env->eflags & ~update_mask) | + (eflags & update_mask) | 0x2; +} + +/* svm_helper.c */ +void QEMU_NORETURN cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, + uint64_t exit_info_1, uintptr_t retaddr); +void do_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1); + +/* seg_helper.c */ +void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw); + +/* smm_helper.c */ +void do_smm_enter(X86CPU *cpu); + +#endif /* I386_HELPER_TCG_H */ diff --git a/target/i386/helper.c b/target/i386/helper.c index 3974fb63b1..9bd91b47a5 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -24,10 +24,8 @@ #include "sysemu/runstate.h" #include "kvm/kvm_i386.h" #ifndef CONFIG_USER_ONLY -#include "sysemu/tcg.h" #include "sysemu/hw_accel.h" #include "monitor/monitor.h" -#include "hw/i386/apic_internal.h" #endif =20 void cpu_sync_bndcs_hflags(CPUX86State *env) @@ -574,27 +572,6 @@ void do_cpu_sipi(X86CPU *cpu) } #endif =20 -/* Frob eflags into and out of the CPU temporary format. */ - -void x86_cpu_exec_enter(CPUState *cs) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - - CC_SRC =3D env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - env->df =3D 1 - (2 * ((env->eflags >> 10) & 1)); - CC_OP =3D CC_OP_EFLAGS; - env->eflags &=3D ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); -} - -void x86_cpu_exec_exit(CPUState *cs) -{ - X86CPU *cpu =3D X86_CPU(cs); - CPUX86State *env =3D &cpu->env; - - env->eflags =3D cpu_compute_eflags(env); -} - #ifndef CONFIG_USER_ONLY uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr) { diff --git a/target/i386/meson.build b/target/i386/meson.build index c4bf20b319..9c20208e5a 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -6,6 +6,7 @@ i386_ss.add(files( 'xsave_helper.c', 'cpu-dump.c', )) +i386_ss.add(when: 'CONFIG_TCG', if_true: files('tcg-cpu.c')) i386_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files('= sev-stub.c')) =20 i386_softmmu_ss =3D ss.source_set() diff --git a/target/i386/tcg-cpu.c b/target/i386/tcg-cpu.c new file mode 100644 index 0000000000..628dd29fe7 --- /dev/null +++ b/target/i386/tcg-cpu.c @@ -0,0 +1,71 @@ +/* + * i386 TCG cpu class initialization + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "tcg-cpu.h" +#include "exec/exec-all.h" +#include "sysemu/runstate.h" +#include "helper-tcg.h" + +#if !defined(CONFIG_USER_ONLY) +#include "hw/i386/apic.h" +#endif + +/* Frob eflags into and out of the CPU temporary format. */ + +static void x86_cpu_exec_enter(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + CC_SRC =3D env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + env->df =3D 1 - (2 * ((env->eflags >> 10) & 1)); + CC_OP =3D CC_OP_EFLAGS; + env->eflags &=3D ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); +} + +static void x86_cpu_exec_exit(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + env->eflags =3D cpu_compute_eflags(env); +} + +static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + X86CPU *cpu =3D X86_CPU(cs); + + cpu->env.eip =3D tb->pc - tb->cs_base; +} + +void tcg_cpu_common_class_init(CPUClass *cc) +{ + cc->do_interrupt =3D x86_cpu_do_interrupt; + cc->cpu_exec_interrupt =3D x86_cpu_exec_interrupt; + cc->synchronize_from_tb =3D x86_cpu_synchronize_from_tb; + cc->cpu_exec_enter =3D x86_cpu_exec_enter; + cc->cpu_exec_exit =3D x86_cpu_exec_exit; + cc->tcg_initialize =3D tcg_x86_init; + cc->tlb_fill =3D x86_cpu_tlb_fill; +#ifndef CONFIG_USER_ONLY + cc->debug_excp_handler =3D breakpoint_handler; +#endif +} diff --git a/target/i386/tcg-cpu.h b/target/i386/tcg-cpu.h new file mode 100644 index 0000000000..81f02e562e --- /dev/null +++ b/target/i386/tcg-cpu.h @@ -0,0 +1,15 @@ +/* + * i386 TCG CPU class initialization + * + * Copyright 2020 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_CPU_H +#define TCG_CPU_H + +void tcg_cpu_common_class_init(CPUClass *cc); + +#endif /* TCG_CPU_H */ diff --git a/target/i386/tcg/bpt_helper.c b/target/i386/tcg/bpt_helper.c index c3a8ea73c9..5a551ce06e 100644 --- a/target/i386/tcg/bpt_helper.c +++ b/target/i386/tcg/bpt_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" =20 =20 #ifndef CONFIG_USER_ONLY diff --git a/target/i386/tcg/cc_helper.c b/target/i386/tcg/cc_helper.c index c9c90e10db..0b4c5b2cee 100644 --- a/target/i386/tcg/cc_helper.c +++ b/target/i386/tcg/cc_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" =20 const uint8_t parity_table[256] =3D { CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0, diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c index b10c7ecbcc..7cf690652e 100644 --- a/target/i386/tcg/excp_helper.c +++ b/target/i386/tcg/excp_helper.c @@ -23,6 +23,7 @@ #include "qemu/log.h" #include "sysemu/runstate.h" #include "exec/helper-proto.h" +#include "helper-tcg.h" =20 void helper_raise_interrupt(CPUX86State *env, int intno, int next_eip_adde= nd) { diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 4ea73874d8..28703a41a2 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -26,6 +26,7 @@ #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" #include "fpu/softfloat-macros.h" +#include "helper-tcg.h" =20 #ifdef CONFIG_SOFTMMU #include "hw/irq.h" @@ -2986,23 +2987,21 @@ void update_mxcsr_status(CPUX86State *env) =20 void update_mxcsr_from_sse_status(CPUX86State *env) { - if (tcg_enabled()) { - uint8_t flags =3D get_float_exception_flags(&env->sse_status); - /* - * The MXCSR denormal flag has opposite semantics to - * float_flag_input_denormal (the softfloat code sets that flag - * only when flushing input denormals to zero, but SSE sets it - * only when not flushing them to zero), so is not converted - * here. - */ - env->mxcsr |=3D ((flags & float_flag_invalid ? FPUS_IE : 0) | - (flags & float_flag_divbyzero ? FPUS_ZE : 0) | - (flags & float_flag_overflow ? FPUS_OE : 0) | - (flags & float_flag_underflow ? FPUS_UE : 0) | - (flags & float_flag_inexact ? FPUS_PE : 0) | - (flags & float_flag_output_denormal ? FPUS_UE | FPU= S_PE : - 0)); - } + uint8_t flags =3D get_float_exception_flags(&env->sse_status); + /* + * The MXCSR denormal flag has opposite semantics to + * float_flag_input_denormal (the softfloat code sets that flag + * only when flushing input denormals to zero, but SSE sets it + * only when not flushing them to zero), so is not converted + * here. + */ + env->mxcsr |=3D ((flags & float_flag_invalid ? FPUS_IE : 0) | + (flags & float_flag_divbyzero ? FPUS_ZE : 0) | + (flags & float_flag_overflow ? FPUS_OE : 0) | + (flags & float_flag_underflow ? FPUS_UE : 0) | + (flags & float_flag_inexact ? FPUS_PE : 0) | + (flags & float_flag_output_denormal ? FPUS_UE | FPUS_PE= : + 0)); } =20 void helper_update_mxcsr(CPUX86State *env) diff --git a/target/i386/tcg/int_helper.c b/target/i386/tcg/int_helper.c index 334469ca8c..5fedb851f3 100644 --- a/target/i386/tcg/int_helper.c +++ b/target/i386/tcg/int_helper.c @@ -24,6 +24,7 @@ #include "exec/helper-proto.h" #include "qapi/error.h" #include "qemu/guest-random.h" +#include "helper-tcg.h" =20 //#define DEBUG_MULDIV =20 diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 3a6d3ae2ef..1f6808d311 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -25,6 +25,7 @@ #include "qemu/int128.h" #include "qemu/atomic128.h" #include "tcg/tcg.h" +#include "helper-tcg.h" =20 void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0) { diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c index b6b1d41b14..9afcd11ea1 100644 --- a/target/i386/tcg/misc_helper.c +++ b/target/i386/tcg/misc_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" +#include "helper-tcg.h" =20 void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) { diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c index ade5d245d2..329aeef780 100644 --- a/target/i386/tcg/mpx_helper.c +++ b/target/i386/tcg/mpx_helper.c @@ -22,6 +22,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" +#include "helper-tcg.h" =20 =20 void helper_bndck(CPUX86State *env, uint32_t fail) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index be88938c2a..bad751c495 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -25,6 +25,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/log.h" +#include "helper-tcg.h" =20 //#define DEBUG_PCALL =20 diff --git a/target/i386/tcg/smm_helper.c b/target/i386/tcg/smm_helper.c index eb5aa6eb3d..ede197a379 100644 --- a/target/i386/tcg/smm_helper.c +++ b/target/i386/tcg/smm_helper.c @@ -22,6 +22,8 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/log.h" +#include "helper-tcg.h" + =20 /* SMM support */ =20 diff --git a/target/i386/tcg/svm_helper.c b/target/i386/tcg/svm_helper.c index 6224387eab..202832762e 100644 --- a/target/i386/tcg/svm_helper.c +++ b/target/i386/tcg/svm_helper.c @@ -22,6 +22,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "helper-tcg.h" =20 /* Secure Virtual Machine helpers */ =20 diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index caea6f5fb1..bb64070365 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -28,6 +28,7 @@ =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" +#include "helper-tcg.h" =20 #include "trace-tcg.h" #include "exec/log.h" --=20 2.26.2