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Content-Type: text/plain; charset="utf-8" Add a new MMU mode that includes the current virt mode. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 4b301bc0ea36da962fc1605371b65019ac3073df.1604464950.git.alistai= r.francis@wdc.com --- target/riscv/cpu-param.h | 11 ++++++++++- target/riscv/cpu.h | 4 +++- target/riscv/cpu_helper.c | 2 +- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h index 664fc1d371..80eb615f93 100644 --- a/target/riscv/cpu-param.h +++ b/target/riscv/cpu-param.h @@ -18,6 +18,15 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ #endif #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ -#define NB_MMU_MODES 4 +/* + * The current MMU Modes are: + * - U mode 0b000 + * - S mode 0b001 + * - M mode 0b011 + * - U mode HLV/HLVX/HSV 0b100 + * - S mode HLV/HLVX/HSV 0b101 + * - M mode HLV/HLVX/HSV 0b111 + */ +#define NB_MMU_MODES 8 =20 #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 87b68affa8..5d8e54c426 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -363,7 +363,9 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState = *env, target_ulong riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); =20 -#define TB_FLAGS_MMU_MASK 3 +#define TB_FLAGS_MMU_MASK 7 +#define TB_FLAGS_PRIV_MMU_MASK 3 +#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) #define TB_FLAGS_MSTATUS_FS MSTATUS_FS =20 typedef CPURISCVState CPUArchState; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3eb3a034db..9dfa7af401 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -323,7 +323,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, * (riscv_cpu_do_interrupt) is correct */ MemTxResult res; MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; - int mode =3D mmu_idx; + int mode =3D mmu_idx & TB_FLAGS_PRIV_MMU_MASK; bool use_background =3D false; =20 /* --=20 2.29.2 From nobody Fri May 3 09:43:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Content-Type: text/plain; charset="utf-8" When performing the hypervisor load/store operations set the MMU mode to indicate that we are virtualised. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: e411c61a1452cad16853f13cac2fb86dc91ebee8.1604464950.git.alistai= r.francis@wdc.com --- target/riscv/op_helper.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index e20d56dcb8..548c5851ec 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -235,30 +235,31 @@ target_ulong helper_hyp_load(CPURISCVState *env, targ= et_ulong address, (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { target_ulong pte; + int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 riscv_cpu_set_two_stage_lookup(env, true); =20 switch (memop) { case MO_SB: - pte =3D cpu_ldsb_data_ra(env, address, GETPC()); + pte =3D cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_UB: - pte =3D cpu_ldub_data_ra(env, address, GETPC()); + pte =3D cpu_ldub_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TESW: - pte =3D cpu_ldsw_data_ra(env, address, GETPC()); + pte =3D cpu_ldsw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUW: - pte =3D cpu_lduw_data_ra(env, address, GETPC()); + pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TESL: - pte =3D cpu_ldl_data_ra(env, address, GETPC()); + pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUL: - pte =3D cpu_ldl_data_ra(env, address, GETPC()); + pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEQ: - pte =3D cpu_ldq_data_ra(env, address, GETPC()); + pte =3D cpu_ldq_mmuidx_ra(env, address, mmu_idx, GETPC()); break; default: g_assert_not_reached(); @@ -284,23 +285,25 @@ void helper_hyp_store(CPURISCVState *env, target_ulon= g address, (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { + int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; + riscv_cpu_set_two_stage_lookup(env, true); =20 switch (memop) { case MO_SB: case MO_UB: - cpu_stb_data_ra(env, address, val, GETPC()); + cpu_stb_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TESW: case MO_TEUW: - cpu_stw_data_ra(env, address, val, GETPC()); + cpu_stw_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TESL: case MO_TEUL: - cpu_stl_data_ra(env, address, val, GETPC()); + cpu_stl_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; case MO_TEQ: - cpu_stq_data_ra(env, address, val, GETPC()); + cpu_stq_mmuidx_ra(env, address, val, mmu_idx, GETPC()); break; default: g_assert_not_reached(); @@ -326,15 +329,16 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, ta= rget_ulong address, (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && get_field(env->hstatus, HSTATUS_HU))) { target_ulong pte; + int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 riscv_cpu_set_two_stage_lookup(env, true); =20 switch (memop) { case MO_TEUW: - pte =3D cpu_lduw_data_ra(env, address, GETPC()); + pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); break; case MO_TEUL: - pte =3D cpu_ldl_data_ra(env, address, GETPC()); + pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); break; default: g_assert_not_reached(); --=20 2.29.2 From nobody Fri May 3 09:43:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1604981565; cv=none; d=zohomail.com; s=zohoarc; b=Y//suR5UatkvkNzCSPY/OVpt63fsr72NdS9UIZu91J/WCVdrd54wvmtW22echGPK2EAlmp3IXZ8JcbVwBEla/Wp0RW5P+zqDkI1RTCaVA6vMAm48onQxQLNU4nBbG46FAuYJ2SnuPqTuMXEAKu8PlBO6c6MM9jheX+tC/1aKJiQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604981565; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Content-Type: text/plain; charset="utf-8" The HS_TWO_STAGE flag is no longer required as the MMU index contains the information if we are performing a two stage access. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: f514b128b1ff0fb41c85f914cee18f905007a922.1604464950.git.alistai= r.francis@wdc.com --- target/riscv/cpu.h | 3 +- target/riscv/cpu_bits.h | 1 - target/riscv/cpu_helper.c | 60 ++++++++++++++++----------------------- target/riscv/op_helper.c | 12 -------- 4 files changed, 25 insertions(+), 51 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5d8e54c426..0cf48a1521 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -323,8 +323,7 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env); void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); -bool riscv_cpu_two_stage_lookup(CPURISCVState *env); -void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable); +bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index daedad8691..24b24c69c5 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -469,7 +469,6 @@ * page table fault. */ #define FORCE_HS_EXCEP 2 -#define HS_TWO_STAGE 4 =20 /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9dfa7af401..a2787b1d48 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -207,22 +207,9 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, = bool enable) env->virt =3D set_field(env->virt, FORCE_HS_EXCEP, enable); } =20 -bool riscv_cpu_two_stage_lookup(CPURISCVState *env) +bool riscv_cpu_two_stage_lookup(int mmu_idx) { - if (!riscv_has_ext(env, RVH)) { - return false; - } - - return get_field(env->virt, HS_TWO_STAGE); -} - -void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable) -{ - if (!riscv_has_ext(env, RVH)) { - return; - } - - env->virt =3D set_field(env->virt, HS_TWO_STAGE, enable); + return mmu_idx & TB_FLAGS_PRIV_HYP_ACCESS_MASK; } =20 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) @@ -333,7 +320,7 @@ static int get_physical_address(CPURISCVState *env, hwa= ddr *physical, * was called. Background registers will be used if the guest has * forced a two stage translation to be on (in HS or M mode). */ - if (riscv_cpu_two_stage_lookup(env) && access_type !=3D MMU_INST_FETCH= ) { + if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx= )) { use_background =3D true; } =20 @@ -572,7 +559,7 @@ restart: =20 static void raise_mmu_exception(CPURISCVState *env, target_ulong address, MMUAccessType access_type, bool pmp_violat= ion, - bool first_stage) + bool first_stage, bool two_stage) { CPUState *cs =3D env_cpu(env); int page_fault_exceptions; @@ -595,8 +582,7 @@ static void raise_mmu_exception(CPURISCVState *env, tar= get_ulong address, } break; case MMU_DATA_LOAD: - if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env= )) && - !first_stage) { + if (two_stage && !first_stage) { cs->exception_index =3D RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT; } else { cs->exception_index =3D page_fault_exceptions ? @@ -604,8 +590,7 @@ static void raise_mmu_exception(CPURISCVState *env, tar= get_ulong address, } break; case MMU_DATA_STORE: - if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env= )) && - !first_stage) { + if (two_stage && !first_stage) { cs->exception_index =3D RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAUL= T; } else { cs->exception_index =3D page_fault_exceptions ? @@ -696,6 +681,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, int prot, prot2; bool pmp_violation =3D false; bool first_stage_error =3D true; + bool two_stage_lookup =3D false; int ret =3D TRANSLATE_FAIL; int mode =3D mmu_idx; target_ulong tlb_size =3D 0; @@ -715,11 +701,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, access_type !=3D MMU_INST_FETCH && get_field(env->mstatus, MSTATUS_MPRV) && get_field(env->mstatus, MSTATUS_MPV)) { - riscv_cpu_set_two_stage_lookup(env, true); + two_stage_lookup =3D true; } =20 if (riscv_cpu_virt_enabled(env) || - (riscv_cpu_two_stage_lookup(env) && access_type !=3D MMU_INST_FETC= H)) { + ((riscv_cpu_two_stage_lookup(mmu_idx) || two_stage_lookup) && + access_type !=3D MMU_INST_FETCH)) { /* Two stage lookup */ ret =3D get_physical_address(env, &pa, &prot, address, &env->guest_phys_fault_addr, access_typ= e, @@ -782,14 +769,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, __func__, address, ret, pa, prot); } =20 - /* We did the two stage lookup based on MPRV, unset the lookup */ - if (riscv_has_ext(env, RVH) && env->priv =3D=3D PRV_M && - access_type !=3D MMU_INST_FETCH && - get_field(env->mstatus, MSTATUS_MPRV) && - get_field(env->mstatus, MSTATUS_MPV)) { - riscv_cpu_set_two_stage_lookup(env, false); - } - if (riscv_feature(env, RISCV_FEATURE_PMP) && (ret =3D=3D TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { @@ -811,7 +790,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } else if (probe) { return false; } else { - raise_mmu_exception(env, address, access_type, pmp_violation, firs= t_stage_error); + raise_mmu_exception(env, address, access_type, pmp_violation, + first_stage_error, + riscv_cpu_virt_enabled(env) || + riscv_cpu_two_stage_lookup(mmu_idx)); riscv_raise_exception(env, cs->exception_index, retaddr); } =20 @@ -915,9 +897,16 @@ void riscv_cpu_do_interrupt(CPUState *cs) /* handle the trap in S-mode */ if (riscv_has_ext(env, RVH)) { target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg; + bool two_stage_lookup =3D false; + + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + two_stage_lookup =3D true; + } =20 - if ((riscv_cpu_virt_enabled(env) || - riscv_cpu_two_stage_lookup(env)) && write_tval) { + if ((riscv_cpu_virt_enabled(env) || two_stage_lookup) && write= _tval) { /* * If we are writing a guest virtual address to stval, set * this to 1. If we are trapping to VS we will set this to= 0 @@ -955,11 +944,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) riscv_cpu_set_force_hs_excep(env, 0); } else { /* Trap into HS mode */ - if (!riscv_cpu_two_stage_lookup(env)) { + if (!two_stage_lookup) { env->hstatus =3D set_field(env->hstatus, HSTATUS_SPV, riscv_cpu_virt_enabled(env)); } - riscv_cpu_set_two_stage_lookup(env, false); htval =3D env->guest_phys_fault_addr; } } diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 548c5851ec..5759850e69 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -237,8 +237,6 @@ target_ulong helper_hyp_load(CPURISCVState *env, target= _ulong address, target_ulong pte; int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_SB: pte =3D cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); @@ -265,8 +263,6 @@ target_ulong helper_hyp_load(CPURISCVState *env, target= _ulong address, g_assert_not_reached(); } =20 - riscv_cpu_set_two_stage_lookup(env, false); - return pte; } =20 @@ -287,8 +283,6 @@ void helper_hyp_store(CPURISCVState *env, target_ulong = address, get_field(env->hstatus, HSTATUS_HU))) { int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_SB: case MO_UB: @@ -309,8 +303,6 @@ void helper_hyp_store(CPURISCVState *env, target_ulong = address, g_assert_not_reached(); } =20 - riscv_cpu_set_two_stage_lookup(env, false); - return; } =20 @@ -331,8 +323,6 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, targ= et_ulong address, target_ulong pte; int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; =20 - riscv_cpu_set_two_stage_lookup(env, true); - switch (memop) { case MO_TEUW: pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); @@ -344,8 +334,6 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, targ= et_ulong address, g_assert_not_reached(); } =20 - riscv_cpu_set_two_stage_lookup(env, false); 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Content-Type: text/plain; charset="utf-8" Remove the special Virtulisation load and store functions and just use the standard tcg tcg_gen_qemu_ld_tl() and tcg_gen_qemu_st_tl() functions instead. As part of this change we ensure we still run an access check to make sure we can perform the operations. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 189ac3e53ef2854824d18aad7074c6649f17de2c.1604464950.git.alistai= r.francis@wdc.com --- target/riscv/cpu.h | 12 +++ target/riscv/helper.h | 2 - target/riscv/op_helper.c | 86 ----------------- target/riscv/translate.c | 2 + target/riscv/insn_trans/trans_rvh.c.inc | 123 +++++++++--------------- 5 files changed, 59 insertions(+), 166 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0cf48a1521..c0a326c843 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -375,6 +375,8 @@ FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1) FIELD(TB_FLAGS, LMUL, 3, 2) FIELD(TB_FLAGS, SEW, 5, 3) FIELD(TB_FLAGS, VILL, 8, 1) +/* Is a Hypervisor instruction load/store allowed? */ +FIELD(TB_FLAGS, HLSX, 9, 1) =20 /* * A simplification for VLMAX @@ -421,7 +423,17 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState = *env, target_ulong *pc, if (riscv_cpu_fp_enabled(env)) { flags |=3D env->mstatus & MSTATUS_FS; } + + if (riscv_has_ext(env, RVH)) { + if (env->priv =3D=3D PRV_M || + (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || + (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && + get_field(env->hstatus, HSTATUS_HU))) { + flags =3D FIELD_DP32(flags, TB_FLAGS, HLSX, 1); + } + } #endif + *pflags =3D flags; } =20 diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 4b690147fb..ee35311052 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -81,8 +81,6 @@ DEF_HELPER_1(tlb_flush, void, env) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) -DEF_HELPER_4(hyp_load, tl, env, tl, tl, tl) -DEF_HELPER_5(hyp_store, void, env, tl, tl, tl, tl) DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) #endif =20 diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 5759850e69..980d4f39e1 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -227,92 +227,6 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } =20 -target_ulong helper_hyp_load(CPURISCVState *env, target_ulong address, - target_ulong attrs, target_ulong memop) -{ - if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - target_ulong pte; - int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; - - switch (memop) { - case MO_SB: - pte =3D cpu_ldsb_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_UB: - pte =3D cpu_ldub_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TESW: - pte =3D cpu_ldsw_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEUW: - pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TESL: - pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEUL: - pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEQ: - pte =3D cpu_ldq_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - default: - g_assert_not_reached(); - } - - return pte; - } - - if (riscv_cpu_virt_enabled(env)) { - riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); - } else { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } - return 0; -} - -void helper_hyp_store(CPURISCVState *env, target_ulong address, - target_ulong val, target_ulong attrs, target_ulong m= emop) -{ - if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; - - switch (memop) { - case MO_SB: - case MO_UB: - cpu_stb_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - case MO_TESW: - case MO_TEUW: - cpu_stw_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - case MO_TESL: - case MO_TEUL: - cpu_stl_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - case MO_TEQ: - cpu_stq_mmuidx_ra(env, address, val, mmu_idx, GETPC()); - break; - default: - g_assert_not_reached(); - } - - return; - } - - if (riscv_cpu_virt_enabled(env)) { - riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); - } else { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } -} - target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, target_ulong attrs, target_ulong memop) { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 79dca2291b..554d52a4be 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -56,6 +56,7 @@ typedef struct DisasContext { to reset this known value. */ int frm; bool ext_ifencei; + bool hlsx; /* vector extension */ bool vill; uint8_t lmul; @@ -807,6 +808,7 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->frm =3D -1; /* unknown rounding mode */ ctx->ext_ifencei =3D cpu->cfg.ext_ifencei; ctx->vlen =3D cpu->cfg.vlen; + ctx->hlsx =3D FIELD_EX32(tb_flags, TB_FLAGS, HLSX); ctx->vill =3D FIELD_EX32(tb_flags, TB_FLAGS, VILL); ctx->sew =3D FIELD_EX32(tb_flags, TB_FLAGS, SEW); ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index 881c9ef4d2..cc197e7186 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -16,26 +16,34 @@ * this program. If not, see . */ =20 +#ifndef CONFIG_USER_ONLY +static void check_access(DisasContext *ctx) { + if (!ctx->hlsx) { + if (ctx->virt_enabled) { + generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); + } else { + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); + } + } +} +#endif + static bool trans_hlv_b(DisasContext *ctx, arg_hlv_b *a) { REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_SB); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_SB); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -48,20 +56,16 @@ static bool trans_hlv_h(DisasContext *ctx, arg_hlv_h *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESW); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TESW); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -74,20 +78,16 @@ static bool trans_hlv_w(DisasContext *ctx, arg_hlv_w *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESL); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TESL); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -100,20 +100,16 @@ static bool trans_hlv_bu(DisasContext *ctx, arg_hlv_b= u *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_UB); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_UB); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -126,20 +122,15 @@ static bool trans_hlv_hu(DisasContext *ctx, arg_hlv_h= u *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); =20 - gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUW); + check_access(ctx); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + gen_get_gpr(t0, a->rs1); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEUW); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -152,20 +143,16 @@ static bool trans_hsv_b(DisasContext *ctx, arg_hsv_b = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_SB); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_SB); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -178,20 +165,16 @@ static bool trans_hsv_h(DisasContext *ctx, arg_hsv_h = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESW); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TESW); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -204,20 +187,16 @@ static bool trans_hsv_w(DisasContext *ctx, arg_hsv_w = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TESL); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TESL); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -231,20 +210,16 @@ static bool trans_hlv_wu(DisasContext *ctx, arg_hlv_w= u *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUL); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEUL); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -257,20 +232,16 @@ static bool trans_hlv_d(DisasContext *ctx, arg_hlv_d = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEQ); =20 - gen_helper_hyp_load(t1, cpu_env, t0, mem_idx, memop); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MAS= K, MO_TEQ); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -283,20 +254,16 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d = *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv dat =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); gen_get_gpr(dat, a->rs2); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEQ); =20 - gen_helper_hyp_store(cpu_env, t0, dat, mem_idx, memop); + tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK, MO_TEQ); =20 tcg_temp_free(t0); tcg_temp_free(dat); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; --=20 2.29.2 From nobody Fri May 3 09:43:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1604981582; cv=none; d=zohomail.com; s=zohoarc; b=V6eK5vSyghd2FJbiQ9ffVf/upGucUq1j59AdHYUgG4nMpafDVCS8B/tVyrA9YHfSNpM11VTx8DmhTOPj+lA3J/nixlvtD63WjgIsVp7JVSjnP9TPRfraUyyO9KjJdyMEIbVuCtaV1mCQWv8d3vlLyMRnl5Hrf9aENK7UJiwFbyA= ARC-Message-Signature: i=1; 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Content-Type: text/plain; charset="utf-8" Split the hypervisor execute load functions into two seperate functions. This avoids us having to pass the memop to the C helper functions. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 5b1550f0faa3c435cc77f3c1ae811dea98ab9e36.1604464950.git.alistai= r.francis@wdc.com --- target/riscv/helper.h | 3 ++- target/riscv/op_helper.c | 36 +++++++------------------ target/riscv/insn_trans/trans_rvh.c.inc | 20 +++++--------- 3 files changed, 17 insertions(+), 42 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index ee35311052..939731c345 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -81,7 +81,8 @@ DEF_HELPER_1(tlb_flush, void, env) #ifndef CONFIG_USER_ONLY DEF_HELPER_1(hyp_tlb_flush, void, env) DEF_HELPER_1(hyp_gvma_tlb_flush, void, env) -DEF_HELPER_4(hyp_x_load, tl, env, tl, tl, tl) +DEF_HELPER_2(hyp_hlvx_hu, tl, env, tl) +DEF_HELPER_2(hyp_hlvx_wu, tl, env, tl) #endif =20 /* Vector functions */ diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 980d4f39e1..d55def76cf 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -227,36 +227,18 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env) helper_hyp_tlb_flush(env); } =20 -target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address, - target_ulong attrs, target_ulong memop) +target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address) { - if (env->priv =3D=3D PRV_M || - (env->priv =3D=3D PRV_S && !riscv_cpu_virt_enabled(env)) || - (env->priv =3D=3D PRV_U && !riscv_cpu_virt_enabled(env) && - get_field(env->hstatus, HSTATUS_HU))) { - target_ulong pte; - int mmu_idx =3D cpu_mmu_index(env, false) | TB_FLAGS_PRIV_HYP_ACCE= SS_MASK; - - switch (memop) { - case MO_TEUW: - pte =3D cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - case MO_TEUL: - pte =3D cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); - break; - default: - g_assert_not_reached(); - } + int mmu_idx =3D cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK; =20 - return pte; - } + return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC()); +} =20 - if (riscv_cpu_virt_enabled(env)) { - riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT, GETP= C()); - } else { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); - } - return 0; +target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address) +{ + int mmu_idx =3D cpu_mmu_index(env, true) | TB_FLAGS_PRIV_HYP_ACCESS_MA= SK; + + return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC()); } =20 #endif /* !CONFIG_USER_ONLY */ diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_tr= ans/trans_rvh.c.inc index cc197e7186..ce7ed5affb 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -277,20 +277,16 @@ static bool trans_hlvx_hu(DisasContext *ctx, arg_hlvx= _hu *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUW); =20 - gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_helper_hyp_hlvx_hu(t1, cpu_env, t0); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; @@ -303,20 +299,16 @@ static bool trans_hlvx_wu(DisasContext *ctx, arg_hlvx= _wu *a) #ifndef CONFIG_USER_ONLY TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv mem_idx =3D tcg_temp_new(); - TCGv memop =3D tcg_temp_new(); + + check_access(ctx); =20 gen_get_gpr(t0, a->rs1); - tcg_gen_movi_tl(mem_idx, ctx->mem_idx); - tcg_gen_movi_tl(memop, MO_TEUL); =20 - gen_helper_hyp_x_load(t1, cpu_env, t0, mem_idx, memop); + gen_helper_hyp_hlvx_wu(t1, cpu_env, t0); gen_set_gpr(a->rd, t1); =20 tcg_temp_free(t0); tcg_temp_free(t1); - tcg_temp_free(mem_idx); - tcg_temp_free(memop); return true; #else return false; --=20 2.29.2 From nobody Fri May 3 09:43:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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d="scan'208";a="255803605" IronPort-SDR: kU4N0Annb4Ia8a8HH9S/t5tw23W+LxHs3JJbQS8bu+NrpaDtvdwrh7cz7eOaD0I5YFHqnHARmu E0uH47YYsEqGUYmGDkt56+6rEeD5eXxyBy+9kkyYkAhSLnDZJcIWawri8Uf6VifMaVSA3Ax4bC qp6+5gkaDDlkgTvC1jbnnxTn2RCnT6XhBFvCUfEL0dy/l+icdJaO2tmWLgsb2VOT1hjBwXrs3O 3h3XMGoTur1Gm8dBeg7VRj6nYvH8iYKWya6/RT6TaN96RHKBkuaDc3UjN/rE3gIi+k4NEohlju RcDbEwiTlbiGFzIOP9OEnF3V IronPort-SDR: rO0XqHEz9/pkAUhchlyGz1p8E7DH31COg352P1T+ncWxJX3/xP+cAH0Dn+C/nfgaA5XGe6ITnc DGLGab/O7s7IOfEgotMJ6WtdOn8G8whkujkfXoIMZwGqtPzTwaJ76cdJz50ewvSuxUDiGSIs6F JOjqEdbGis05xAsH9B9Z5y+EeXJeWlu0wiWFqflW/sfUxFGYAwl0US6Wm41eouv2sTkS546mfj yJdb8DyKQX68gJhAE6gSCplrv4lPIvcHkXqFfUImyolJyoY5Vd1r3fNDBY5EF3CysU95MJaXlq tQo= WDCIronportException: Internal From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 6/6] hw/intc/ibex_plic: Clear the claim register when read Date: Mon, 9 Nov 2020 19:57:03 -0800 Message-Id: <20201110035703.83786-7-alistair.francis@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201110035703.83786-1-alistair.francis@wdc.com> References: <20201110035703.83786-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=57671029a=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/09 23:09:00 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) After claiming the interrupt by reading the claim register we want to clear the register to make sure the interrupt doesn't appear at the next read. This matches the documentation for the claim register as when an interrupt is claimed by a target the relevant bit of IP is cleared (which we already do): https://docs.opentitan.org/hw/ip/rv_plic/doc/index.html This also matches the current hardware. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 68d4575deef2559b7a747f3bda193fcf43af4558.1604629928.git.alistai= r.francis@wdc.com --- hw/intc/ibex_plic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c index f49fa67c91..235e6b88ff 100644 --- a/hw/intc/ibex_plic.c +++ b/hw/intc/ibex_plic.c @@ -139,6 +139,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr add= r, /* Return the current claimed interrupt */ ret =3D s->claim; =20 + /* Clear the claimed interrupt */ + s->claim =3D 0x00000000; + /* Update the interrupt status after the claim */ ibex_plic_update(s); } --=20 2.29.2