From nobody Fri Oct 10 09:43:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1604931672; cv=none; d=zohomail.com; s=zohoarc; b=ASJKtuPVDslxYBQdERVWA7sY7SLdDTjxKTSZ67pLk2zphEYKzmw1zRi0qQ0n7eRymuXcA9ZKjVPmv1mvLJKXxDJm3Yslg6oizRq1k0QTaBSgqgcPYVW8B8LqocJIfvNmkFOJ/iDbYHOgrw7luQWRj+X46d0xH9sx+c1uLXhnOzM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604931672; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Xegqj87053LSQvH/QvjlKeFdGFmh8Zree5ykOhaYNIw=; b=BJ4jL2Wr+YF4S7jHTJpJxPOH23ZS9U17BC4ucWQiq8zSrmbuvgF5VHEXjx9aulDn1mc6nZq73PkovjzSBZHKvIIq5tByKf9iVbrPUGeda2uiS9MChoZl4qgiqaNXIaXz73H0y9bRPJHCe/dMDmLgKn8gLTJQXL7rA1moeHOrdvE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604931672257371.35576387855656; Mon, 9 Nov 2020 06:21:12 -0800 (PST) Received: from localhost ([::1]:40182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kc82h-0007PO-5M for importer@patchew.org; Mon, 09 Nov 2020 09:21:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40284) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kc7sK-00032D-IX; Mon, 09 Nov 2020 09:10:28 -0500 Received: from poy.remlab.net ([2001:41d0:2:5a1a::]:60174 helo=ns207790.ip-94-23-215.eu) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kc7sG-0002kj-67; Mon, 09 Nov 2020 09:10:28 -0500 Received: from basile.remlab.net (ip6-localhost [IPv6:::1]) by ns207790.ip-94-23-215.eu (Postfix) with ESMTP id 839955FBC5; Mon, 9 Nov 2020 15:10:21 +0100 (CET) From: remi.denis.courmont@huawei.com To: qemu-arm@nongnu.org Subject: [PATCH 03/17] target/arm: use arm_is_el2_enabled() where applicable Date: Mon, 9 Nov 2020 16:10:06 +0200 Message-Id: <20201109141020.27234-3-remi.denis.courmont@huawei.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <5554493.MhkbZ0Pkbq@basile.remlab.net> References: <5554493.MhkbZ0Pkbq@basile.remlab.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41d0:2:5a1a::; envelope-from=remi@remlab.net; helo=ns207790.ip-94-23-215.eu X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/09 08:56:07 X-ACL-Warn: Detected OS = ??? X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: R=C3=A9mi Denis-Courmont Do not assume that EL2 is available in non-secure context. That equivalence is broken by ARMv8.4-SEL2. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/helper-a64.c | 8 +------- target/arm/helper.c | 33 +++++++++++++-------------------- 3 files changed, 16 insertions(+), 29 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index adaded6bab..a1ee436853 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2101,7 +2101,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, i= nt el) return aa64; } =20 - if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)= ) { + if (arm_is_el2_enabled(env)) { aa64 =3D aa64 && (env->cp15.hcr_el2 & HCR_RW); } =20 @@ -3045,7 +3045,7 @@ static inline int arm_debug_target_el(CPUARMState *en= v) bool secure =3D arm_is_secure(env); bool route_to_el2 =3D false; =20 - if (arm_feature(env, ARM_FEATURE_EL2) && !secure) { + if (arm_is_el2_enabled(env)) { route_to_el2 =3D env->cp15.hcr_el2 & HCR_TGE || env->cp15.mdcr_el2 & MDCR_TDE; } diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 030821489b..c385fe82e9 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -972,8 +972,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_= t new_pc) if (new_el =3D=3D -1) { goto illegal_return; } - if (new_el > cur_el - || (new_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2))) { + if (new_el > cur_el || (new_el =3D=3D 2 && !arm_is_el2_enabled(env))) { /* Disallow return to an EL which is unimplemented or higher * than the current one. */ @@ -985,11 +984,6 @@ void HELPER(exception_return)(CPUARMState *env, uint64= _t new_pc) goto illegal_return; } =20 - if (new_el =3D=3D 2 && arm_is_secure_below_el3(env)) { - /* Return to the non-existent secure-EL2 */ - goto illegal_return; - } - if (new_el =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { goto illegal_return; } diff --git a/target/arm/helper.c b/target/arm/helper.c index b8b57d3b6b..817d4b1ca4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1048,8 +1048,8 @@ static CPAccessResult cpacr_access(CPUARMState *env, = const ARMCPRegInfo *ri, { if (arm_feature(env, ARM_FEATURE_V8)) { /* Check if CPACR accesses are to be trapped to EL2 */ - if (arm_current_el(env) =3D=3D 1 && - (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) { + if (arm_current_el(env) =3D=3D 1 && arm_is_el2_enabled(env) && + (env->cp15.cptr_el[2] & CPTR_TCPAC)) { return CP_ACCESS_TRAP_EL2; /* Check if CPACR accesses are to be trapped to EL3 */ } else if (arm_current_el(env) < 3 && @@ -2519,7 +2519,7 @@ static CPAccessResult gt_counter_access(CPUARMState *= env, int timeridx, bool isread) { unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); + bool has_el2 =3D arm_is_el2_enabled(env); uint64_t hcr =3D arm_hcr_el2_eff(env); =20 switch (cur_el) { @@ -2543,8 +2543,7 @@ static CPAccessResult gt_counter_access(CPUARMState *= env, int timeridx, } } else { /* If HCR_EL2. =3D=3D 0: check CNTHCTL_EL2.EL1PCEN. */ - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx =3D=3D GTIMER_PHYS && !secure && + if (has_el2 && timeridx =3D=3D GTIMER_PHYS && !extract32(env->cp15.cnthctl_el2, 1, 1)) { return CP_ACCESS_TRAP_EL2; } @@ -2553,8 +2552,7 @@ static CPAccessResult gt_counter_access(CPUARMState *= env, int timeridx, =20 case 1: /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H= . */ - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx =3D=3D GTIMER_PHYS && !secure && + if (has_el2 && timeridx =3D=3D GTIMER_PHYS && (hcr & HCR_E2H ? !extract32(env->cp15.cnthctl_el2, 10, 1) : !extract32(env->cp15.cnthctl_el2, 0, 1))) { @@ -2569,7 +2567,7 @@ static CPAccessResult gt_timer_access(CPUARMState *en= v, int timeridx, bool isread) { unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); + bool has_el2 =3D arm_is_el2_enabled(env); uint64_t hcr =3D arm_hcr_el2_eff(env); =20 switch (cur_el) { @@ -2590,8 +2588,7 @@ static CPAccessResult gt_timer_access(CPUARMState *en= v, int timeridx, /* fall through */ =20 case 1: - if (arm_feature(env, ARM_FEATURE_EL2) && - timeridx =3D=3D GTIMER_PHYS && !secure) { + if (has_el2 && timeridx =3D=3D GTIMER_PHYS) { if (hcr & HCR_E2H) { /* If HCR_EL2. =3D=3D '10': check CNTHCTL_EL2.EL1= PTEN. */ if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { @@ -4247,11 +4244,9 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] =3D= { =20 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu =3D env_archcpu(env); unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); =20 - if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el =3D= =3D 1) { + if (arm_is_el2_enabled(env) && cur_el =3D=3D 1) { return env->cp15.vpidr_el2; } return raw_read(env, ri); @@ -4278,9 +4273,8 @@ static uint64_t mpidr_read_val(CPUARMState *env) static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) { unsigned int cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); =20 - if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el =3D=3D 1) { + if (arm_is_el2_enabled(env) && cur_el =3D=3D 1) { return env->cp15.vmpidr_el2; } return mpidr_read_val(env); @@ -5347,7 +5341,7 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) { uint64_t ret =3D env->cp15.hcr_el2; =20 - if (arm_is_secure_below_el3(env)) { + if (!arm_is_el2_enabled(env)) { /* * "This register has no effect if EL2 is not enabled in the * current Security state". This is ARMv8.4-SecEL2 speak for @@ -6144,7 +6138,7 @@ int sve_exception_el(CPUARMState *env, int el) /* CPTR_EL2. Since TZ and TFP are positive, * they will be zero when EL2 is not present. */ - if (el <=3D 2 && !arm_is_secure_below_el3(env)) { + if (el <=3D 2 && arm_is_el2_enabled(env)) { if (env->cp15.cptr_el[2] & CPTR_TZ) { return 2; } @@ -8723,8 +8717,7 @@ static int bad_mode_switch(CPUARMState *env, int mode= , CPSRWriteType write_type) } return 0; case ARM_CPU_MODE_HYP: - return !arm_feature(env, ARM_FEATURE_EL2) - || arm_current_el(env) < 2 || arm_is_secure_below_el3(env); + return !arm_is_el2_enabled(env) || arm_current_el(env) < 2; case ARM_CPU_MODE_MON: return arm_current_el(env) < 3; default: @@ -12634,7 +12627,7 @@ int fp_exception_el(CPUARMState *env, int cur_el) =20 /* CPTR_EL2 : present in v7VE or v8 */ if (cur_el <=3D 2 && extract32(env->cp15.cptr_el[2], 10, 1) - && !arm_is_secure_below_el3(env)) { + && arm_is_el2_enabled(env)) { /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ return 2; } --=20 2.29.2