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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" According to the PowerISA v3.1 reference, Table 68 "Actions for xscmpudp - Part 1: Compare Unordered", whenever one of the two operands is a NaN the SO bit is set while the other three bits are cleared. Apply the same change to xscmpuqp. The respective ordered counterparts are unaffected. Signed-off-by: Giuseppe Musacchio --- target/ppc/fpu_helper.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 9b8c8b70b6..b07ff66375 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2479,13 +2479,11 @@ void helper_##op(CPUPPCState *env, uint32_t opcode,= \ if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \ float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \ vxsnan_flag =3D true; = \ - cc =3D CRF_SO; = \ if (fpscr_ve =3D=3D 0 && ordered) { = \ vxvc_flag =3D true; = \ } \ } else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || \ float64_is_quiet_nan(xb->VsrD(0), &env->fp_status)) { \ - cc =3D CRF_SO; = \ if (ordered) { \ vxvc_flag =3D true; = \ } \ @@ -2497,12 +2495,19 @@ void helper_##op(CPUPPCState *env, uint32_t opcode,= \ float_invalid_op_vxvc(env, 0, GETPC()); \ } \ \ - if (float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { \ + switch (float64_compare(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) {\ + case float_relation_less: \ cc |=3D CRF_LT; = \ - } else if (!float64_le(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) { \ - cc |=3D CRF_GT; = \ - } else { \ + break; \ + case float_relation_equal: \ cc |=3D CRF_EQ; = \ + break; \ + case float_relation_greater: \ + cc |=3D CRF_GT; = \ + break; \ + case float_relation_unordered: \ + cc |=3D CRF_SO; = \ + break; \ } \ \ env->fpscr &=3D ~FP_FPCC; = \ @@ -2545,12 +2550,19 @@ void helper_##op(CPUPPCState *env, uint32_t opcode,= \ float_invalid_op_vxvc(env, 0, GETPC()); \ } \ \ - if (float128_lt(xa->f128, xb->f128, &env->fp_status)) { \ + switch (float128_compare(xa->f128, xb->f128, &env->fp_status)) { \ + case float_relation_less: \ cc |=3D CRF_LT; \ - } else if (!float128_le(xa->f128, xb->f128, &env->fp_status)) { \ - cc |=3D CRF_GT; \ - } else { \ + break; \ + case float_relation_equal: \ cc |=3D CRF_EQ; \ + break; \ + case float_relation_greater: \ + cc |=3D CRF_GT; \ + break; \ + case float_relation_unordered: \ + cc |=3D CRF_SO; \ + break; \ } \ \ env->fpscr &=3D ~FP_FPCC; \ --=20 2.27.0