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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l1sm3162649wrb.1.2020.11.06.09.11.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2020 09:11:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c5vzAfZVeD2fj+XSE443hBvvKPlw3OYEaKcDPAg0K5A=; b=dIleZsap3o6+gXkOpa4XvxrVEYJ996ZN0OD9RRKGSTVcfC88Oy44hK7YibbrOwON0K ZJOfVd4VrlGwyqvGaqnINa4uofv0mw64XDU7yvbMCBGgW/VVjfTXe/fHUY+piAAweZI8 aqNkmLicRvZBwxA7HnxQb/7kWtq4eV4EUuYMEQ/wOmycK1hfU06RLPBGdjD7i+A0L90G 15fwFJyw4rzOcx/w7/ofjlk+Vo6T71UzIVgcnwqvYKl5PTbwG7Fup8EeCKyxQ0CHL5Ak ZYxBcfjoXPoPsAhobPej6IlOrGuaz7EIAUANKsC6lvL6S+e39wH5CQu4fqDR8c9QMNgF orAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c5vzAfZVeD2fj+XSE443hBvvKPlw3OYEaKcDPAg0K5A=; b=OKodl3ZqyjS8P2FWI6Dl3NWO7SVF2eRZPDtqyLATKriz9oxRav6qu4QFcBAgTzoKFg yQDfNQSqJcBk3nUJgjxvgTB/jyvQoCI04H8lqCe14Sx/NO8JWc+BGTqf0vM8BT3S1vAj miVQ+4381pf83TpnuEmp5ZvZtPalsF7yk2x8jNkMvBjUlWF9zT29G8t83yEZ7HzJubxB iIQE68U2NqqlKeb0cShoJyqC6STw+ClfuTnd6l6jjearW8iDbo7EDGj4phfCEDcgYQ4z h/KohBLlFnOQ9vevdX+lgJ+4S86IAD2QwS3EhzzkjRP2Yo+Uh9j13mUlyBncuraD0UyA A3KQ== X-Gm-Message-State: AOAM531/n3jpdjrS+Zu+7HB9O3kzPl48lVEgDb2joz41jr8nvn6dgQgm jN4LFq5yFbPCTLOBME438wBwu63ScYwtwA== X-Google-Smtp-Source: ABdhPJztB/QX6nwJKFN+J6RQb+WN+lfvuF7XxFQL8Ijbu/8AR61GfVhaWtoMDjj6qqE/uyEiZ8CC2g== X-Received: by 2002:a05:600c:2282:: with SMTP id 2mr653714wmf.154.1604682716930; Fri, 06 Nov 2020 09:11:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH for-5.2 1/4] hw/net/can/ctucan: Don't allow guest to write off end of tx_buffer Date: Fri, 6 Nov 2020 17:11:50 +0000 Message-Id: <20201106171153.32673-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201106171153.32673-1-peter.maydell@linaro.org> References: <20201106171153.32673-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , Vikram Garhwal , Pavel Pisa Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The ctucan device has 4 CAN bus cores, each of which has a set of 20 32-bit registers for writing the transmitted data. The registers are however not contiguous; each core's buffers is 0x100 bytes after the last. We got the checks on the address wrong in the ctucan_mem_write() function: * the first "is addr in range at all" check allowed addr =3D=3D CTUCAN_CORE_MEM_SIZE, which is actually the first byte off the end of the range * the decode of addresses into core-number plus offset in the tx buffer for that core failed to check that the offset was in range, so the guest could write off the end of the tx_buffer[] array * the decode had an explicit check for whether the core-number was out of range, which is actually impossible given the CTUCAN_CORE_MEM_SIZE check and the number of cores. Fix the top level check, check the offset, and turn the check on the core-number into an assertion. Fixes: Coverity CID 1432874 Signed-off-by: Peter Maydell Acked-by: Pavel Pisa --- hw/net/can/ctucan_core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/net/can/ctucan_core.c b/hw/net/can/ctucan_core.c index d20835cd7e9..ea09bf71a0c 100644 --- a/hw/net/can/ctucan_core.c +++ b/hw/net/can/ctucan_core.c @@ -303,7 +303,7 @@ void ctucan_mem_write(CtuCanCoreState *s, hwaddr addr, = uint64_t val, DPRINTF("write 0x%02llx addr 0x%02x\n", (unsigned long long)val, (unsigned int)addr); =20 - if (addr > CTUCAN_CORE_MEM_SIZE) { + if (addr >=3D CTUCAN_CORE_MEM_SIZE) { return; } =20 @@ -312,7 +312,8 @@ void ctucan_mem_write(CtuCanCoreState *s, hwaddr addr, = uint64_t val, addr -=3D CTU_CAN_FD_TXTB1_DATA_1; buff_num =3D addr / CTUCAN_CORE_TXBUFF_SPAN; addr %=3D CTUCAN_CORE_TXBUFF_SPAN; - if (buff_num < CTUCAN_CORE_TXBUF_NUM) { + assert(buff_num < CTUCAN_CORE_TXBUF_NUM); + if (addr < sizeof(s->tx_buffer[buff_num].data)) { uint32_t *bufp =3D (uint32_t *)(s->tx_buffer[buff_num].data + = addr); *bufp =3D cpu_to_le32(val); } --=20 2.20.1