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[76.14.210.194]) by smtp.gmail.com with ESMTPSA id 5sm3526175pfx.63.2020.11.05.09.11.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2020 09:11:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=kNbjBkupF0zVjgUXfsX0pswQ6D+6HK9IRUb0+XAw64M=; b=bBDKNXVA2RSk/S/ZU9iptMBa2CDUYQ3WYvZGtdfIgnN4x5BsSWtE968o0weK7s+n8k 62UF5kiwNYJf4v/3J7nhgs5/usCgnU1O5ezaqu87SXTjabfWd8YhUbxQKJA5v5moU7TL G0IEgGAJjMPL0Maf3Q3HOwxMwj1p/zHmhuxlwXCgU0Z9mTQdXWLGOYglPP/nz+/+hDo8 4eB7uBRXR1UYXIavJ4KRNXCvtX+2lYnXWPlqVJi3mH3McQ/jH3Y0velOUpWFTiC49t/o ZH17BX3OgJLuLr7VSZA07PZLgHXOPUghb/ubAKhFoHexiRE2htJsMKEG8YdLa1Y9bDsm uY9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=kNbjBkupF0zVjgUXfsX0pswQ6D+6HK9IRUb0+XAw64M=; b=AD60of7o2hMzJBUQ3o8Uzp74D2yaanKbfgp5Bqk/YNNRj0dVe/E7326u7D2OQQKano z/6/FJlofR/WQ0VsoTkCGmhFgy47i+RddyNahGbweeNtkH4VWTw0+Ig1hMlBVkzuj/s5 KhGjyOxWvmCDq3Ac99JF8zAk1CL8GxXCPUFsXU7nScwRlTG/zqpR90d+raQGMPxIT1f3 gqnfXNim5GsDbQ/4QPoFO8pphmhN3xK9L0IG0Kq1x5sbmqHNsLXYiKoPvrcZh6Yl22xg 4C8/fBw7ktiyabLAOm2TJ9ViL3dcSjPzOoFZkgrGegpv4zgj38sIVlUIyEEqPNNBf1AI Ugow== X-Gm-Message-State: AOAM530HUMMKTI3UV0Q0VrAUDLPNoDlb3GWEbEJe8m31MwGnZ0nd734v rGoKLx2z2erEZk4diGGZGxCjVg0y+D7NvQ== X-Google-Smtp-Source: ABdhPJzuk84QWs1JcAWwplfZ+wEpT1+a/Jn9jkOuDfgtJdq7sWQKTZmTVAo4jA+X9/TnMtjbfi4m4g== X-Received: by 2002:a17:902:d917:b029:d6:d1b8:5d9a with SMTP id c23-20020a170902d917b02900d6d1b85d9amr3115914plz.72.1604596291680; Thu, 05 Nov 2020 09:11:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-5.2] target/arm: Fix neon VTBL/VTBX for len > 1 Date: Thu, 5 Nov 2020 09:11:26 -0800 Message-Id: <20201105171126.88014-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, Ard Biesheuvel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The helper function did not get updated when we reorganized the vector register file for SVE. Since then, the neon dregs are non-sequential and cannot be simply indexed. At the same time, make the helper function operate on 64-bit quantities so that we do not have to call it twice. Fixes: c39c2b9043e Reported-by: Ard Biesheuvel Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.h | 2 +- target/arm/op_helper.c | 23 +++++++++-------- target/arm/translate-neon.c.inc | 44 +++++++++++---------------------- 3 files changed, 29 insertions(+), 40 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 774d2cddb5..ff8148ddc6 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -245,7 +245,7 @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f3= 2, ptr) DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) -DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32) +DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) =20 DEF_HELPER_3(shl_cc, i32, env, i32, i32) DEF_HELPER_3(shr_cc, i32, env, i32, i32) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index b1065216b2..9bfd6760a0 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -68,21 +68,24 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp= , uint32_t syndrome, cpu_loop_exit_restore(cs, ra); } =20 -uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, - uint32_t maxindex) +uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, + uint64_t ireg, uint64_t def) { - uint32_t val, shift; - uint64_t *table =3D vn; + uint64_t tmp, val =3D 0; + uint32_t maxindex =3D ((desc & 3) + 1) * 8; + uint32_t base_reg =3D desc >> 2; + uint32_t shift, index, reg; =20 - val =3D 0; - for (shift =3D 0; shift < 32; shift +=3D 8) { - uint32_t index =3D (ireg >> shift) & 0xff; + for (shift =3D 0; shift < 64; shift +=3D 8) { + index =3D (ireg >> shift) & 0xff; if (index < maxindex) { - uint32_t tmp =3D (table[index >> 3] >> ((index & 7) << 3)) & 0= xff; - val |=3D tmp << shift; + reg =3D base_reg + (index >> 3); + tmp =3D env->vfp.zregs[reg >> 1].d[reg & 1]; + tmp =3D ((tmp >> ((index & 7) << 3)) & 0xff) << shift; } else { - val |=3D def & (0xff << shift); + tmp =3D def & (0xffull << shift); } + val |=3D tmp; } return val; } diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index 59368cb243..0ae95cb8df 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -2861,9 +2861,8 @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) =20 static bool trans_VTBL(DisasContext *s, arg_VTBL *a) { - int n; - TCGv_i32 tmp, tmp2, tmp3, tmp4; - TCGv_ptr ptr1; + TCGv_i64 val, def; + TCGv_i32 desc; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -2879,43 +2878,30 @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) return true; } =20 - n =3D a->len + 1; - if ((a->vn + n) > 32) { + if ((a->vn + a->len + 1) > 32) { /* * This is UNPREDICTABLE; we choose to UNDEF to avoid the * helper function running off the end of the register file. */ return false; } - n <<=3D 3; - tmp =3D tcg_temp_new_i32(); - if (a->op) { - read_neon_element32(tmp, a->vd, 0, MO_32); - } else { - tcg_gen_movi_i32(tmp, 0); - } - tmp2 =3D tcg_temp_new_i32(); - read_neon_element32(tmp2, a->vm, 0, MO_32); - ptr1 =3D vfp_reg_ptr(true, a->vn); - tmp4 =3D tcg_const_i32(n); - gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4); =20 + desc =3D tcg_const_i32((a->vn << 2) | a->len); + def =3D tcg_temp_new_i64(); if (a->op) { - read_neon_element32(tmp, a->vd, 1, MO_32); + read_neon_element64(def, a->vd, 0, MO_64); } else { - tcg_gen_movi_i32(tmp, 0); + tcg_gen_movi_i64(def, 0); } - tmp3 =3D tcg_temp_new_i32(); - read_neon_element32(tmp3, a->vm, 1, MO_32); - gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp4); - tcg_temp_free_ptr(ptr1); + val =3D tcg_temp_new_i64(); + read_neon_element64(val, a->vm, 0, MO_64); =20 - write_neon_element32(tmp2, a->vd, 0, MO_32); - write_neon_element32(tmp3, a->vd, 1, MO_32); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); + gen_helper_neon_tbl(val, cpu_env, desc, val, def); + write_neon_element64(val, a->vd, 0, MO_64); + + tcg_temp_free_i64(def); + tcg_temp_free_i64(val); + tcg_temp_free_i32(desc); return true; } =20 --=20 2.25.1