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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/26] target/arm: Use neon_element_offset in
neon_load/store_reg
Date: Mon, 2 Nov 2020 17:09:42 +0000
Message-Id: <20201102171005.30690-4-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
These are the only users of neon_reg_offset, so remove that.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 14 ++------------
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index bf0b5cac616..88a926d1df0 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1137,26 +1137,16 @@ static inline long vfp_reg_offset(bool dp, unsigned=
reg)
}
}
=20
-/* Return the offset of a 32-bit piece of a NEON register.
- zero is the least significant end of the register. */
-static inline long
-neon_reg_offset (int reg, int n)
-{
- int sreg;
- sreg =3D reg * 2 + n;
- return vfp_reg_offset(0, sreg);
-}
-
static TCGv_i32 neon_load_reg(int reg, int pass)
{
TCGv_i32 tmp =3D tcg_temp_new_i32();
- tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass));
+ tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32));
return tmp;
}
=20
static void neon_store_reg(int reg, int pass, TCGv_i32 var)
{
- tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass));
+ tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32));
tcg_temp_free_i32(var);
}
=20
--=20
2.20.1