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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 11/26] target/arm: Improve do_prewiden_3d
Date: Mon, 2 Nov 2020 17:09:50 +0000
Message-Id: <20201102171005.30690-12-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
We can use proper widening loads to extend 32-bit inputs,
and skip the "widenfn" step.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030022618.785675-12-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 6 +++
target/arm/translate-neon.c.inc | 66 ++++++++++++++++++---------------
2 files changed, 43 insertions(+), 29 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7611c1f0f15..29ea1eb7811 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1183,6 +1183,12 @@ static void read_neon_element64(TCGv_i64 dest, int r=
eg, int ele, MemOp memop)
long off =3D neon_element_offset(reg, ele, memop);
=20
switch (memop) {
+ case MO_SL:
+ tcg_gen_ld32s_i64(dest, cpu_env, off);
+ break;
+ case MO_UL:
+ tcg_gen_ld32u_i64(dest, cpu_env, off);
+ break;
case MO_Q:
tcg_gen_ld_i64(dest, cpu_env, off);
break;
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.=
inc
index 1c16c56e7ec..59368cb2436 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -1788,11 +1788,10 @@ static bool trans_Vimm_1r(DisasContext *s, arg_1reg=
_imm *a)
static bool do_prewiden_3d(DisasContext *s, arg_3diff *a,
NeonGenWidenFn *widenfn,
NeonGenTwo64OpFn *opfn,
- bool src1_wide)
+ int src1_mop, int src2_mop)
{
/* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW=
) */
TCGv_i64 rn0_64, rn1_64, rm_64;
- TCGv_i32 rm;
=20
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false;
@@ -1804,12 +1803,12 @@ static bool do_prewiden_3d(DisasContext *s, arg_3di=
ff *a,
return false;
}
=20
- if (!widenfn || !opfn) {
+ if (!opfn) {
/* size =3D=3D 3 case, which is an entirely different insn group */
return false;
}
=20
- if ((a->vd & 1) || (src1_wide && (a->vn & 1))) {
+ if ((a->vd & 1) || (src1_mop =3D=3D MO_Q && (a->vn & 1))) {
return false;
}
=20
@@ -1821,40 +1820,48 @@ static bool do_prewiden_3d(DisasContext *s, arg_3di=
ff *a,
rn1_64 =3D tcg_temp_new_i64();
rm_64 =3D tcg_temp_new_i64();
=20
- if (src1_wide) {
- read_neon_element64(rn0_64, a->vn, 0, MO_64);
+ if (src1_mop >=3D 0) {
+ read_neon_element64(rn0_64, a->vn, 0, src1_mop);
} else {
TCGv_i32 tmp =3D tcg_temp_new_i32();
read_neon_element32(tmp, a->vn, 0, MO_32);
widenfn(rn0_64, tmp);
tcg_temp_free_i32(tmp);
}
- rm =3D tcg_temp_new_i32();
- read_neon_element32(rm, a->vm, 0, MO_32);
+ if (src2_mop >=3D 0) {
+ read_neon_element64(rm_64, a->vm, 0, src2_mop);
+ } else {
+ TCGv_i32 tmp =3D tcg_temp_new_i32();
+ read_neon_element32(tmp, a->vm, 0, MO_32);
+ widenfn(rm_64, tmp);
+ tcg_temp_free_i32(tmp);
+ }
=20
- widenfn(rm_64, rm);
- tcg_temp_free_i32(rm);
opfn(rn0_64, rn0_64, rm_64);
=20
/*
* Load second pass inputs before storing the first pass result, to
* avoid incorrect results if a narrow input overlaps with the result.
*/
- if (src1_wide) {
- read_neon_element64(rn1_64, a->vn, 1, MO_64);
+ if (src1_mop >=3D 0) {
+ read_neon_element64(rn1_64, a->vn, 1, src1_mop);
} else {
TCGv_i32 tmp =3D tcg_temp_new_i32();
read_neon_element32(tmp, a->vn, 1, MO_32);
widenfn(rn1_64, tmp);
tcg_temp_free_i32(tmp);
}
- rm =3D tcg_temp_new_i32();
- read_neon_element32(rm, a->vm, 1, MO_32);
+ if (src2_mop >=3D 0) {
+ read_neon_element64(rm_64, a->vm, 1, src2_mop);
+ } else {
+ TCGv_i32 tmp =3D tcg_temp_new_i32();
+ read_neon_element32(tmp, a->vm, 1, MO_32);
+ widenfn(rm_64, tmp);
+ tcg_temp_free_i32(tmp);
+ }
=20
write_neon_element64(rn0_64, a->vd, 0, MO_64);
=20
- widenfn(rm_64, rm);
- tcg_temp_free_i32(rm);
opfn(rn1_64, rn1_64, rm_64);
write_neon_element64(rn1_64, a->vd, 1, MO_64);
=20
@@ -1865,14 +1872,13 @@ static bool do_prewiden_3d(DisasContext *s, arg_3di=
ff *a,
return true;
}
=20
-#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \
+#define DO_PREWIDEN(INSN, S, OP, SRC1WIDE, SIGN) \
static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \
{ \
static NeonGenWidenFn * const widenfn[] =3D { \
gen_helper_neon_widen_##S##8, \
gen_helper_neon_widen_##S##16, \
- tcg_gen_##EXT##_i32_i64, \
- NULL, \
+ NULL, NULL, \
}; \
static NeonGenTwo64OpFn * const addfn[] =3D { \
gen_helper_neon_##OP##l_u16, \
@@ -1880,18 +1886,20 @@ static bool do_prewiden_3d(DisasContext *s, arg_3di=
ff *a,
tcg_gen_##OP##_i64, \
NULL, \
}; \
- return do_prewiden_3d(s, a, widenfn[a->size], \
- addfn[a->size], SRC1WIDE); \
+ int narrow_mop =3D a->size =3D=3D MO_32 ? MO_32 | SIGN : -1; =
\
+ return do_prewiden_3d(s, a, widenfn[a->size], addfn[a->size], \
+ SRC1WIDE ? MO_Q : narrow_mop, \
+ narrow_mop); \
}
=20
-DO_PREWIDEN(VADDL_S, s, ext, add, false)
-DO_PREWIDEN(VADDL_U, u, extu, add, false)
-DO_PREWIDEN(VSUBL_S, s, ext, sub, false)
-DO_PREWIDEN(VSUBL_U, u, extu, sub, false)
-DO_PREWIDEN(VADDW_S, s, ext, add, true)
-DO_PREWIDEN(VADDW_U, u, extu, add, true)
-DO_PREWIDEN(VSUBW_S, s, ext, sub, true)
-DO_PREWIDEN(VSUBW_U, u, extu, sub, true)
+DO_PREWIDEN(VADDL_S, s, add, false, MO_SIGN)
+DO_PREWIDEN(VADDL_U, u, add, false, 0)
+DO_PREWIDEN(VSUBL_S, s, sub, false, MO_SIGN)
+DO_PREWIDEN(VSUBL_U, u, sub, false, 0)
+DO_PREWIDEN(VADDW_S, s, add, true, MO_SIGN)
+DO_PREWIDEN(VADDW_U, u, add, true, 0)
+DO_PREWIDEN(VSUBW_S, s, sub, true, MO_SIGN)
+DO_PREWIDEN(VSUBW_U, u, sub, true, 0)
=20
static bool do_narrow_3d(DisasContext *s, arg_3diff *a,
NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn)
--=20
2.20.1