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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=o8jDI4u3/cANjXLMZiCSLvouwLvybPEhpBDKKscFIa4=; b=Xo4Uo7tqgMe6HV86xqrQzux6yFdjhhDkZTBe3Ictot4b6gSPdW07y0+TQWjw6aoe1F yHz++AjNpBANAF1/ZlHg0iLXBOONtWNYInUaT6l0OgJ67hJWyYUCJMEEMUfmIIVbKdC1 kKhrzB90E+KZRr7worB9YJOlC2npKU6TSD9tpmSlhAW6J2JjvNuANSl0Z4NZDKMrf5h5 ycArCUJi5GOdYTTrVi1L7L7coSqQh59D3wpY51i7abRjGnICOvoWlV11L+7IU838nGsb DylVFp1lsCDwpIA+HrI6Nq2NVCNddGrxGT9JcpfMwEFbOhsmWgPOgf9dqVlBg1EzRcsD hhAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o8jDI4u3/cANjXLMZiCSLvouwLvybPEhpBDKKscFIa4=; b=ijqjq4+1reu4I7m46RwaoMquqZ4IysAZMolLacn/Y6jvxCK+F9Dh0Qr727HUFJmjOQ fvJ15q7QGEWm+GlSVqBWXZZzvad1koaTVPJinX8Mnm26nfvJ+SEXNe9Np74ce6HGQ+WK Gk1sL4DBWDAddL8T9haxlFrxwDVK/dxKYcMWph2lTtp10xhMGK5nDQc6/UfJC80AO/Up jfiFFE5nFFezUyBjbqYKePlSv0zxnXdBZZS/d4pV5Ocf3u5AR4z/D3bz5NFzfcz5no9o C/kVT+772hSePK1TnTrdm1LlNC+rSn/8My1A8+n7HYAzCDQVYA4fxvaKMPr8rprLHIgu MqAA== X-Gm-Message-State: AOAM5338N8VpknvljYufGGYNF06M2E/vDgWjAaioIYkmDr9pOgXCYhet hOMTStlQxKmVvdyJgIYeJLpFB3S+0KYtWg== X-Google-Smtp-Source: ABdhPJwDeP+3bz4ky1xHk31h3QUEW6zCNqzc9eWDqJ/wOG2ukV0aeU1jEMpsvckeHXvRyB98QNR9kA== X-Received: by 2002:a5d:568a:: with SMTP id f10mr21272353wrv.30.1604337009603; Mon, 02 Nov 2020 09:10:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/26] target/arm: Introduce neon_full_reg_offset Date: Mon, 2 Nov 2020 17:09:40 +0000 Message-Id: <20201102171005.30690-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This function makes it clear that we're talking about the whole register, and not the 32-bit piece at index 0. This fixes a bug when running on a big-endian host. Signed-off-by: Richard Henderson Message-id: 20201030022618.785675-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 8 ++++++ target/arm/translate-neon.c.inc | 44 ++++++++++++++++----------------- target/arm/translate-vfp.c.inc | 2 +- 3 files changed, 31 insertions(+), 23 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 38371db5401..1b61e50f9c5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1094,6 +1094,14 @@ static inline void gen_hlt(DisasContext *s, int imm) unallocated_encoding(s); } =20 +/* + * Return the offset of a "full" NEON Dreg. + */ +static long neon_full_reg_offset(unsigned reg) +{ + return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); +} + static inline long vfp_reg_offset(bool dp, unsigned reg) { if (dp) { diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index 4d1a292981b..e259e24c055 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -76,7 +76,7 @@ neon_element_offset(int reg, int element, MemOp size) ofs ^=3D 8 - element_size; } #endif - return neon_reg_offset(reg, 0) + ofs; + return neon_full_reg_offset(reg) + ofs; } =20 static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) @@ -585,12 +585,12 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_= VLD_all_lanes *a) * We cannot write 16 bytes at once because the * destination is unaligned. */ - tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd), 8, 8, tmp); - tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0), - neon_reg_offset(vd, 0), 8, 8); + tcg_gen_gvec_mov(0, neon_full_reg_offset(vd + 1), + neon_full_reg_offset(vd), 8, 8); } else { - tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd), vec_size, vec_size, tmp); } tcg_gen_addi_i32(addr, addr, 1 << size); @@ -691,9 +691,9 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLD= ST_single *a) static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn) { int vec_size =3D a->q ? 16 : 8; - int rd_ofs =3D neon_reg_offset(a->vd, 0); - int rn_ofs =3D neon_reg_offset(a->vn, 0); - int rm_ofs =3D neon_reg_offset(a->vm, 0); + int rd_ofs =3D neon_full_reg_offset(a->vd); + int rn_ofs =3D neon_full_reg_offset(a->vn); + int rm_ofs =3D neon_full_reg_offset(a->vm); =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -1177,8 +1177,8 @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_s= hift *a, GVecGen2iFn *fn) { /* Handle a 2-reg-shift insn which can be vectorized. */ int vec_size =3D a->q ? 16 : 8; - int rd_ofs =3D neon_reg_offset(a->vd, 0); - int rm_ofs =3D neon_reg_offset(a->vm, 0); + int rd_ofs =3D neon_full_reg_offset(a->vd); + int rm_ofs =3D neon_full_reg_offset(a->vm); =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -1620,8 +1620,8 @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift= *a, { /* FP operations in 2-reg-and-shift group */ int vec_size =3D a->q ? 16 : 8; - int rd_ofs =3D neon_reg_offset(a->vd, 0); - int rm_ofs =3D neon_reg_offset(a->vm, 0); + int rd_ofs =3D neon_full_reg_offset(a->vd); + int rm_ofs =3D neon_full_reg_offset(a->vm); TCGv_ptr fpst; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { @@ -1756,7 +1756,7 @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm= *a, return true; } =20 - reg_ofs =3D neon_reg_offset(a->vd, 0); + reg_ofs =3D neon_full_reg_offset(a->vd); vec_size =3D a->q ? 16 : 8; imm =3D asimd_imm_const(a->imm, a->cmode, a->op); =20 @@ -2300,9 +2300,9 @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3di= ff *a) return true; } =20 - tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0), - neon_reg_offset(a->vn, 0), - neon_reg_offset(a->vm, 0), + tcg_gen_gvec_3_ool(neon_full_reg_offset(a->vd), + neon_full_reg_offset(a->vn), + neon_full_reg_offset(a->vm), 16, 16, 0, fn_gvec); return true; } @@ -2445,8 +2445,8 @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2s= calar *a, { /* Two registers and a scalar, using gvec */ int vec_size =3D a->q ? 16 : 8; - int rd_ofs =3D neon_reg_offset(a->vd, 0); - int rn_ofs =3D neon_reg_offset(a->vn, 0); + int rd_ofs =3D neon_full_reg_offset(a->vd); + int rn_ofs =3D neon_full_reg_offset(a->vn); int rm_ofs; int idx; TCGv_ptr fpstatus; @@ -2477,7 +2477,7 @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2s= calar *a, /* a->vm is M:Vm, which encodes both register and index */ idx =3D extract32(a->vm, a->size + 2, 2); a->vm =3D extract32(a->vm, 0, a->size + 2); - rm_ofs =3D neon_reg_offset(a->vm, 0); + rm_ofs =3D neon_full_reg_offset(a->vm); =20 fpstatus =3D fpstatus_ptr(a->size =3D=3D 1 ? FPST_STD_F16 : FPST_STD); tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpstatus, @@ -2923,7 +2923,7 @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VD= UP_scalar *a) return true; } =20 - tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0), + tcg_gen_gvec_dup_mem(a->size, neon_full_reg_offset(a->vd), neon_element_offset(a->vm, a->index, a->size), a->q ? 16 : 8, a->q ? 16 : 8); return true; @@ -3412,8 +3412,8 @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2= misc *a) static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn) { int vec_size =3D a->q ? 16 : 8; - int rd_ofs =3D neon_reg_offset(a->vd, 0); - int rm_ofs =3D neon_reg_offset(a->vm, 0); + int rd_ofs =3D neon_full_reg_offset(a->vd); + int rm_ofs =3D neon_full_reg_offset(a->vm); =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index a7ed9bc81b9..368bae0a73d 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -653,7 +653,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) } =20 tmp =3D load_reg(s, a->rt); - tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0), + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(a->vn), vec_size, vec_size, tmp); tcg_temp_free_i32(tmp); =20 --=20 2.20.1 From nobody Fri May 17 11:58:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337104; cv=none; d=zohomail.com; s=zohoarc; b=YnBKb7r2hrOx/PNHZY8FYG45jABjVQ6Tv/2TZU/s+nM4JW4OFGxAsqtUuzihQD7s/ZrnoddWNTw93gj7o4hGtVYhA6V4mix3LRlA2cWOshJTuTni3TRushg4tPVRkhS/YYgiqj3QuZhiqcloe3bJS8P3wK2q95e/KF+BPnLnJRs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337104; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Yb81K1WgzUECohN6OsmqHKMszy1ABT92E/6OuxF9svY=; b=SLdi78HkXCBmOdhUwp4YPRcbBdcbrRI/s7AnYTDB0fHk3Kp5is2a25X+f0gpwHTIvUHVqEJd9zgW9YD2DaTUnqq3eNhk0KGkGkjihCCie+mn2tsgYNbtSdr8Z6l//cRE6qGrftSKQS17lvee6a5p4r+QvhciOz9qFkdE70sVF/c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16043371045455.120919424688509; Mon, 2 Nov 2020 09:11:44 -0800 (PST) Received: from localhost ([::1]:44078 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdMt-0002Dr-Q8 for importer@patchew.org; Mon, 02 Nov 2020 12:11:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53738) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLT-0000Up-Vu for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:15 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:33116) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLQ-0006N5-Lr for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:15 -0500 Received: by mail-wr1-x435.google.com with SMTP id b8so15524334wrn.0 for ; Mon, 02 Nov 2020 09:10:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Yb81K1WgzUECohN6OsmqHKMszy1ABT92E/6OuxF9svY=; b=wPOpp8VHtXiTgV+myuUd/APwGrjWJXkCfl+7LQ/M/mGBPA+cWcIKovhCiSrQQoT4Io B9vyVJ9NAy5FaPyhfNQ/CBhjJx6mOIdzY7Vp2llaqAixIoQ92WD7mAAmp9Q8C/YvzZWH 7lL1jqT0hPKy3iZ5PzxW+HApRRdafUuGUOs+8IpbxMziHNUdy7esL0R6f8e/D9loVH8N vKh+IIMhB1KXdc/Ldon7Jn+qOnLtlRvlv++dXl78kWzU9rPt9gc/HQrSY5asI09fgmoN ZZ57ANmOGK4uY/IbITHVy/oRODj8MXIC+xz6QpA2JIjPryau48Xvs/clHFZrVK4Eop0q 4GAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Yb81K1WgzUECohN6OsmqHKMszy1ABT92E/6OuxF9svY=; b=GL47vEChyJeGdyQThO8isb8kdeMr9EOUSY/qOzSYeJCjWON/sNtaud5P4sHGlYCdIk /bqTP0scMoRusTU3ZooiZ1DU9EnPOCr/PhlJgLSCRcL7ibCNE0V1xAB0V9qK/+Mtlc8d mH7lwsZFVirWLp89nMu5RnLVmgLJn1URLCX53Wlb/WA9HB4TWHl5JcDmvqxhITfjOokO S48aZAermq5XrmvQ7yv57V1/FlhBwOkNVkj/VU0batfsnIBnKgX3a19omremv7GIShmG rDjodk4U2bf8vXF1RBrCFPizdo0oGPKcT5idS5Q1tSJ6Ga2eXrwyIc0+kOZSlEP8ZfTP WtnA== X-Gm-Message-State: AOAM532zPXx5ojYAS4MMmJyOsKnGd1im3cwGPoe1WZ5zOBxgqS/6h9n+ i/NfouOBNXD3fkCqZMjaVuAI6ni0UGnSug== X-Google-Smtp-Source: ABdhPJzU0na+cw90ic0ZBPvxBB0HWh39emJwGfsunmm8YYbP3UAOLaoBNipUUzDdmp84F+Q1h6Tbig== X-Received: by 2002:adf:81e5:: with SMTP id 92mr21277897wra.411.1604337010949; Mon, 02 Nov 2020 09:10:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/26] target/arm: Move neon_element_offset to translate.c Date: Mon, 2 Nov 2020 17:09:41 +0000 Message-Id: <20201102171005.30690-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This will shortly have users outside of translate-neon.c.inc. Signed-off-by: Richard Henderson Message-id: 20201030022618.785675-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 20 ++++++++++++++++++++ target/arm/translate-neon.c.inc | 19 ------------------- 2 files changed, 20 insertions(+), 19 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 1b61e50f9c5..bf0b5cac616 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1102,6 +1102,26 @@ static long neon_full_reg_offset(unsigned reg) return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); } =20 +/* + * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, + * where 0 is the least significant end of the register. + */ +static long neon_element_offset(int reg, int element, MemOp size) +{ + int element_size =3D 1 << size; + int ofs =3D element * element_size; +#ifdef HOST_WORDS_BIGENDIAN + /* + * Calculate the offset assuming fully little-endian, + * then XOR to account for the order of the 8-byte units. + */ + if (element_size < 8) { + ofs ^=3D 8 - element_size; + } +#endif + return neon_full_reg_offset(reg) + ofs; +} + static inline long vfp_reg_offset(bool dp, unsigned reg) { if (dp) { diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index e259e24c055..96ab2248fcf 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -60,25 +60,6 @@ static inline int neon_3same_fp_size(DisasContext *s, in= t x) #include "decode-neon-ls.c.inc" #include "decode-neon-shared.c.inc" =20 -/* Return the offset of a 2**SIZE piece of a NEON register, at index ELE, - * where 0 is the least significant end of the register. - */ -static inline long -neon_element_offset(int reg, int element, MemOp size) -{ - int element_size =3D 1 << size; - int ofs =3D element * element_size; -#ifdef HOST_WORDS_BIGENDIAN - /* Calculate the offset assuming fully little-endian, - * then XOR to account for the order of the 8-byte units. - */ - if (element_size < 8) { - ofs ^=3D 8 - element_size; - } -#endif - return neon_full_reg_offset(reg) + ofs; -} - static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) { long offset =3D neon_element_offset(reg, ele, mop & MO_SIZE); --=20 2.20.1 From nobody Fri May 17 11:58:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337428; cv=none; d=zohomail.com; s=zohoarc; b=TsVpfDpOwBNqMrGlQbMrchfjO4adyq9gIdUmqNvUwOrbCky144ogbU8OVvEgSjdZjlzhawDUdcyV+0eEFEVmn4RTG6IWho1gBvbZ4osPBJbvjMP0Z3+wwB0qROiCVEfi/i8aLTDWiAg5Oa7MsAos3zVRDq9lqDwdzbn59lDqgus= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337428; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JwYY+dnUWGn92siUF9yWZYm92u30bUmTLinCII/ykAU=; b=SikzR41o4YZ4tEzbql1WNpUjBmG2uqtNhvUJ0VS2usqPomDyDkAuA3TTfKwkh//QlDUBnfWyJ5ZqSNyMWZHDD5XEe8T1le+ytTJheRUGbOcXW8qbP+8qJyWgcw93p/RMKhcs5ZvRhIBCt9Bwgv4xeqUALq20xAPcQWpPX9CbrfM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337428865622.0984382363731; Mon, 2 Nov 2020 09:17:08 -0800 (PST) Received: from localhost ([::1]:60192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdS7-0000lb-Eq for importer@patchew.org; Mon, 02 Nov 2020 12:17:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53734) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLT-0000Ul-TY for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:15 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:43646) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLS-0006NJ-7V for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:15 -0500 Received: by mail-wr1-x442.google.com with SMTP id g12so15468427wrp.10 for ; Mon, 02 Nov 2020 09:10:13 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JwYY+dnUWGn92siUF9yWZYm92u30bUmTLinCII/ykAU=; b=hpg6d4CGarhwSYsLoknXiRwVJjw5j4A7JxuIb/gyxyUjoe9INUmu37ViIPfasid55R 9CBqeJfpmhBxRI2zRsCFc0NbTSVVy5fCe6QpfU8h+RNjkm/DPGU/dFy4lRuQLWD9l6FL AjPvpv9dPJsZyYp0Ebkm2I69higHqPoQfW2dRA0SGk58hjd2VFFt82hZgZQvxku1YLrz w4//zIu3mMaKNy/GPUGo8YLyLjGEPdOLcZYncdnT2+erBaQtQdUMiMuEZxGhhElU7wKU K9R7KFLsIU8sKysi9v6DPgWKc8Gn1fEFEmrsT3is501rWYHG5NwAmSrU7RvMjCMDhYEZ pU0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JwYY+dnUWGn92siUF9yWZYm92u30bUmTLinCII/ykAU=; b=HJ44jooI/GPY26NPlGCKOZM1sgY6Ap5u7nfTuDq9EJMhLk8KWrbA1oVkVb6OwNYkLQ MUsujxZqH1ieZhk6Z1fxNnHnlGLOrzPqCXCHLSXaFNQG2YeRqmp4rDYKEDUbbQzQ/8XM BvGnJcr6mgp2cf8o3J+gBnsNS/wLG0GEgmQI/xafG6quMwhmFNgEaEdvtHIVtcCHkHJf /LO3u83DMlL1wdVsuyd6q0vS4oeMjoj6gptSYFiW+9+PZbsLiC2pz/rGs7g8c+6BPZsd ts5HL3MIpNOH4/CSy/vz7PmYKz5nKevhvsrjcgI/RRYnThJ+BqXUrgMBGNH71dfW02xH 64rQ== X-Gm-Message-State: AOAM531p1+jJdHVWcjZFIv1AHhBXjBqAIrrGmn6RdlDN2/NQ7Se8Mmtx LvZVmpIgd4pSTMN+ON0cId34k/eo7aCb3Q== X-Google-Smtp-Source: ABdhPJxMNaoa3Wv7BHpowglcKBv8MJk9URbNh8Xuk9/zscigs/5yFFKfzLT1oCozGyDXHtNf5ulVwg== X-Received: by 2002:adf:db51:: with SMTP id f17mr21218044wrj.126.1604337012379; Mon, 02 Nov 2020 09:10:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/26] target/arm: Use neon_element_offset in neon_load/store_reg Date: Mon, 2 Nov 2020 17:09:42 +0000 Message-Id: <20201102171005.30690-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson These are the only users of neon_reg_offset, so remove that. Signed-off-by: Richard Henderson Message-id: 20201030022618.785675-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index bf0b5cac616..88a926d1df0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1137,26 +1137,16 @@ static inline long vfp_reg_offset(bool dp, unsigned= reg) } } =20 -/* Return the offset of a 32-bit piece of a NEON register. - zero is the least significant end of the register. */ -static inline long -neon_reg_offset (int reg, int n) -{ - int sreg; - sreg =3D reg * 2 + n; - return vfp_reg_offset(0, sreg); -} - static TCGv_i32 neon_load_reg(int reg, int pass) { TCGv_i32 tmp =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp, cpu_env, neon_reg_offset(reg, pass)); + tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32)); return tmp; } =20 static void neon_store_reg(int reg, int pass, TCGv_i32 var) { - tcg_gen_st_i32(var, cpu_env, neon_reg_offset(reg, pass)); + tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32)); tcg_temp_free_i32(var); } =20 --=20 2.20.1 From nobody Fri May 17 11:58:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337107; cv=none; d=zohomail.com; s=zohoarc; b=cOoHbj68PofIg9kuy0IgD6DL5ZCWgUM9985VkU+VphhXaoEfyt3/zAybWxtqKnIrKH2rTpvyacbcn5aojPh/HRMr4ammtl+inlcQxfsyEKmkJCQApodqImwQlgUShslzNpppvNKt57NG3NzbLjPZUHVQh3YpRSJTvFiMeVumzxM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337107; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wRbK+boMFOA38V3XwqhrElTFyf+xXduXL37Qdsdc3+E=; b=j7/cml9bejCO5gYWXbCc+4/2F5VxGInp8+ebpxoKKfbfCi7tSDqKocklFSGNgq/pcPbsdvpA3EPePi2vVyd/u8HL4NS0qo3B5wj1pu9B+S2YqbVvSnOCf5RQR2qu5q/9z/pD2Ioifr1Ir/V01I9QQkFWXw37bk/20PVszdv0870= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337107366892.5197879548175; Mon, 2 Nov 2020 09:11:47 -0800 (PST) Received: from localhost ([::1]:44334 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdMw-0002KH-IM for importer@patchew.org; Mon, 02 Nov 2020 12:11:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53744) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLV-0000WD-11 for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:17 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:51467) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLT-0006O2-8p for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:16 -0500 Received: by mail-wm1-x342.google.com with SMTP id v5so10135949wmh.1 for ; Mon, 02 Nov 2020 09:10:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wRbK+boMFOA38V3XwqhrElTFyf+xXduXL37Qdsdc3+E=; b=mCOSqn7N2zqE0t8RHHsOBxiYKyZhLu3HKkJHxB2A4tIInWRsJq3gqNkBBzl42ktEDi V6xlYqUshVqNcAVJHqNwatEb6vz8Xi+WDXI4KfekSPk/hjTR5xmTOdx2vBFrQTlVJl33 PswG5qs1fRbBst+6/FtFB5ddHuSZKj8ZZhKfCnyMesbT3RnGC1yrsHdZbr3ApX2OD8cE BLIAl3bpwy3+umQaYEk8skKY2xXGX7rrgYxAvrlc9SFMly9undYCMl9myimP1Vq/mE8A RJx65nzW3tQ2tJ/OZCqaUDN6UsBqUw6dvqueXTqdzoH/Tv+tj/5YGVKueG8h7DplkJFI A+zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wRbK+boMFOA38V3XwqhrElTFyf+xXduXL37Qdsdc3+E=; b=ArXQeXKWeRYqXsSBCTlyC5rV+3pykdaWMwutptS3ciIW+n1OULtUFcq4EMVU249fcz IHe5w2213bUuhW10MlZGtXvL2rxcPZeOH237+X1+OH12xru+Rl9evqT9BeMnl4Ld86it 2PVNLWtaMZ751Uh8b5t+Xyzpfm3xJu0IXfCYGPSqDvqsF9yqs+koilFPkPHuHYiropLz 6MVAv3msXMrPw2fS0L65HFj4trUQiRJhTI5SHeMCWUdrdC3Ednl7/gTJ9zaHgjEv9d2W rBDviAxfu5J7Di6PsfpaQFfQoQiD3lofJiHp6uMY9Vj40obft2IeS62ZfqtiM9LNJ1xT Ll8g== X-Gm-Message-State: AOAM5323L9HUDC9vAodMz8w5UtP+H45Gr47zHHiRybIn6QaYczogBn/b 5DqK1zEhyZbNmGJAaP8r83y596yXdY2VWA== X-Google-Smtp-Source: ABdhPJy/zkVJjO0BuXxvKTWJ84+nJ7OlSMtTKHTbsdGSP6yxsHDZUeqBzu7yDDf2/mUCxjd+XfMwww== X-Received: by 2002:a1c:ed0b:: with SMTP id l11mr18314708wmh.46.1604337013616; Mon, 02 Nov 2020 09:10:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/26] target/arm: Use neon_element_offset in vfp_reg_offset Date: Mon, 2 Nov 2020 17:09:43 +0000 Message-Id: <20201102171005.30690-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This seems a bit more readable than using offsetof CPU_DoubleU. Signed-off-by: Richard Henderson Message-id: 20201030022618.785675-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 88a926d1df0..88ded4ac2c0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1122,18 +1122,13 @@ static long neon_element_offset(int reg, int elemen= t, MemOp size) return neon_full_reg_offset(reg) + ofs; } =20 -static inline long vfp_reg_offset(bool dp, unsigned reg) +/* Return the offset of a VFP Dreg (dp =3D true) or VFP Sreg (dp =3D false= ). */ +static long vfp_reg_offset(bool dp, unsigned reg) { if (dp) { - return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); + return neon_element_offset(reg, 0, MO_64); } else { - long ofs =3D offsetof(CPUARMState, vfp.zregs[reg >> 2].d[(reg >> 1= ) & 1]); - if (reg & 1) { - ofs +=3D offsetof(CPU_DoubleU, l.upper); - } else { - ofs +=3D offsetof(CPU_DoubleU, l.lower); - } - return ofs; + return neon_element_offset(reg >> 1, reg & 1, MO_32); } } =20 --=20 2.20.1 From nobody Fri May 17 11:58:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337437; cv=none; d=zohomail.com; s=zohoarc; b=F7lZys5pHpFD4josNx8zn87CDTDRTX9DNWEZAl17IcnOJDrFnnwiryQWlUIQJ7DpWr6D10jYXtzZ7EyqI6ZkxgF4JDyyK3GKAgRyjaeTORFtDOPloImFbjq3HwEoLgQC7HAjo3YWip1q7SbbjPEJ5sefHnz4UdK+DXEF9Bh3CrE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337437; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=se50iPWBZuwIiT5vz8iDmMRFw8f3KT3wtFgjmCqpe7k=; b=eFmyU2c6rXBb8WPa/teTONn4K1QBTmUPGx8dp67hZkq8RIy0V9/E1EbCHe+4VBBEZzZwinc2KU0Ekn8H4WN6l3rianjIjJi+a3gr/cxo6Xcco8ENnLK8EQdYdqiClRt7mEFocDvZ+zBx1K/ZyPTfWpkuE52rvM3ZEIq0LhwQxt0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337437372320.01451967869434; Mon, 2 Nov 2020 09:17:17 -0800 (PST) Received: from localhost ([::1]:60904 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdSG-00014Q-7N for importer@patchew.org; Mon, 02 Nov 2020 12:17:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53800) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLZ-0000gT-2g for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:21 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:36205) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLV-0006Oq-24 for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:20 -0500 Received: by mail-wr1-x42c.google.com with SMTP id x7so15519074wrl.3 for ; Mon, 02 Nov 2020 09:10:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=se50iPWBZuwIiT5vz8iDmMRFw8f3KT3wtFgjmCqpe7k=; b=ACmOFEDypReFHoWRcXyLUR3Tw4qCS6bDN5YNGqIQo+8uVkOY2vO83SU2COdnXTRulH ZSZcVLVw5hgGGuwPO25W4LZZa116WX/ooIJmxhrGeAZKlHZ6KMwlZckADKfMtkbmiw0s wQ9nlaQ5DwrpLETdsUJqV3355bf1u8JZNDwZD+WlFPM1poUpiA339qN2KMfXcHcO1Xt7 znfM8GKXpWH2YVuj1UoKkL6/scMkN/VPa0j0kZFMzrqaWUBnsZ4fBrbD5E7hrMbGVyve UTG2/n32rrHg3dDeO7wzWykLw4GhL8NIaLJK3uv6sKFia7CDUjm9g7udBkgaTEMcjzup 0zUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=se50iPWBZuwIiT5vz8iDmMRFw8f3KT3wtFgjmCqpe7k=; b=F7oxZFBQAVMPU8WH1RLXfI554L0pqBHjTcE+0NAlpFomag5YfcssknA9YFucxFa8Lr 5VgCj59g8x3Hsm4I8ypFCSaJkiqc+8tGOGhE/Oh7Oz+H1bInqZ/d1sJutbrSUG9N7cqX VpH5fpQsaId2uVW8reKCbCFUJxS+wKcJ/wsklGHP4zZPKehnjHZuu/78pj0oEeIcjzdh Vyti9nKYjKhWNH98YryLzjL/Z/uWjYM4RPxgMlWlldThQt+D3TZcpkSE2d6yiIM40qG5 isWA5EwOg6k/1/nzIKFyMtT8lv94gY0M6B3h+yO9JfQmoatGp4YJtP19U+t99/8wTpf6 uZtg== X-Gm-Message-State: AOAM5303aU4G8k3VRSIzbhaTXcklG5MwOgzLSAozJ0gLQipynjnA7afE Y7fm0bRxtfnmYyiZmjBUWuz5iPOFWYGAzw== X-Google-Smtp-Source: ABdhPJz0lPYz55FsF/XmnH/qTJLjelhqgfsMP4Vg+I84DzXAdZugEM8emzMzsJ5jgM7y/kfqaqX83Q== X-Received: by 2002:a5d:534d:: with SMTP id t13mr20581299wrv.69.1604337014893; Mon, 02 Nov 2020 09:10:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/26] target/arm: Add read/write_neon_element32 Date: Mon, 2 Nov 2020 17:09:44 +0000 Message-Id: <20201102171005.30690-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Model these off the aa64 read/write_vec_element functions. Use it within translate-neon.c.inc. The new functions do not allocate or free temps, so this rearranges the calling code a bit. Signed-off-by: Richard Henderson Message-id: 20201030022618.785675-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 26 ++++ target/arm/translate-neon.c.inc | 256 ++++++++++++++++++++------------ 2 files changed, 183 insertions(+), 99 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 88ded4ac2c0..0ed9eab0b0d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1165,6 +1165,32 @@ static inline void neon_store_reg32(TCGv_i32 var, in= t reg) tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); } =20 +static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp siz= e) +{ + long off =3D neon_element_offset(reg, ele, size); + + switch (size) { + case MO_32: + tcg_gen_ld_i32(dest, cpu_env, off); + break; + default: + g_assert_not_reached(); + } +} + +static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp siz= e) +{ + long off =3D neon_element_offset(reg, ele, size); + + switch (size) { + case MO_32: + tcg_gen_st_i32(src, cpu_env, off); + break; + default: + g_assert_not_reached(); + } +} + static TCGv_ptr vfp_reg_ptr(bool dp, int reg) { TCGv_ptr ret =3D tcg_temp_new_ptr(); diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index 96ab2248fcf..549381703ea 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -956,18 +956,24 @@ static bool do_3same_pair(DisasContext *s, arg_3same = *a, NeonGenTwoOpFn *fn) * early. Since Q is 0 there are always just two passes, so instead * of a complicated loop over each pass we just unroll. */ - tmp =3D neon_load_reg(a->vn, 0); - tmp2 =3D neon_load_reg(a->vn, 1); + tmp =3D tcg_temp_new_i32(); + tmp2 =3D tcg_temp_new_i32(); + tmp3 =3D tcg_temp_new_i32(); + + read_neon_element32(tmp, a->vn, 0, MO_32); + read_neon_element32(tmp2, a->vn, 1, MO_32); fn(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); =20 - tmp3 =3D neon_load_reg(a->vm, 0); - tmp2 =3D neon_load_reg(a->vm, 1); + read_neon_element32(tmp3, a->vm, 0, MO_32); + read_neon_element32(tmp2, a->vm, 1, MO_32); fn(tmp3, tmp3, tmp2); - tcg_temp_free_i32(tmp2); =20 - neon_store_reg(a->vd, 0, tmp); - neon_store_reg(a->vd, 1, tmp3); + write_neon_element32(tmp, a->vd, 0, MO_32); + write_neon_element32(tmp3, a->vd, 1, MO_32); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp3); return true; } =20 @@ -1275,7 +1281,7 @@ static bool do_2shift_env_32(DisasContext *s, arg_2re= g_shift *a, * 2-reg-and-shift operations, size < 3 case, where the * helper needs to be passed cpu_env. */ - TCGv_i32 constimm; + TCGv_i32 constimm, tmp; int pass; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { @@ -1301,12 +1307,14 @@ static bool do_2shift_env_32(DisasContext *s, arg_2= reg_shift *a, * by immediate using the variable shift operations. */ constimm =3D tcg_const_i32(dup_const(a->size, a->shift)); + tmp =3D tcg_temp_new_i32(); =20 for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { - TCGv_i32 tmp =3D neon_load_reg(a->vm, pass); + read_neon_element32(tmp, a->vm, pass, MO_32); fn(tmp, cpu_env, tmp, constimm); - neon_store_reg(a->vd, pass, tmp); + write_neon_element32(tmp, a->vd, pass, MO_32); } + tcg_temp_free_i32(tmp); tcg_temp_free_i32(constimm); return true; } @@ -1364,21 +1372,21 @@ static bool do_2shift_narrow_64(DisasContext *s, ar= g_2reg_shift *a, constimm =3D tcg_const_i64(-a->shift); rm1 =3D tcg_temp_new_i64(); rm2 =3D tcg_temp_new_i64(); + rd =3D tcg_temp_new_i32(); =20 /* Load both inputs first to avoid potential overwrite if rm =3D=3D rd= */ neon_load_reg64(rm1, a->vm); neon_load_reg64(rm2, a->vm + 1); =20 shiftfn(rm1, rm1, constimm); - rd =3D tcg_temp_new_i32(); narrowfn(rd, cpu_env, rm1); - neon_store_reg(a->vd, 0, rd); + write_neon_element32(rd, a->vd, 0, MO_32); =20 shiftfn(rm2, rm2, constimm); - rd =3D tcg_temp_new_i32(); narrowfn(rd, cpu_env, rm2); - neon_store_reg(a->vd, 1, rd); + write_neon_element32(rd, a->vd, 1, MO_32); =20 + tcg_temp_free_i32(rd); tcg_temp_free_i64(rm1); tcg_temp_free_i64(rm2); tcg_temp_free_i64(constimm); @@ -1428,10 +1436,14 @@ static bool do_2shift_narrow_32(DisasContext *s, ar= g_2reg_shift *a, constimm =3D tcg_const_i32(imm); =20 /* Load all inputs first to avoid potential overwrite */ - rm1 =3D neon_load_reg(a->vm, 0); - rm2 =3D neon_load_reg(a->vm, 1); - rm3 =3D neon_load_reg(a->vm + 1, 0); - rm4 =3D neon_load_reg(a->vm + 1, 1); + rm1 =3D tcg_temp_new_i32(); + rm2 =3D tcg_temp_new_i32(); + rm3 =3D tcg_temp_new_i32(); + rm4 =3D tcg_temp_new_i32(); + read_neon_element32(rm1, a->vm, 0, MO_32); + read_neon_element32(rm2, a->vm, 1, MO_32); + read_neon_element32(rm3, a->vm, 2, MO_32); + read_neon_element32(rm4, a->vm, 3, MO_32); rtmp =3D tcg_temp_new_i64(); =20 shiftfn(rm1, rm1, constimm); @@ -1441,7 +1453,8 @@ static bool do_2shift_narrow_32(DisasContext *s, arg_= 2reg_shift *a, tcg_temp_free_i32(rm2); =20 narrowfn(rm1, cpu_env, rtmp); - neon_store_reg(a->vd, 0, rm1); + write_neon_element32(rm1, a->vd, 0, MO_32); + tcg_temp_free_i32(rm1); =20 shiftfn(rm3, rm3, constimm); shiftfn(rm4, rm4, constimm); @@ -1452,7 +1465,8 @@ static bool do_2shift_narrow_32(DisasContext *s, arg_= 2reg_shift *a, =20 narrowfn(rm3, cpu_env, rtmp); tcg_temp_free_i64(rtmp); - neon_store_reg(a->vd, 1, rm3); + write_neon_element32(rm3, a->vd, 1, MO_32); + tcg_temp_free_i32(rm3); return true; } =20 @@ -1553,8 +1567,10 @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_s= hift *a, widen_mask =3D dup_const(a->size + 1, widen_mask); } =20 - rm0 =3D neon_load_reg(a->vm, 0); - rm1 =3D neon_load_reg(a->vm, 1); + rm0 =3D tcg_temp_new_i32(); + rm1 =3D tcg_temp_new_i32(); + read_neon_element32(rm0, a->vm, 0, MO_32); + read_neon_element32(rm1, a->vm, 1, MO_32); tmp =3D tcg_temp_new_i64(); =20 widenfn(tmp, rm0); @@ -1808,11 +1824,13 @@ static bool do_prewiden_3d(DisasContext *s, arg_3di= ff *a, if (src1_wide) { neon_load_reg64(rn0_64, a->vn); } else { - TCGv_i32 tmp =3D neon_load_reg(a->vn, 0); + TCGv_i32 tmp =3D tcg_temp_new_i32(); + read_neon_element32(tmp, a->vn, 0, MO_32); widenfn(rn0_64, tmp); tcg_temp_free_i32(tmp); } - rm =3D neon_load_reg(a->vm, 0); + rm =3D tcg_temp_new_i32(); + read_neon_element32(rm, a->vm, 0, MO_32); =20 widenfn(rm_64, rm); tcg_temp_free_i32(rm); @@ -1825,11 +1843,13 @@ static bool do_prewiden_3d(DisasContext *s, arg_3di= ff *a, if (src1_wide) { neon_load_reg64(rn1_64, a->vn + 1); } else { - TCGv_i32 tmp =3D neon_load_reg(a->vn, 1); + TCGv_i32 tmp =3D tcg_temp_new_i32(); + read_neon_element32(tmp, a->vn, 1, MO_32); widenfn(rn1_64, tmp); tcg_temp_free_i32(tmp); } - rm =3D neon_load_reg(a->vm, 1); + rm =3D tcg_temp_new_i32(); + read_neon_element32(rm, a->vm, 1, MO_32); =20 neon_store_reg64(rn0_64, a->vd); =20 @@ -1922,9 +1942,11 @@ static bool do_narrow_3d(DisasContext *s, arg_3diff = *a, =20 narrowfn(rd1, rn_64); =20 - neon_store_reg(a->vd, 0, rd0); - neon_store_reg(a->vd, 1, rd1); + write_neon_element32(rd0, a->vd, 0, MO_32); + write_neon_element32(rd1, a->vd, 1, MO_32); =20 + tcg_temp_free_i32(rd0); + tcg_temp_free_i32(rd1); tcg_temp_free_i64(rn_64); tcg_temp_free_i64(rm_64); =20 @@ -1999,14 +2021,14 @@ static bool do_long_3d(DisasContext *s, arg_3diff *= a, rd0 =3D tcg_temp_new_i64(); rd1 =3D tcg_temp_new_i64(); =20 - rn =3D neon_load_reg(a->vn, 0); - rm =3D neon_load_reg(a->vm, 0); + rn =3D tcg_temp_new_i32(); + rm =3D tcg_temp_new_i32(); + read_neon_element32(rn, a->vn, 0, MO_32); + read_neon_element32(rm, a->vm, 0, MO_32); opfn(rd0, rn, rm); - tcg_temp_free_i32(rn); - tcg_temp_free_i32(rm); =20 - rn =3D neon_load_reg(a->vn, 1); - rm =3D neon_load_reg(a->vm, 1); + read_neon_element32(rn, a->vn, 1, MO_32); + read_neon_element32(rm, a->vm, 1, MO_32); opfn(rd1, rn, rm); tcg_temp_free_i32(rn); tcg_temp_free_i32(rm); @@ -2308,16 +2330,16 @@ static void gen_neon_dup_high16(TCGv_i32 var) =20 static inline TCGv_i32 neon_get_scalar(int size, int reg) { - TCGv_i32 tmp; - if (size =3D=3D 1) { - tmp =3D neon_load_reg(reg & 7, reg >> 4); + TCGv_i32 tmp =3D tcg_temp_new_i32(); + if (size =3D=3D MO_16) { + read_neon_element32(tmp, reg & 7, reg >> 4, MO_32); if (reg & 8) { gen_neon_dup_high16(tmp); } else { gen_neon_dup_low16(tmp); } } else { - tmp =3D neon_load_reg(reg & 15, reg >> 4); + read_neon_element32(tmp, reg & 15, reg >> 4, MO_32); } return tmp; } @@ -2331,7 +2353,7 @@ static bool do_2scalar(DisasContext *s, arg_2scalar *= a, * perform an accumulation operation of that result into the * destination. */ - TCGv_i32 scalar; + TCGv_i32 scalar, tmp; int pass; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { @@ -2358,17 +2380,20 @@ static bool do_2scalar(DisasContext *s, arg_2scalar= *a, } =20 scalar =3D neon_get_scalar(a->size, a->vm); + tmp =3D tcg_temp_new_i32(); =20 for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { - TCGv_i32 tmp =3D neon_load_reg(a->vn, pass); + read_neon_element32(tmp, a->vn, pass, MO_32); opfn(tmp, tmp, scalar); if (accfn) { - TCGv_i32 rd =3D neon_load_reg(a->vd, pass); + TCGv_i32 rd =3D tcg_temp_new_i32(); + read_neon_element32(rd, a->vd, pass, MO_32); accfn(tmp, rd, tmp); tcg_temp_free_i32(rd); } - neon_store_reg(a->vd, pass, tmp); + write_neon_element32(tmp, a->vd, pass, MO_32); } + tcg_temp_free_i32(tmp); tcg_temp_free_i32(scalar); return true; } @@ -2523,7 +2548,7 @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2sca= lar *a, * performs a kind of fused op-then-accumulate using a helper * function that takes all of rd, rn and the scalar at once. */ - TCGv_i32 scalar; + TCGv_i32 scalar, rn, rd; int pass; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { @@ -2554,14 +2579,17 @@ static bool do_vqrdmlah_2sc(DisasContext *s, arg_2s= calar *a, } =20 scalar =3D neon_get_scalar(a->size, a->vm); + rn =3D tcg_temp_new_i32(); + rd =3D tcg_temp_new_i32(); =20 for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { - TCGv_i32 rn =3D neon_load_reg(a->vn, pass); - TCGv_i32 rd =3D neon_load_reg(a->vd, pass); + read_neon_element32(rn, a->vn, pass, MO_32); + read_neon_element32(rd, a->vd, pass, MO_32); opfn(rd, cpu_env, rn, scalar, rd); - tcg_temp_free_i32(rn); - neon_store_reg(a->vd, pass, rd); + write_neon_element32(rd, a->vd, pass, MO_32); } + tcg_temp_free_i32(rn); + tcg_temp_free_i32(rd); tcg_temp_free_i32(scalar); =20 return true; @@ -2628,12 +2656,12 @@ static bool do_2scalar_long(DisasContext *s, arg_2s= calar *a, scalar =3D neon_get_scalar(a->size, a->vm); =20 /* Load all inputs before writing any outputs, in case of overlap */ - rn =3D neon_load_reg(a->vn, 0); + rn =3D tcg_temp_new_i32(); + read_neon_element32(rn, a->vn, 0, MO_32); rn0_64 =3D tcg_temp_new_i64(); opfn(rn0_64, rn, scalar); - tcg_temp_free_i32(rn); =20 - rn =3D neon_load_reg(a->vn, 1); + read_neon_element32(rn, a->vn, 1, MO_32); rn1_64 =3D tcg_temp_new_i64(); opfn(rn1_64, rn, scalar); tcg_temp_free_i32(rn); @@ -2857,30 +2885,34 @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) return false; } n <<=3D 3; + tmp =3D tcg_temp_new_i32(); if (a->op) { - tmp =3D neon_load_reg(a->vd, 0); + read_neon_element32(tmp, a->vd, 0, MO_32); } else { - tmp =3D tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, 0); } - tmp2 =3D neon_load_reg(a->vm, 0); + tmp2 =3D tcg_temp_new_i32(); + read_neon_element32(tmp2, a->vm, 0, MO_32); ptr1 =3D vfp_reg_ptr(true, a->vn); tmp4 =3D tcg_const_i32(n); gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4); - tcg_temp_free_i32(tmp); + if (a->op) { - tmp =3D neon_load_reg(a->vd, 1); + read_neon_element32(tmp, a->vd, 1, MO_32); } else { - tmp =3D tcg_temp_new_i32(); tcg_gen_movi_i32(tmp, 0); } - tmp3 =3D neon_load_reg(a->vm, 1); + tmp3 =3D tcg_temp_new_i32(); + read_neon_element32(tmp3, a->vm, 1, MO_32); gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4); + tcg_temp_free_i32(tmp); tcg_temp_free_i32(tmp4); tcg_temp_free_ptr(ptr1); - neon_store_reg(a->vd, 0, tmp2); - neon_store_reg(a->vd, 1, tmp3); - tcg_temp_free_i32(tmp); + + write_neon_element32(tmp2, a->vd, 0, MO_32); + write_neon_element32(tmp3, a->vd, 1, MO_32); + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp3); return true; } =20 @@ -2913,6 +2945,7 @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VD= UP_scalar *a) static bool trans_VREV64(DisasContext *s, arg_VREV64 *a) { int pass, half; + TCGv_i32 tmp[2]; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -2936,11 +2969,12 @@ static bool trans_VREV64(DisasContext *s, arg_VREV6= 4 *a) return true; } =20 - for (pass =3D 0; pass < (a->q ? 2 : 1); pass++) { - TCGv_i32 tmp[2]; + tmp[0] =3D tcg_temp_new_i32(); + tmp[1] =3D tcg_temp_new_i32(); =20 + for (pass =3D 0; pass < (a->q ? 2 : 1); pass++) { for (half =3D 0; half < 2; half++) { - tmp[half] =3D neon_load_reg(a->vm, pass * 2 + half); + read_neon_element32(tmp[half], a->vm, pass * 2 + half, MO_32); switch (a->size) { case 0: tcg_gen_bswap32_i32(tmp[half], tmp[half]); @@ -2954,9 +2988,12 @@ static bool trans_VREV64(DisasContext *s, arg_VREV64= *a) g_assert_not_reached(); } } - neon_store_reg(a->vd, pass * 2, tmp[1]); - neon_store_reg(a->vd, pass * 2 + 1, tmp[0]); + write_neon_element32(tmp[1], a->vd, pass * 2, MO_32); + write_neon_element32(tmp[0], a->vd, pass * 2 + 1, MO_32); } + + tcg_temp_free_i32(tmp[0]); + tcg_temp_free_i32(tmp[1]); return true; } =20 @@ -3001,12 +3038,14 @@ static bool do_2misc_pairwise(DisasContext *s, arg_= 2misc *a, rm0_64 =3D tcg_temp_new_i64(); rm1_64 =3D tcg_temp_new_i64(); rd_64 =3D tcg_temp_new_i64(); - tmp =3D neon_load_reg(a->vm, pass * 2); + + tmp =3D tcg_temp_new_i32(); + read_neon_element32(tmp, a->vm, pass * 2, MO_32); widenfn(rm0_64, tmp); - tcg_temp_free_i32(tmp); - tmp =3D neon_load_reg(a->vm, pass * 2 + 1); + read_neon_element32(tmp, a->vm, pass * 2 + 1, MO_32); widenfn(rm1_64, tmp); tcg_temp_free_i32(tmp); + opfn(rd_64, rm0_64, rm1_64); tcg_temp_free_i64(rm0_64); tcg_temp_free_i64(rm1_64); @@ -3219,8 +3258,10 @@ static bool do_vmovn(DisasContext *s, arg_2misc *a, narrowfn(rd0, cpu_env, rm); neon_load_reg64(rm, a->vm + 1); narrowfn(rd1, cpu_env, rm); - neon_store_reg(a->vd, 0, rd0); - neon_store_reg(a->vd, 1, rd1); + write_neon_element32(rd0, a->vd, 0, MO_32); + write_neon_element32(rd1, a->vd, 1, MO_32); + tcg_temp_free_i32(rd0); + tcg_temp_free_i32(rd1); tcg_temp_free_i64(rm); return true; } @@ -3277,9 +3318,11 @@ static bool trans_VSHLL(DisasContext *s, arg_2misc *= a) } =20 rd =3D tcg_temp_new_i64(); + rm0 =3D tcg_temp_new_i32(); + rm1 =3D tcg_temp_new_i32(); =20 - rm0 =3D neon_load_reg(a->vm, 0); - rm1 =3D neon_load_reg(a->vm, 1); + read_neon_element32(rm0, a->vm, 0, MO_32); + read_neon_element32(rm1, a->vm, 1, MO_32); =20 widenfn(rd, rm0); tcg_gen_shli_i64(rd, rd, 8 << a->size); @@ -3320,21 +3363,25 @@ static bool trans_VCVT_F16_F32(DisasContext *s, arg= _2misc *a) =20 fpst =3D fpstatus_ptr(FPST_STD); ahp =3D get_ahp_flag(); - tmp =3D neon_load_reg(a->vm, 0); + tmp =3D tcg_temp_new_i32(); + read_neon_element32(tmp, a->vm, 0, MO_32); gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); - tmp2 =3D neon_load_reg(a->vm, 1); + tmp2 =3D tcg_temp_new_i32(); + read_neon_element32(tmp2, a->vm, 1, MO_32); gen_helper_vfp_fcvt_f32_to_f16(tmp2, tmp2, fpst, ahp); tcg_gen_shli_i32(tmp2, tmp2, 16); tcg_gen_or_i32(tmp2, tmp2, tmp); - tcg_temp_free_i32(tmp); - tmp =3D neon_load_reg(a->vm, 2); + read_neon_element32(tmp, a->vm, 2, MO_32); gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp); - tmp3 =3D neon_load_reg(a->vm, 3); - neon_store_reg(a->vd, 0, tmp2); + tmp3 =3D tcg_temp_new_i32(); + read_neon_element32(tmp3, a->vm, 3, MO_32); + write_neon_element32(tmp2, a->vd, 0, MO_32); + tcg_temp_free_i32(tmp2); gen_helper_vfp_fcvt_f32_to_f16(tmp3, tmp3, fpst, ahp); tcg_gen_shli_i32(tmp3, tmp3, 16); tcg_gen_or_i32(tmp3, tmp3, tmp); - neon_store_reg(a->vd, 1, tmp3); + write_neon_element32(tmp3, a->vd, 1, MO_32); + tcg_temp_free_i32(tmp3); tcg_temp_free_i32(tmp); tcg_temp_free_i32(ahp); tcg_temp_free_ptr(fpst); @@ -3369,21 +3416,25 @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg= _2misc *a) fpst =3D fpstatus_ptr(FPST_STD); ahp =3D get_ahp_flag(); tmp3 =3D tcg_temp_new_i32(); - tmp =3D neon_load_reg(a->vm, 0); - tmp2 =3D neon_load_reg(a->vm, 1); + tmp2 =3D tcg_temp_new_i32(); + tmp =3D tcg_temp_new_i32(); + read_neon_element32(tmp, a->vm, 0, MO_32); + read_neon_element32(tmp2, a->vm, 1, MO_32); tcg_gen_ext16u_i32(tmp3, tmp); gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); - neon_store_reg(a->vd, 0, tmp3); + write_neon_element32(tmp3, a->vd, 0, MO_32); tcg_gen_shri_i32(tmp, tmp, 16); gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp); - neon_store_reg(a->vd, 1, tmp); - tmp3 =3D tcg_temp_new_i32(); + write_neon_element32(tmp, a->vd, 1, MO_32); + tcg_temp_free_i32(tmp); tcg_gen_ext16u_i32(tmp3, tmp2); gen_helper_vfp_fcvt_f16_to_f32(tmp3, tmp3, fpst, ahp); - neon_store_reg(a->vd, 2, tmp3); + write_neon_element32(tmp3, a->vd, 2, MO_32); + tcg_temp_free_i32(tmp3); tcg_gen_shri_i32(tmp2, tmp2, 16); gen_helper_vfp_fcvt_f16_to_f32(tmp2, tmp2, fpst, ahp); - neon_store_reg(a->vd, 3, tmp2); + write_neon_element32(tmp2, a->vd, 3, MO_32); + tcg_temp_free_i32(tmp2); tcg_temp_free_i32(ahp); tcg_temp_free_ptr(fpst); =20 @@ -3489,6 +3540,7 @@ DO_2M_CRYPTO(SHA256SU0, aa32_sha2, 2) =20 static bool do_2misc(DisasContext *s, arg_2misc *a, NeonGenOneOpFn *fn) { + TCGv_i32 tmp; int pass; =20 /* Handle a 2-reg-misc operation by iterating 32 bits at a time */ @@ -3514,11 +3566,13 @@ static bool do_2misc(DisasContext *s, arg_2misc *a,= NeonGenOneOpFn *fn) return true; } =20 + tmp =3D tcg_temp_new_i32(); for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { - TCGv_i32 tmp =3D neon_load_reg(a->vm, pass); + read_neon_element32(tmp, a->vm, pass, MO_32); fn(tmp, tmp); - neon_store_reg(a->vd, pass, tmp); + write_neon_element32(tmp, a->vd, pass, MO_32); } + tcg_temp_free_i32(tmp); =20 return true; } @@ -3871,25 +3925,29 @@ static bool trans_VTRN(DisasContext *s, arg_2misc *= a) return true; } =20 - if (a->size =3D=3D 2) { + tmp =3D tcg_temp_new_i32(); + tmp2 =3D tcg_temp_new_i32(); + if (a->size =3D=3D MO_32) { for (pass =3D 0; pass < (a->q ? 4 : 2); pass +=3D 2) { - tmp =3D neon_load_reg(a->vm, pass); - tmp2 =3D neon_load_reg(a->vd, pass + 1); - neon_store_reg(a->vm, pass, tmp2); - neon_store_reg(a->vd, pass + 1, tmp); + read_neon_element32(tmp, a->vm, pass, MO_32); + read_neon_element32(tmp2, a->vd, pass + 1, MO_32); + write_neon_element32(tmp2, a->vm, pass, MO_32); + write_neon_element32(tmp, a->vd, pass + 1, MO_32); } } else { for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { - tmp =3D neon_load_reg(a->vm, pass); - tmp2 =3D neon_load_reg(a->vd, pass); - if (a->size =3D=3D 0) { + read_neon_element32(tmp, a->vm, pass, MO_32); + read_neon_element32(tmp2, a->vd, pass, MO_32); + if (a->size =3D=3D MO_8) { gen_neon_trn_u8(tmp, tmp2); } else { gen_neon_trn_u16(tmp, tmp2); } - neon_store_reg(a->vm, pass, tmp2); - neon_store_reg(a->vd, pass, tmp); + write_neon_element32(tmp2, a->vm, pass, MO_32); + write_neon_element32(tmp, a->vd, pass, MO_32); } } + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(tmp2); return true; } --=20 2.20.1 From nobody Fri May 17 11:58:47 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uOowFsU/Wl7DM2DhiQSboTeZ8PmxUU3zA8lUWHXMoCA=; b=qtlOcKNHD51bFJMnKxmfmDOoVCuBP0Vx2FGUlByo2agEZlknsXubwiOFl10ZpzXjZ1 SRELv2cUPfIgsJSpfIABJiBgiPm8q7V4YvjxrniHlHxZwvrr0wQQE26DxpN8NyZdNeK3 zDgmHTrv1knShz1RIlaq2qOUGzy5HwubnstHrxuapvkh/1l91XoDQO0csJy/TS6kASU4 IacZcRS5kwI7CT+bBT42CLswwmadMXdnOrn1k6J7jtqp1p60dOA6CMVKP31zZOs6lN3A Gf2wh1DZC54tkwfKLUNhAOg2MLRZhmQMM5nWIexkgQhqzikpV0slfTapforLly5z9x73 sVlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uOowFsU/Wl7DM2DhiQSboTeZ8PmxUU3zA8lUWHXMoCA=; b=HntypfU5iONwfJboBtS+d3gW2ju0w8y3W8vT55OrvJpumuWBUN9qRx7GIMua/mKfyW a8LirE6n0PXcfE866yUTU9EPllI5u7OsAkhbbDiXZvwQGoheWJ7Qxir9wwvmXVYr3xed cm9tC+F1bDcaJ976yCGXfuWBf5ItSzLELNPc5jYDu9oNjMXvmSseqdFT0QhnGQDgMRm1 RHHRpsMR+RLcXI37ZzNNka96LJjtJi/jJykH47om5Ch5RrPeqG87p+HD3MagH9AE80Bl annuYB4r+bK2h92BLedDPVapR1fp4DafWjurEdi5JV7vF3Pb23v/JCT4ZD7CXQXtQc9Z wl/g== X-Gm-Message-State: AOAM531qHfMRrVe78Y/85Quw6uabj7kiifWyuD0EuF1s293Exl1KdCUD XS692G4f8Uydk67Otx18ol4TJ/BBYVmBoA== X-Google-Smtp-Source: ABdhPJzeoJZN6uwSNMyJJXhMomsfyeFGhLOlGHTVCxtz68EeLmiyxDqdVgX9rHU7DCBiY7BnysFVew== X-Received: by 2002:adf:eec7:: with SMTP id a7mr21407223wrp.294.1604337015858; Mon, 02 Nov 2020 09:10:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/26] target/arm: Expand read/write_neon_element32 to all MemOp Date: Mon, 2 Nov 2020 17:09:45 +0000 Message-Id: <20201102171005.30690-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We can then use this to improve VMOV (scalar to gp) and VMOV (gp to scalar) so that we simply perform the memory operation that we wanted, rather than inserting or extracting from a 32-bit quantity. These were the last uses of neon_load/store_reg, so remove them. Signed-off-by: Richard Henderson Message-id: 20201030022618.785675-7-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 50 +++++++++++++----------- target/arm/translate-vfp.c.inc | 71 +++++----------------------------- 2 files changed, 37 insertions(+), 84 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0ed9eab0b0d..55d5f4ed73b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1106,9 +1106,9 @@ static long neon_full_reg_offset(unsigned reg) * Return the offset of a 2**SIZE piece of a NEON register, at index ELE, * where 0 is the least significant end of the register. */ -static long neon_element_offset(int reg, int element, MemOp size) +static long neon_element_offset(int reg, int element, MemOp memop) { - int element_size =3D 1 << size; + int element_size =3D 1 << (memop & MO_SIZE); int ofs =3D element * element_size; #ifdef HOST_WORDS_BIGENDIAN /* @@ -1132,19 +1132,6 @@ static long vfp_reg_offset(bool dp, unsigned reg) } } =20 -static TCGv_i32 neon_load_reg(int reg, int pass) -{ - TCGv_i32 tmp =3D tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp, cpu_env, neon_element_offset(reg, pass, MO_32)); - return tmp; -} - -static void neon_store_reg(int reg, int pass, TCGv_i32 var) -{ - tcg_gen_st_i32(var, cpu_env, neon_element_offset(reg, pass, MO_32)); - tcg_temp_free_i32(var); -} - static inline void neon_load_reg64(TCGv_i64 var, int reg) { tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); @@ -1165,12 +1152,25 @@ static inline void neon_store_reg32(TCGv_i32 var, i= nt reg) tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); } =20 -static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp siz= e) +static void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp mem= op) { - long off =3D neon_element_offset(reg, ele, size); + long off =3D neon_element_offset(reg, ele, memop); =20 - switch (size) { - case MO_32: + switch (memop) { + case MO_SB: + tcg_gen_ld8s_i32(dest, cpu_env, off); + break; + case MO_UB: + tcg_gen_ld8u_i32(dest, cpu_env, off); + break; + case MO_SW: + tcg_gen_ld16s_i32(dest, cpu_env, off); + break; + case MO_UW: + tcg_gen_ld16u_i32(dest, cpu_env, off); + break; + case MO_UL: + case MO_SL: tcg_gen_ld_i32(dest, cpu_env, off); break; default: @@ -1178,11 +1178,17 @@ static void read_neon_element32(TCGv_i32 dest, int = reg, int ele, MemOp size) } } =20 -static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp siz= e) +static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp mem= op) { - long off =3D neon_element_offset(reg, ele, size); + long off =3D neon_element_offset(reg, ele, memop); =20 - switch (size) { + switch (memop) { + case MO_8: + tcg_gen_st8_i32(src, cpu_env, off); + break; + case MO_16: + tcg_gen_st16_i32(src, cpu_env, off); + break; case MO_32: tcg_gen_st_i32(src, cpu_env, off); break; diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 368bae0a73d..28f22f98729 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -511,11 +511,9 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV= _to_gp *a) { /* VMOV scalar to general purpose register */ TCGv_i32 tmp; - int pass; - uint32_t offset; =20 - /* SIZE =3D=3D 2 is a VFP instruction; otherwise NEON. */ - if (a->size =3D=3D 2 + /* SIZE =3D=3D MO_32 is a VFP instruction; otherwise NEON. */ + if (a->size =3D=3D MO_32 ? !dc_isar_feature(aa32_fpsp_v2, s) : !arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -526,44 +524,12 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMO= V_to_gp *a) return false; } =20 - offset =3D a->index << a->size; - pass =3D extract32(offset, 2, 1); - offset =3D extract32(offset, 0, 2) * 8; - if (!vfp_access_check(s)) { return true; } =20 - tmp =3D neon_load_reg(a->vn, pass); - switch (a->size) { - case 0: - if (offset) { - tcg_gen_shri_i32(tmp, tmp, offset); - } - if (a->u) { - gen_uxtb(tmp); - } else { - gen_sxtb(tmp); - } - break; - case 1: - if (a->u) { - if (offset) { - tcg_gen_shri_i32(tmp, tmp, 16); - } else { - gen_uxth(tmp); - } - } else { - if (offset) { - tcg_gen_sari_i32(tmp, tmp, 16); - } else { - gen_sxth(tmp); - } - } - break; - case 2: - break; - } + tmp =3D tcg_temp_new_i32(); + read_neon_element32(tmp, a->vn, a->index, a->size | (a->u ? 0 : MO_SIG= N)); store_reg(s, a->rt, tmp); =20 return true; @@ -572,12 +538,10 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMO= V_to_gp *a) static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) { /* VMOV general purpose register to scalar */ - TCGv_i32 tmp, tmp2; - int pass; - uint32_t offset; + TCGv_i32 tmp; =20 - /* SIZE =3D=3D 2 is a VFP instruction; otherwise NEON. */ - if (a->size =3D=3D 2 + /* SIZE =3D=3D MO_32 is a VFP instruction; otherwise NEON. */ + if (a->size =3D=3D MO_32 ? !dc_isar_feature(aa32_fpsp_v2, s) : !arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -588,30 +552,13 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_V= MOV_from_gp *a) return false; } =20 - offset =3D a->index << a->size; - pass =3D extract32(offset, 2, 1); - offset =3D extract32(offset, 0, 2) * 8; - if (!vfp_access_check(s)) { return true; } =20 tmp =3D load_reg(s, a->rt); - switch (a->size) { - case 0: - tmp2 =3D neon_load_reg(a->vn, pass); - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8); - tcg_temp_free_i32(tmp2); - break; - case 1: - tmp2 =3D neon_load_reg(a->vn, pass); - tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16); - tcg_temp_free_i32(tmp2); - break; - case 2: - break; - } - neon_store_reg(a->vn, pass, tmp); + write_neon_element32(tmp, a->vn, a->index, a->size); + tcg_temp_free_i32(tmp); =20 return true; } --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337253; cv=none; d=zohomail.com; s=zohoarc; b=GoWayH7EUfd/Cza4Wds93mzfXsQp6nH3IHHlzd5Fuuzse2fUWA4upiTolLuBQYOTgfL8czaTPWyyKcGSb/uwzrPTj/nD2c0Ch8KvdGSdOEiA2mf7n3KNU6273VoB46KM3jOzyL+eP+UbmoDNNmhetjlujQxUmBQxecauhOeNlUQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337253; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sWH77vnZKxmfMH0cyI9wVHiVNrPCEWcEw7jQppb988Q=; b=dAtLRCUD8TNI46y6sVDaJHsFLo5TB2H+hKaG0lEG89lemPAqkwZZoF/RR/dEM84M1ictr2y1hGyYY/VBtW8cUO6WgReDs+cBrG4Bd2zns5wPX2CI6xfUSUiuzKOJ/IupFg8KAhv8idi99x66YWhH4M+nllIRMoPhwz7g8VP6lc4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337253143578.3481010872805; Mon, 2 Nov 2020 09:14:13 -0800 (PST) Received: from localhost ([::1]:52812 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdPI-0005v0-CK for importer@patchew.org; Mon, 02 Nov 2020 12:14:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLa-0000im-7m for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:22 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:40646) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLX-0006R2-2G for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:21 -0500 Received: by mail-wr1-x42e.google.com with SMTP id 33so4706770wrl.7 for ; Mon, 02 Nov 2020 09:10:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sWH77vnZKxmfMH0cyI9wVHiVNrPCEWcEw7jQppb988Q=; b=zpAvAxBnnOjuKFf4/zkmxDjn5KzzC7I3m4K7inD+7XOnAoNzIa6emaB/0wSuYAhJXb AONogYB67nB9e+U60+1EJCCWncjp9emPb1uYuup4Q3rYlTTegwWpeu7GY8RPEskm33pr 2JIutQCjbRQgoDxCmUHheOcAALuRlNo16QPo2f3LhwwVN839tTXLbMty3Ux5WUDFLNVt OU/yo3os48YlS0jDigK+FmB1chWyrLI77pcCWlHIcFaBcllDolCwfW7YOlfDFFGHlyvy LdjRLl8YijEpBw0KsEScZRIPkSHLzSAW3gQWQ9TLfVni3x3jWJiL0J3ksxZHR0MAFEGV zQtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sWH77vnZKxmfMH0cyI9wVHiVNrPCEWcEw7jQppb988Q=; b=oFmKk3zBMy3h4A/HjsN5X53A3B34TTG7C5l/CEWawQZzqb7wVgE/d61q01Ht1ENhC8 OD84f36yZzEjnVSLqjKd7M8iZ1P0oXs0G0jAZ1bJEeTFupddf6kTa1e9sgublJN+MUty eFnJ0KCBWTjSOKgPAeTamkcDdjaZyYsLsCNyV0Q18Yi8InQu634qVoXlPXDQdrWoIvpr hyJlVNTwRC979rtLqfzz0Fv6hEutNrBnJ4DrRjI1WAPAV4fUivMC/VHhZjHWmX6b9Yyv zgXKWc2MPc+Fjbl+/wks0zp2WUmmY0feP4RiXNh5iz9fPZScYeBUBDMhcHFxohOdnDij Za6Q== X-Gm-Message-State: AOAM5315euVPmvywnWtYZnjV6OQITfTXMJQQjeA3wlLWwb9R0dCl+VIs IBhSOTvGPtJ4zxZv2m/WGwO36WK/PN+ZgA== X-Google-Smtp-Source: ABdhPJxRzTtd82i7I6tr1T6sYYQ/3yaIBRn032rYfnXpTCAL4hUNaWM0cQTrekldfWdvAs10FXCUdQ== X-Received: by 2002:adf:b30c:: with SMTP id j12mr21156279wrd.82.1604337017218; Mon, 02 Nov 2020 09:10:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/26] target/arm: Rename neon_load_reg32 to vfp_load_reg32 Date: Mon, 2 Nov 2020 17:09:46 +0000 Message-Id: <20201102171005.30690-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson The only uses of this function are for loading VFP single-precision values, and nothing to do with NEON. Signed-off-by: Richard Henderson Message-id: 20201030022618.785675-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 4 +- target/arm/translate-vfp.c.inc | 184 ++++++++++++++++----------------- 2 files changed, 94 insertions(+), 94 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 55d5f4ed73b..8491ab705b4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1142,12 +1142,12 @@ static inline void neon_store_reg64(TCGv_i64 var, i= nt reg) tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); } =20 -static inline void neon_load_reg32(TCGv_i32 var, int reg) +static inline void vfp_load_reg32(TCGv_i32 var, int reg) { tcg_gen_ld_i32(var, cpu_env, vfp_reg_offset(false, reg)); } =20 -static inline void neon_store_reg32(TCGv_i32 var, int reg) +static inline void vfp_store_reg32(TCGv_i32 var, int reg) { tcg_gen_st_i32(var, cpu_env, vfp_reg_offset(false, reg)); } diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 28f22f98729..d2a9b658bbd 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -283,8 +283,8 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) frn =3D tcg_temp_new_i32(); frm =3D tcg_temp_new_i32(); dest =3D tcg_temp_new_i32(); - neon_load_reg32(frn, rn); - neon_load_reg32(frm, rm); + vfp_load_reg32(frn, rn); + vfp_load_reg32(frm, rm); switch (a->cc) { case 0: /* eq: Z */ tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, @@ -315,7 +315,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) if (sz =3D=3D 1) { tcg_gen_andi_i32(dest, dest, 0xffff); } - neon_store_reg32(dest, rd); + vfp_store_reg32(dest, rd); tcg_temp_free_i32(frn); tcg_temp_free_i32(frm); tcg_temp_free_i32(dest); @@ -395,13 +395,13 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) TCGv_i32 tcg_res; tcg_op =3D tcg_temp_new_i32(); tcg_res =3D tcg_temp_new_i32(); - neon_load_reg32(tcg_op, rm); + vfp_load_reg32(tcg_op, rm); if (sz =3D=3D 1) { gen_helper_rinth(tcg_res, tcg_op, fpst); } else { gen_helper_rints(tcg_res, tcg_op, fpst); } - neon_store_reg32(tcg_res, rd); + vfp_store_reg32(tcg_res, rd); tcg_temp_free_i32(tcg_op); tcg_temp_free_i32(tcg_res); } @@ -470,7 +470,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) gen_helper_vfp_tould(tcg_res, tcg_double, tcg_shift, fpst); } tcg_gen_extrl_i64_i32(tcg_tmp, tcg_res); - neon_store_reg32(tcg_tmp, rd); + vfp_store_reg32(tcg_tmp, rd); tcg_temp_free_i32(tcg_tmp); tcg_temp_free_i64(tcg_res); tcg_temp_free_i64(tcg_double); @@ -478,7 +478,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) TCGv_i32 tcg_single, tcg_res; tcg_single =3D tcg_temp_new_i32(); tcg_res =3D tcg_temp_new_i32(); - neon_load_reg32(tcg_single, rm); + vfp_load_reg32(tcg_single, rm); if (sz =3D=3D 1) { if (is_signed) { gen_helper_vfp_toslh(tcg_res, tcg_single, tcg_shift, fpst); @@ -492,7 +492,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst); } } - neon_store_reg32(tcg_res, rd); + vfp_store_reg32(tcg_res, rd); tcg_temp_free_i32(tcg_res); tcg_temp_free_i32(tcg_single); } @@ -776,14 +776,14 @@ static bool trans_VMOV_half(DisasContext *s, arg_VMOV= _single *a) if (a->l) { /* VFP to general purpose register */ tmp =3D tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vn); + vfp_load_reg32(tmp, a->vn); tcg_gen_andi_i32(tmp, tmp, 0xffff); store_reg(s, a->rt, tmp); } else { /* general purpose register to VFP */ tmp =3D load_reg(s, a->rt); tcg_gen_andi_i32(tmp, tmp, 0xffff); - neon_store_reg32(tmp, a->vn); + vfp_store_reg32(tmp, a->vn); tcg_temp_free_i32(tmp); } =20 @@ -805,7 +805,7 @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV= _single *a) if (a->l) { /* VFP to general purpose register */ tmp =3D tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vn); + vfp_load_reg32(tmp, a->vn); if (a->rt =3D=3D 15) { /* Set the 4 flag bits in the CPSR. */ gen_set_nzcv(tmp); @@ -816,7 +816,7 @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV= _single *a) } else { /* general purpose register to VFP */ tmp =3D load_reg(s, a->rt); - neon_store_reg32(tmp, a->vn); + vfp_store_reg32(tmp, a->vn); tcg_temp_free_i32(tmp); } =20 @@ -842,18 +842,18 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMO= V_64_sp *a) if (a->op) { /* fpreg to gpreg */ tmp =3D tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm); + vfp_load_reg32(tmp, a->vm); store_reg(s, a->rt, tmp); tmp =3D tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm + 1); + vfp_load_reg32(tmp, a->vm + 1); store_reg(s, a->rt2, tmp); } else { /* gpreg to fpreg */ tmp =3D load_reg(s, a->rt); - neon_store_reg32(tmp, a->vm); + vfp_store_reg32(tmp, a->vm); tcg_temp_free_i32(tmp); tmp =3D load_reg(s, a->rt2); - neon_store_reg32(tmp, a->vm + 1); + vfp_store_reg32(tmp, a->vm + 1); tcg_temp_free_i32(tmp); } =20 @@ -885,18 +885,18 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMO= V_64_dp *a) if (a->op) { /* fpreg to gpreg */ tmp =3D tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm * 2); + vfp_load_reg32(tmp, a->vm * 2); store_reg(s, a->rt, tmp); tmp =3D tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm * 2 + 1); + vfp_load_reg32(tmp, a->vm * 2 + 1); store_reg(s, a->rt2, tmp); } else { /* gpreg to fpreg */ tmp =3D load_reg(s, a->rt); - neon_store_reg32(tmp, a->vm * 2); + vfp_store_reg32(tmp, a->vm * 2); tcg_temp_free_i32(tmp); tmp =3D load_reg(s, a->rt2); - neon_store_reg32(tmp, a->vm * 2 + 1); + vfp_store_reg32(tmp, a->vm * 2 + 1); tcg_temp_free_i32(tmp); } =20 @@ -927,9 +927,9 @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLD= R_VSTR_sp *a) tmp =3D tcg_temp_new_i32(); if (a->l) { gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); - neon_store_reg32(tmp, a->vd); + vfp_store_reg32(tmp, a->vd); } else { - neon_load_reg32(tmp, a->vd); + vfp_load_reg32(tmp, a->vd); gen_aa32_st16(s, tmp, addr, get_mem_index(s)); } tcg_temp_free_i32(tmp); @@ -961,9 +961,9 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLD= R_VSTR_sp *a) tmp =3D tcg_temp_new_i32(); if (a->l) { gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - neon_store_reg32(tmp, a->vd); + vfp_store_reg32(tmp, a->vd); } else { - neon_load_reg32(tmp, a->vd); + vfp_load_reg32(tmp, a->vd); gen_aa32_st32(s, tmp, addr, get_mem_index(s)); } tcg_temp_free_i32(tmp); @@ -1066,10 +1066,10 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg= _VLDM_VSTM_sp *a) if (a->l) { /* load */ gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - neon_store_reg32(tmp, a->vd + i); + vfp_store_reg32(tmp, a->vd + i); } else { /* store */ - neon_load_reg32(tmp, a->vd + i); + vfp_load_reg32(tmp, a->vd + i); gen_aa32_st32(s, tmp, addr, get_mem_index(s)); } tcg_gen_addi_i32(addr, addr, offset); @@ -1285,15 +1285,15 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3O= pSPFn *fn, fd =3D tcg_temp_new_i32(); fpst =3D fpstatus_ptr(FPST_FPCR); =20 - neon_load_reg32(f0, vn); - neon_load_reg32(f1, vm); + vfp_load_reg32(f0, vn); + vfp_load_reg32(f1, vm); =20 for (;;) { if (reads_vd) { - neon_load_reg32(fd, vd); + vfp_load_reg32(fd, vd); } fn(fd, f0, f1, fpst); - neon_store_reg32(fd, vd); + vfp_store_reg32(fd, vd); =20 if (veclen =3D=3D 0) { break; @@ -1303,10 +1303,10 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3O= pSPFn *fn, veclen--; vd =3D vfp_advance_sreg(vd, delta_d); vn =3D vfp_advance_sreg(vn, delta_d); - neon_load_reg32(f0, vn); + vfp_load_reg32(f0, vn); if (delta_m) { vm =3D vfp_advance_sreg(vm, delta_m); - neon_load_reg32(f1, vm); + vfp_load_reg32(f1, vm); } } =20 @@ -1349,14 +1349,14 @@ static bool do_vfp_3op_hp(DisasContext *s, VFPGen3O= pSPFn *fn, fd =3D tcg_temp_new_i32(); fpst =3D fpstatus_ptr(FPST_FPCR_F16); =20 - neon_load_reg32(f0, vn); - neon_load_reg32(f1, vm); + vfp_load_reg32(f0, vn); + vfp_load_reg32(f1, vm); =20 if (reads_vd) { - neon_load_reg32(fd, vd); + vfp_load_reg32(fd, vd); } fn(fd, f0, f1, fpst); - neon_store_reg32(fd, vd); + vfp_store_reg32(fd, vd); =20 tcg_temp_free_i32(f0); tcg_temp_free_i32(f1); @@ -1489,11 +1489,11 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2O= pSPFn *fn, int vd, int vm) f0 =3D tcg_temp_new_i32(); fd =3D tcg_temp_new_i32(); =20 - neon_load_reg32(f0, vm); + vfp_load_reg32(f0, vm); =20 for (;;) { fn(fd, f0); - neon_store_reg32(fd, vd); + vfp_store_reg32(fd, vd); =20 if (veclen =3D=3D 0) { break; @@ -1503,7 +1503,7 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) /* single source one-many */ while (veclen--) { vd =3D vfp_advance_sreg(vd, delta_d); - neon_store_reg32(fd, vd); + vfp_store_reg32(fd, vd); } break; } @@ -1512,7 +1512,7 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) veclen--; vd =3D vfp_advance_sreg(vd, delta_d); vm =3D vfp_advance_sreg(vm, delta_m); - neon_load_reg32(f0, vm); + vfp_load_reg32(f0, vm); } =20 tcg_temp_free_i32(f0); @@ -1545,9 +1545,9 @@ static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpS= PFn *fn, int vd, int vm) } =20 f0 =3D tcg_temp_new_i32(); - neon_load_reg32(f0, vm); + vfp_load_reg32(f0, vm); fn(f0, f0); - neon_store_reg32(f0, vd); + vfp_store_reg32(f0, vd); tcg_temp_free_i32(f0); =20 return true; @@ -2037,20 +2037,20 @@ static bool do_vfm_hp(DisasContext *s, arg_VFMA_sp = *a, bool neg_n, bool neg_d) vm =3D tcg_temp_new_i32(); vd =3D tcg_temp_new_i32(); =20 - neon_load_reg32(vn, a->vn); - neon_load_reg32(vm, a->vm); + vfp_load_reg32(vn, a->vn); + vfp_load_reg32(vm, a->vm); if (neg_n) { /* VFNMS, VFMS */ gen_helper_vfp_negh(vn, vn); } - neon_load_reg32(vd, a->vd); + vfp_load_reg32(vd, a->vd); if (neg_d) { /* VFNMA, VFNMS */ gen_helper_vfp_negh(vd, vd); } fpst =3D fpstatus_ptr(FPST_FPCR_F16); gen_helper_vfp_muladdh(vd, vn, vm, vd, fpst); - neon_store_reg32(vd, a->vd); + vfp_store_reg32(vd, a->vd); =20 tcg_temp_free_ptr(fpst); tcg_temp_free_i32(vn); @@ -2102,20 +2102,20 @@ static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp = *a, bool neg_n, bool neg_d) vm =3D tcg_temp_new_i32(); vd =3D tcg_temp_new_i32(); =20 - neon_load_reg32(vn, a->vn); - neon_load_reg32(vm, a->vm); + vfp_load_reg32(vn, a->vn); + vfp_load_reg32(vm, a->vm); if (neg_n) { /* VFNMS, VFMS */ gen_helper_vfp_negs(vn, vn); } - neon_load_reg32(vd, a->vd); + vfp_load_reg32(vd, a->vd); if (neg_d) { /* VFNMA, VFNMS */ gen_helper_vfp_negs(vd, vd); } fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_vfp_muladds(vd, vn, vm, vd, fpst); - neon_store_reg32(vd, a->vd); + vfp_store_reg32(vd, a->vd); =20 tcg_temp_free_ptr(fpst); tcg_temp_free_i32(vn); @@ -2230,7 +2230,7 @@ static bool trans_VMOV_imm_hp(DisasContext *s, arg_VM= OV_imm_sp *a) } =20 fd =3D tcg_const_i32(vfp_expand_imm(MO_16, a->imm)); - neon_store_reg32(fd, a->vd); + vfp_store_reg32(fd, a->vd); tcg_temp_free_i32(fd); return true; } @@ -2270,7 +2270,7 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VM= OV_imm_sp *a) fd =3D tcg_const_i32(vfp_expand_imm(MO_32, a->imm)); =20 for (;;) { - neon_store_reg32(fd, vd); + vfp_store_reg32(fd, vd); =20 if (veclen =3D=3D 0) { break; @@ -2397,11 +2397,11 @@ static bool trans_VCMP_hp(DisasContext *s, arg_VCMP= _sp *a) vd =3D tcg_temp_new_i32(); vm =3D tcg_temp_new_i32(); =20 - neon_load_reg32(vd, a->vd); + vfp_load_reg32(vd, a->vd); if (a->z) { tcg_gen_movi_i32(vm, 0); } else { - neon_load_reg32(vm, a->vm); + vfp_load_reg32(vm, a->vm); } =20 if (a->e) { @@ -2436,11 +2436,11 @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP= _sp *a) vd =3D tcg_temp_new_i32(); vm =3D tcg_temp_new_i32(); =20 - neon_load_reg32(vd, a->vd); + vfp_load_reg32(vd, a->vd); if (a->z) { tcg_gen_movi_i32(vm, 0); } else { - neon_load_reg32(vm, a->vm); + vfp_load_reg32(vm, a->vm); } =20 if (a->e) { @@ -2519,7 +2519,7 @@ static bool trans_VCVT_f32_f16(DisasContext *s, arg_V= CVT_f32_f16 *a) /* The T bit tells us if we want the low or high 16 bits of Vm */ tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); gen_helper_vfp_fcvt_f16_to_f32(tmp, tmp, fpst, ahp_mode); - neon_store_reg32(tmp, a->vd); + vfp_store_reg32(tmp, a->vd); tcg_temp_free_i32(ahp_mode); tcg_temp_free_ptr(fpst); tcg_temp_free_i32(tmp); @@ -2583,7 +2583,7 @@ static bool trans_VCVT_f16_f32(DisasContext *s, arg_V= CVT_f16_f32 *a) ahp_mode =3D get_ahp_flag(); tmp =3D tcg_temp_new_i32(); =20 - neon_load_reg32(tmp, a->vm); + vfp_load_reg32(tmp, a->vm); gen_helper_vfp_fcvt_f32_to_f16(tmp, tmp, fpst, ahp_mode); tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); tcg_temp_free_i32(ahp_mode); @@ -2645,10 +2645,10 @@ static bool trans_VRINTR_hp(DisasContext *s, arg_VR= INTR_sp *a) } =20 tmp =3D tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm); + vfp_load_reg32(tmp, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR_F16); gen_helper_rinth(tmp, tmp, fpst); - neon_store_reg32(tmp, a->vd); + vfp_store_reg32(tmp, a->vd); tcg_temp_free_ptr(fpst); tcg_temp_free_i32(tmp); return true; @@ -2668,10 +2668,10 @@ static bool trans_VRINTR_sp(DisasContext *s, arg_VR= INTR_sp *a) } =20 tmp =3D tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm); + vfp_load_reg32(tmp, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rints(tmp, tmp, fpst); - neon_store_reg32(tmp, a->vd); + vfp_store_reg32(tmp, a->vd); tcg_temp_free_ptr(fpst); tcg_temp_free_i32(tmp); return true; @@ -2724,13 +2724,13 @@ static bool trans_VRINTZ_hp(DisasContext *s, arg_VR= INTZ_sp *a) } =20 tmp =3D tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm); + vfp_load_reg32(tmp, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR_F16); tcg_rmode =3D tcg_const_i32(float_round_to_zero); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rinth(tmp, tmp, fpst); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - neon_store_reg32(tmp, a->vd); + vfp_store_reg32(tmp, a->vd); tcg_temp_free_ptr(fpst); tcg_temp_free_i32(tcg_rmode); tcg_temp_free_i32(tmp); @@ -2752,13 +2752,13 @@ static bool trans_VRINTZ_sp(DisasContext *s, arg_VR= INTZ_sp *a) } =20 tmp =3D tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm); + vfp_load_reg32(tmp, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR); tcg_rmode =3D tcg_const_i32(float_round_to_zero); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rints(tmp, tmp, fpst); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - neon_store_reg32(tmp, a->vd); + vfp_store_reg32(tmp, a->vd); tcg_temp_free_ptr(fpst); tcg_temp_free_i32(tcg_rmode); tcg_temp_free_i32(tmp); @@ -2816,10 +2816,10 @@ static bool trans_VRINTX_hp(DisasContext *s, arg_VR= INTX_sp *a) } =20 tmp =3D tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm); + vfp_load_reg32(tmp, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR_F16); gen_helper_rinth_exact(tmp, tmp, fpst); - neon_store_reg32(tmp, a->vd); + vfp_store_reg32(tmp, a->vd); tcg_temp_free_ptr(fpst); tcg_temp_free_i32(tmp); return true; @@ -2839,10 +2839,10 @@ static bool trans_VRINTX_sp(DisasContext *s, arg_VR= INTX_sp *a) } =20 tmp =3D tcg_temp_new_i32(); - neon_load_reg32(tmp, a->vm); + vfp_load_reg32(tmp, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rints_exact(tmp, tmp, fpst); - neon_store_reg32(tmp, a->vd); + vfp_store_reg32(tmp, a->vd); tcg_temp_free_ptr(fpst); tcg_temp_free_i32(tmp); return true; @@ -2900,7 +2900,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s= p *a) =20 vm =3D tcg_temp_new_i32(); vd =3D tcg_temp_new_i64(); - neon_load_reg32(vm, a->vm); + vfp_load_reg32(vm, a->vm); gen_helper_vfp_fcvtds(vd, vm, cpu_env); neon_store_reg64(vd, a->vd); tcg_temp_free_i32(vm); @@ -2930,7 +2930,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d= p *a) vm =3D tcg_temp_new_i64(); neon_load_reg64(vm, a->vm); gen_helper_vfp_fcvtsd(vd, vm, cpu_env); - neon_store_reg32(vd, a->vd); + vfp_store_reg32(vd, a->vd); tcg_temp_free_i32(vd); tcg_temp_free_i64(vm); return true; @@ -2950,7 +2950,7 @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VC= VT_int_sp *a) } =20 vm =3D tcg_temp_new_i32(); - neon_load_reg32(vm, a->vm); + vfp_load_reg32(vm, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR_F16); if (a->s) { /* i32 -> f16 */ @@ -2959,7 +2959,7 @@ static bool trans_VCVT_int_hp(DisasContext *s, arg_VC= VT_int_sp *a) /* u32 -> f16 */ gen_helper_vfp_uitoh(vm, vm, fpst); } - neon_store_reg32(vm, a->vd); + vfp_store_reg32(vm, a->vd); tcg_temp_free_i32(vm); tcg_temp_free_ptr(fpst); return true; @@ -2979,7 +2979,7 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VC= VT_int_sp *a) } =20 vm =3D tcg_temp_new_i32(); - neon_load_reg32(vm, a->vm); + vfp_load_reg32(vm, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR); if (a->s) { /* i32 -> f32 */ @@ -2988,7 +2988,7 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VC= VT_int_sp *a) /* u32 -> f32 */ gen_helper_vfp_uitos(vm, vm, fpst); } - neon_store_reg32(vm, a->vd); + vfp_store_reg32(vm, a->vd); tcg_temp_free_i32(vm); tcg_temp_free_ptr(fpst); return true; @@ -3015,7 +3015,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) =20 vm =3D tcg_temp_new_i32(); vd =3D tcg_temp_new_i64(); - neon_load_reg32(vm, a->vm); + vfp_load_reg32(vm, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR); if (a->s) { /* i32 -> f64 */ @@ -3057,7 +3057,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) vd =3D tcg_temp_new_i32(); neon_load_reg64(vm, a->vm); gen_helper_vjcvt(vd, vm, cpu_env); - neon_store_reg32(vd, a->vd); + vfp_store_reg32(vd, a->vd); tcg_temp_free_i64(vm); tcg_temp_free_i32(vd); return true; @@ -3080,7 +3080,7 @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VC= VT_fix_sp *a) frac_bits =3D (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); =20 vd =3D tcg_temp_new_i32(); - neon_load_reg32(vd, a->vd); + vfp_load_reg32(vd, a->vd); =20 fpst =3D fpstatus_ptr(FPST_FPCR_F16); shift =3D tcg_const_i32(frac_bits); @@ -3115,7 +3115,7 @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VC= VT_fix_sp *a) g_assert_not_reached(); } =20 - neon_store_reg32(vd, a->vd); + vfp_store_reg32(vd, a->vd); tcg_temp_free_i32(vd); tcg_temp_free_i32(shift); tcg_temp_free_ptr(fpst); @@ -3139,7 +3139,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VC= VT_fix_sp *a) frac_bits =3D (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); =20 vd =3D tcg_temp_new_i32(); - neon_load_reg32(vd, a->vd); + vfp_load_reg32(vd, a->vd); =20 fpst =3D fpstatus_ptr(FPST_FPCR); shift =3D tcg_const_i32(frac_bits); @@ -3174,7 +3174,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VC= VT_fix_sp *a) g_assert_not_reached(); } =20 - neon_store_reg32(vd, a->vd); + vfp_store_reg32(vd, a->vd); tcg_temp_free_i32(vd); tcg_temp_free_i32(shift); tcg_temp_free_ptr(fpst); @@ -3261,7 +3261,7 @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VC= VT_sp_int *a) =20 fpst =3D fpstatus_ptr(FPST_FPCR_F16); vm =3D tcg_temp_new_i32(); - neon_load_reg32(vm, a->vm); + vfp_load_reg32(vm, a->vm); =20 if (a->s) { if (a->rz) { @@ -3276,7 +3276,7 @@ static bool trans_VCVT_hp_int(DisasContext *s, arg_VC= VT_sp_int *a) gen_helper_vfp_touih(vm, vm, fpst); } } - neon_store_reg32(vm, a->vd); + vfp_store_reg32(vm, a->vd); tcg_temp_free_i32(vm); tcg_temp_free_ptr(fpst); return true; @@ -3297,7 +3297,7 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VC= VT_sp_int *a) =20 fpst =3D fpstatus_ptr(FPST_FPCR); vm =3D tcg_temp_new_i32(); - neon_load_reg32(vm, a->vm); + vfp_load_reg32(vm, a->vm); =20 if (a->s) { if (a->rz) { @@ -3312,7 +3312,7 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VC= VT_sp_int *a) gen_helper_vfp_touis(vm, vm, fpst); } } - neon_store_reg32(vm, a->vd); + vfp_store_reg32(vm, a->vd); tcg_temp_free_i32(vm); tcg_temp_free_ptr(fpst); return true; @@ -3355,7 +3355,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) gen_helper_vfp_touid(vd, vm, fpst); } } - neon_store_reg32(vd, a->vd); + vfp_store_reg32(vd, a->vd); tcg_temp_free_i32(vd); tcg_temp_free_i64(vm); tcg_temp_free_ptr(fpst); @@ -3468,10 +3468,10 @@ static bool trans_VINS(DisasContext *s, arg_VINS *a) /* Insert low half of Vm into high half of Vd */ rm =3D tcg_temp_new_i32(); rd =3D tcg_temp_new_i32(); - neon_load_reg32(rm, a->vm); - neon_load_reg32(rd, a->vd); + vfp_load_reg32(rm, a->vm); + vfp_load_reg32(rd, a->vd); tcg_gen_deposit_i32(rd, rd, rm, 16, 16); - neon_store_reg32(rd, a->vd); + vfp_store_reg32(rd, a->vd); tcg_temp_free_i32(rm); tcg_temp_free_i32(rd); return true; @@ -3495,9 +3495,9 @@ static bool trans_VMOVX(DisasContext *s, arg_VINS *a) =20 /* Set Vd to high half of Vm */ rm =3D tcg_temp_new_i32(); - neon_load_reg32(rm, a->vm); + vfp_load_reg32(rm, a->vm); tcg_gen_shri_i32(rm, rm, 16); - neon_store_reg32(rm, a->vd); + vfp_store_reg32(rm, a->vd); tcg_temp_free_i32(rm); return true; } --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337556; cv=none; d=zohomail.com; s=zohoarc; b=DlRx/BlZRjqYixebIrATmiO2B/rQFtfrt1mfIFi5Tug+C71zOZYAJM73vI+O0floGnVvdI3SlFLONgYMopwF8EP6GjzN8KM/+P/CZMcv8CD2Umihx0LEnESkxNAHL7aorwCKYdb0Sbc4jreexsyMWqh6O7KQCdETYa9EYX18RuE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337556; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LMG2S8LqH/n4F3uuVEqblkPOM6DnMxO6M2jtzxBxXgI=; b=dnJ40l8LwmUHFF82e936544ywllWx/OBAACUKhM0IOnv25mOygFK2uG87TopVb6V79JtowH4u5kcsq8H9xgJjXxzC5OHsh++ecNuz6P+ivx0QtS0jr5vcYjz7ET/oOhGgHD58Eyl48mDRnH5u0zcQnX0rJgWRY+32anI+IAcviY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337556409886.8294732295298; Mon, 2 Nov 2020 09:19:16 -0800 (PST) Received: from localhost ([::1]:41378 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdUB-0004dz-4a for importer@patchew.org; Mon, 02 Nov 2020 12:19:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLk-0000qe-6c for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:32 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:39006) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLh-0006Y4-4F for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:31 -0500 Received: by mail-wr1-x42e.google.com with SMTP id y12so15492625wrp.6 for ; Mon, 02 Nov 2020 09:10:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LMG2S8LqH/n4F3uuVEqblkPOM6DnMxO6M2jtzxBxXgI=; b=N5qqoAprFC/a1VNvUfyGCrREqdxgd7y9wB7wOx7aXGMRO63+zS+nF2eBKZuMJaM4Ig 3TG3VAP3gDeU1n0u529d18RZ303lM6wk7bwhglFQqK7exMREYc2iQPC0XlUmcRXaj/yE f8DfquWVlTbil5Hlhc6bUdCJkoGRKyQQnnnaMLCUH+e9BFKDz8Md9v1G8oM8yxCoav7l LPfpKp3enBxEAUAGWrqTHBK0U/YSQALBvdpxOA7AydjtiW8puahzhfJc32GA/wnM/+mK b5tssRgqz2sAM4JlwoNekmii6HF60OTu6/9KfBObtz/mpoRkwFDEgdvcPCmWOPX8LYNw HBWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LMG2S8LqH/n4F3uuVEqblkPOM6DnMxO6M2jtzxBxXgI=; b=uAMP6LY8WYynz34LVdWA4znkOuYCFnt4BZ0LH3yyvp5WC0aC6yFNLpBGNIOQGvy5Mc Hgb2lPcyVet9erFfhMUkdQxTyNmK7aZW8vE/GrGVImLkZ6UA7mBCXf8hv3WyfZ5jaS0G lBkbJdPPjqmj6crM4Tey/sffTKcR/DgKiIk957jDdkOBQ+APOScm8mafisKJP4VJ2UeA pMgW0Oxr4cOQ/9mZivEBoK46rP/VPQK3Z+S6VFehdgFR8sHkY+Tz0RxlzxS293lnPGCg JxktF5UTZuqxT9bqpUQMjyGw1M9FSAitB+XPPRNQO3l6hyk71x7pfdRQbeOvaTD7Nutg u70A== X-Gm-Message-State: AOAM533Ofc0GZJtHnaO84rNMX9DxuDYplRZw8B2Emfg9ljn28KEWcobj i2Hu6jjBhxmiq3VuMbgxJQnqlvbs1Yn1YQ== X-Google-Smtp-Source: ABdhPJxGMM2626CThcGrtmMQ1z5ifu+/g0XlLI0ku19brVltxEqfwCiKGkXXs6fQ2YnwF/3wagw/YQ== X-Received: by 2002:adf:cd87:: with SMTP id q7mr21344432wrj.169.1604337026803; Mon, 02 Nov 2020 09:10:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/26] target/arm: Add read/write_neon_element64 Date: Mon, 2 Nov 2020 17:09:47 +0000 Message-Id: <20201102171005.30690-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Replace all uses of neon_load/store_reg64 within translate-neon.c.inc. Signed-off-by: Richard Henderson Message-id: 20201030022618.785675-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 26 +++++++++ target/arm/translate-neon.c.inc | 94 ++++++++++++++++----------------- 2 files changed, 73 insertions(+), 47 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 8491ab705b4..4fb0a62200f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1178,6 +1178,19 @@ static void read_neon_element32(TCGv_i32 dest, int r= eg, int ele, MemOp memop) } } =20 +static void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp mem= op) +{ + long off =3D neon_element_offset(reg, ele, memop); + + switch (memop) { + case MO_Q: + tcg_gen_ld_i64(dest, cpu_env, off); + break; + default: + g_assert_not_reached(); + } +} + static void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp mem= op) { long off =3D neon_element_offset(reg, ele, memop); @@ -1197,6 +1210,19 @@ static void write_neon_element32(TCGv_i32 src, int r= eg, int ele, MemOp memop) } } =20 +static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp mem= op) +{ + long off =3D neon_element_offset(reg, ele, memop); + + switch (memop) { + case MO_64: + tcg_gen_st_i64(src, cpu_env, off); + break; + default: + g_assert_not_reached(); + } +} + static TCGv_ptr vfp_reg_ptr(bool dp, int reg) { TCGv_ptr ret =3D tcg_temp_new_ptr(); diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index 549381703ea..c2d67160f9e 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -1265,9 +1265,9 @@ static bool do_2shift_env_64(DisasContext *s, arg_2re= g_shift *a, for (pass =3D 0; pass < a->q + 1; pass++) { TCGv_i64 tmp =3D tcg_temp_new_i64(); =20 - neon_load_reg64(tmp, a->vm + pass); + read_neon_element64(tmp, a->vm, pass, MO_64); fn(tmp, cpu_env, tmp, constimm); - neon_store_reg64(tmp, a->vd + pass); + write_neon_element64(tmp, a->vd, pass, MO_64); tcg_temp_free_i64(tmp); } tcg_temp_free_i64(constimm); @@ -1375,8 +1375,8 @@ static bool do_2shift_narrow_64(DisasContext *s, arg_= 2reg_shift *a, rd =3D tcg_temp_new_i32(); =20 /* Load both inputs first to avoid potential overwrite if rm =3D=3D rd= */ - neon_load_reg64(rm1, a->vm); - neon_load_reg64(rm2, a->vm + 1); + read_neon_element64(rm1, a->vm, 0, MO_64); + read_neon_element64(rm2, a->vm, 1, MO_64); =20 shiftfn(rm1, rm1, constimm); narrowfn(rd, cpu_env, rm1); @@ -1579,7 +1579,7 @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_sh= ift *a, tcg_gen_shli_i64(tmp, tmp, a->shift); tcg_gen_andi_i64(tmp, tmp, ~widen_mask); } - neon_store_reg64(tmp, a->vd); + write_neon_element64(tmp, a->vd, 0, MO_64); =20 widenfn(tmp, rm1); tcg_temp_free_i32(rm1); @@ -1587,7 +1587,7 @@ static bool do_vshll_2sh(DisasContext *s, arg_2reg_sh= ift *a, tcg_gen_shli_i64(tmp, tmp, a->shift); tcg_gen_andi_i64(tmp, tmp, ~widen_mask); } - neon_store_reg64(tmp, a->vd + 1); + write_neon_element64(tmp, a->vd, 1, MO_64); tcg_temp_free_i64(tmp); return true; } @@ -1822,7 +1822,7 @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff= *a, rm_64 =3D tcg_temp_new_i64(); =20 if (src1_wide) { - neon_load_reg64(rn0_64, a->vn); + read_neon_element64(rn0_64, a->vn, 0, MO_64); } else { TCGv_i32 tmp =3D tcg_temp_new_i32(); read_neon_element32(tmp, a->vn, 0, MO_32); @@ -1841,7 +1841,7 @@ static bool do_prewiden_3d(DisasContext *s, arg_3diff= *a, * avoid incorrect results if a narrow input overlaps with the result. */ if (src1_wide) { - neon_load_reg64(rn1_64, a->vn + 1); + read_neon_element64(rn1_64, a->vn, 1, MO_64); } else { TCGv_i32 tmp =3D tcg_temp_new_i32(); read_neon_element32(tmp, a->vn, 1, MO_32); @@ -1851,12 +1851,12 @@ static bool do_prewiden_3d(DisasContext *s, arg_3di= ff *a, rm =3D tcg_temp_new_i32(); read_neon_element32(rm, a->vm, 1, MO_32); =20 - neon_store_reg64(rn0_64, a->vd); + write_neon_element64(rn0_64, a->vd, 0, MO_64); =20 widenfn(rm_64, rm); tcg_temp_free_i32(rm); opfn(rn1_64, rn1_64, rm_64); - neon_store_reg64(rn1_64, a->vd + 1); + write_neon_element64(rn1_64, a->vd, 1, MO_64); =20 tcg_temp_free_i64(rn0_64); tcg_temp_free_i64(rn1_64); @@ -1928,15 +1928,15 @@ static bool do_narrow_3d(DisasContext *s, arg_3diff= *a, rd0 =3D tcg_temp_new_i32(); rd1 =3D tcg_temp_new_i32(); =20 - neon_load_reg64(rn_64, a->vn); - neon_load_reg64(rm_64, a->vm); + read_neon_element64(rn_64, a->vn, 0, MO_64); + read_neon_element64(rm_64, a->vm, 0, MO_64); =20 opfn(rn_64, rn_64, rm_64); =20 narrowfn(rd0, rn_64); =20 - neon_load_reg64(rn_64, a->vn + 1); - neon_load_reg64(rm_64, a->vm + 1); + read_neon_element64(rn_64, a->vn, 1, MO_64); + read_neon_element64(rm_64, a->vm, 1, MO_64); =20 opfn(rn_64, rn_64, rm_64); =20 @@ -2036,16 +2036,16 @@ static bool do_long_3d(DisasContext *s, arg_3diff *= a, /* Don't store results until after all loads: they might overlap */ if (accfn) { tmp =3D tcg_temp_new_i64(); - neon_load_reg64(tmp, a->vd); + read_neon_element64(tmp, a->vd, 0, MO_64); accfn(tmp, tmp, rd0); - neon_store_reg64(tmp, a->vd); - neon_load_reg64(tmp, a->vd + 1); + write_neon_element64(tmp, a->vd, 0, MO_64); + read_neon_element64(tmp, a->vd, 1, MO_64); accfn(tmp, tmp, rd1); - neon_store_reg64(tmp, a->vd + 1); + write_neon_element64(tmp, a->vd, 1, MO_64); tcg_temp_free_i64(tmp); } else { - neon_store_reg64(rd0, a->vd); - neon_store_reg64(rd1, a->vd + 1); + write_neon_element64(rd0, a->vd, 0, MO_64); + write_neon_element64(rd1, a->vd, 1, MO_64); } =20 tcg_temp_free_i64(rd0); @@ -2669,16 +2669,16 @@ static bool do_2scalar_long(DisasContext *s, arg_2s= calar *a, =20 if (accfn) { TCGv_i64 t64 =3D tcg_temp_new_i64(); - neon_load_reg64(t64, a->vd); + read_neon_element64(t64, a->vd, 0, MO_64); accfn(t64, t64, rn0_64); - neon_store_reg64(t64, a->vd); - neon_load_reg64(t64, a->vd + 1); + write_neon_element64(t64, a->vd, 0, MO_64); + read_neon_element64(t64, a->vd, 1, MO_64); accfn(t64, t64, rn1_64); - neon_store_reg64(t64, a->vd + 1); + write_neon_element64(t64, a->vd, 1, MO_64); tcg_temp_free_i64(t64); } else { - neon_store_reg64(rn0_64, a->vd); - neon_store_reg64(rn1_64, a->vd + 1); + write_neon_element64(rn0_64, a->vd, 0, MO_64); + write_neon_element64(rn1_64, a->vd, 1, MO_64); } tcg_temp_free_i64(rn0_64); tcg_temp_free_i64(rn1_64); @@ -2812,10 +2812,10 @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) right =3D tcg_temp_new_i64(); dest =3D tcg_temp_new_i64(); =20 - neon_load_reg64(right, a->vn); - neon_load_reg64(left, a->vm); + read_neon_element64(right, a->vn, 0, MO_64); + read_neon_element64(left, a->vm, 0, MO_64); tcg_gen_extract2_i64(dest, right, left, a->imm * 8); - neon_store_reg64(dest, a->vd); + write_neon_element64(dest, a->vd, 0, MO_64); =20 tcg_temp_free_i64(left); tcg_temp_free_i64(right); @@ -2831,21 +2831,21 @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a) destright =3D tcg_temp_new_i64(); =20 if (a->imm < 8) { - neon_load_reg64(right, a->vn); - neon_load_reg64(middle, a->vn + 1); + read_neon_element64(right, a->vn, 0, MO_64); + read_neon_element64(middle, a->vn, 1, MO_64); tcg_gen_extract2_i64(destright, right, middle, a->imm * 8); - neon_load_reg64(left, a->vm); + read_neon_element64(left, a->vm, 0, MO_64); tcg_gen_extract2_i64(destleft, middle, left, a->imm * 8); } else { - neon_load_reg64(right, a->vn + 1); - neon_load_reg64(middle, a->vm); + read_neon_element64(right, a->vn, 1, MO_64); + read_neon_element64(middle, a->vm, 0, MO_64); tcg_gen_extract2_i64(destright, right, middle, (a->imm - 8) * = 8); - neon_load_reg64(left, a->vm + 1); + read_neon_element64(left, a->vm, 1, MO_64); tcg_gen_extract2_i64(destleft, middle, left, (a->imm - 8) * 8); } =20 - neon_store_reg64(destright, a->vd); - neon_store_reg64(destleft, a->vd + 1); + write_neon_element64(destright, a->vd, 0, MO_64); + write_neon_element64(destleft, a->vd, 1, MO_64); =20 tcg_temp_free_i64(destright); tcg_temp_free_i64(destleft); @@ -3052,11 +3052,11 @@ static bool do_2misc_pairwise(DisasContext *s, arg_= 2misc *a, =20 if (accfn) { TCGv_i64 tmp64 =3D tcg_temp_new_i64(); - neon_load_reg64(tmp64, a->vd + pass); + read_neon_element64(tmp64, a->vd, pass, MO_64); accfn(rd_64, tmp64, rd_64); tcg_temp_free_i64(tmp64); } - neon_store_reg64(rd_64, a->vd + pass); + write_neon_element64(rd_64, a->vd, pass, MO_64); tcg_temp_free_i64(rd_64); } return true; @@ -3254,9 +3254,9 @@ static bool do_vmovn(DisasContext *s, arg_2misc *a, rd0 =3D tcg_temp_new_i32(); rd1 =3D tcg_temp_new_i32(); =20 - neon_load_reg64(rm, a->vm); + read_neon_element64(rm, a->vm, 0, MO_64); narrowfn(rd0, cpu_env, rm); - neon_load_reg64(rm, a->vm + 1); + read_neon_element64(rm, a->vm, 1, MO_64); narrowfn(rd1, cpu_env, rm); write_neon_element32(rd0, a->vd, 0, MO_32); write_neon_element32(rd1, a->vd, 1, MO_32); @@ -3326,10 +3326,10 @@ static bool trans_VSHLL(DisasContext *s, arg_2misc = *a) =20 widenfn(rd, rm0); tcg_gen_shli_i64(rd, rd, 8 << a->size); - neon_store_reg64(rd, a->vd); + write_neon_element64(rd, a->vd, 0, MO_64); widenfn(rd, rm1); tcg_gen_shli_i64(rd, rd, 8 << a->size); - neon_store_reg64(rd, a->vd + 1); + write_neon_element64(rd, a->vd, 1, MO_64); =20 tcg_temp_free_i64(rd); tcg_temp_free_i32(rm0); @@ -3847,10 +3847,10 @@ static bool trans_VSWP(DisasContext *s, arg_2misc *= a) rm =3D tcg_temp_new_i64(); rd =3D tcg_temp_new_i64(); for (pass =3D 0; pass < (a->q ? 2 : 1); pass++) { - neon_load_reg64(rm, a->vm + pass); - neon_load_reg64(rd, a->vd + pass); - neon_store_reg64(rm, a->vd + pass); - neon_store_reg64(rd, a->vm + pass); + read_neon_element64(rm, a->vm, pass, MO_64); + read_neon_element64(rd, a->vd, pass, MO_64); + write_neon_element64(rm, a->vd, pass, MO_64); + write_neon_element64(rd, a->vm, pass, MO_64); } tcg_temp_free_i64(rm); tcg_temp_free_i64(rd); --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337746; cv=none; d=zohomail.com; s=zohoarc; b=h4ZvthnuzIOR7EJlSP+vc6ixMbSEOTNUb6iKo+ihwqTlm1zrfCrlp8urFLX1vOsLHa/DO3pEId5k49ORw0SmoYAlSOH1yQRRjZDOK7TK6Z7Ms4IcwUKcpi9SwS0XBYbVeYLQ5G2bqrX7IlndmNtoVu3JMk/E50FKd6Zh1aHYVvk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337746; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson The only uses of this function are for loading VFP double-precision values, and nothing to do with NEON. Signed-off-by: Richard Henderson Message-id: 20201030022618.785675-10-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 8 ++-- target/arm/translate-vfp.c.inc | 84 +++++++++++++++++----------------- 2 files changed, 46 insertions(+), 46 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 4fb0a62200f..7611c1f0f15 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1132,14 +1132,14 @@ static long vfp_reg_offset(bool dp, unsigned reg) } } =20 -static inline void neon_load_reg64(TCGv_i64 var, int reg) +static inline void vfp_load_reg64(TCGv_i64 var, int reg) { - tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(1, reg)); + tcg_gen_ld_i64(var, cpu_env, vfp_reg_offset(true, reg)); } =20 -static inline void neon_store_reg64(TCGv_i64 var, int reg) +static inline void vfp_store_reg64(TCGv_i64 var, int reg) { - tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); + tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(true, reg)); } =20 static inline void vfp_load_reg32(TCGv_i32 var, int reg) diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index d2a9b658bbd..f966de5b1f8 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -236,8 +236,8 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) tcg_gen_ext_i32_i64(nf, cpu_NF); tcg_gen_ext_i32_i64(vf, cpu_VF); =20 - neon_load_reg64(frn, rn); - neon_load_reg64(frm, rm); + vfp_load_reg64(frn, rn); + vfp_load_reg64(frm, rm); switch (a->cc) { case 0: /* eq: Z */ tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, @@ -264,7 +264,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) tcg_temp_free_i64(tmp); break; } - neon_store_reg64(dest, rd); + vfp_store_reg64(dest, rd); tcg_temp_free_i64(frn); tcg_temp_free_i64(frm); tcg_temp_free_i64(dest); @@ -385,9 +385,9 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) TCGv_i64 tcg_res; tcg_op =3D tcg_temp_new_i64(); tcg_res =3D tcg_temp_new_i64(); - neon_load_reg64(tcg_op, rm); + vfp_load_reg64(tcg_op, rm); gen_helper_rintd(tcg_res, tcg_op, fpst); - neon_store_reg64(tcg_res, rd); + vfp_store_reg64(tcg_res, rd); tcg_temp_free_i64(tcg_op); tcg_temp_free_i64(tcg_res); } else { @@ -463,7 +463,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) tcg_double =3D tcg_temp_new_i64(); tcg_res =3D tcg_temp_new_i64(); tcg_tmp =3D tcg_temp_new_i32(); - neon_load_reg64(tcg_double, rm); + vfp_load_reg64(tcg_double, rm); if (is_signed) { gen_helper_vfp_tosld(tcg_res, tcg_double, tcg_shift, fpst); } else { @@ -1002,9 +1002,9 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_V= LDR_VSTR_dp *a) tmp =3D tcg_temp_new_i64(); if (a->l) { gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); - neon_store_reg64(tmp, a->vd); + vfp_store_reg64(tmp, a->vd); } else { - neon_load_reg64(tmp, a->vd); + vfp_load_reg64(tmp, a->vd); gen_aa32_st64(s, tmp, addr, get_mem_index(s)); } tcg_temp_free_i64(tmp); @@ -1149,10 +1149,10 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg= _VLDM_VSTM_dp *a) if (a->l) { /* load */ gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); - neon_store_reg64(tmp, a->vd + i); + vfp_store_reg64(tmp, a->vd + i); } else { /* store */ - neon_load_reg64(tmp, a->vd + i); + vfp_load_reg64(tmp, a->vd + i); gen_aa32_st64(s, tmp, addr, get_mem_index(s)); } tcg_gen_addi_i32(addr, addr, offset); @@ -1416,15 +1416,15 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3O= pDPFn *fn, fd =3D tcg_temp_new_i64(); fpst =3D fpstatus_ptr(FPST_FPCR); =20 - neon_load_reg64(f0, vn); - neon_load_reg64(f1, vm); + vfp_load_reg64(f0, vn); + vfp_load_reg64(f1, vm); =20 for (;;) { if (reads_vd) { - neon_load_reg64(fd, vd); + vfp_load_reg64(fd, vd); } fn(fd, f0, f1, fpst); - neon_store_reg64(fd, vd); + vfp_store_reg64(fd, vd); =20 if (veclen =3D=3D 0) { break; @@ -1433,10 +1433,10 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3O= pDPFn *fn, veclen--; vd =3D vfp_advance_dreg(vd, delta_d); vn =3D vfp_advance_dreg(vn, delta_d); - neon_load_reg64(f0, vn); + vfp_load_reg64(f0, vn); if (delta_m) { vm =3D vfp_advance_dreg(vm, delta_m); - neon_load_reg64(f1, vm); + vfp_load_reg64(f1, vm); } } =20 @@ -1599,11 +1599,11 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2O= pDPFn *fn, int vd, int vm) f0 =3D tcg_temp_new_i64(); fd =3D tcg_temp_new_i64(); =20 - neon_load_reg64(f0, vm); + vfp_load_reg64(f0, vm); =20 for (;;) { fn(fd, f0); - neon_store_reg64(fd, vd); + vfp_store_reg64(fd, vd); =20 if (veclen =3D=3D 0) { break; @@ -1613,7 +1613,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) /* single source one-many */ while (veclen--) { vd =3D vfp_advance_dreg(vd, delta_d); - neon_store_reg64(fd, vd); + vfp_store_reg64(fd, vd); } break; } @@ -1622,7 +1622,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) veclen--; vd =3D vfp_advance_dreg(vd, delta_d); vd =3D vfp_advance_dreg(vm, delta_m); - neon_load_reg64(f0, vm); + vfp_load_reg64(f0, vm); } =20 tcg_temp_free_i64(f0); @@ -2173,20 +2173,20 @@ static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp = *a, bool neg_n, bool neg_d) vm =3D tcg_temp_new_i64(); vd =3D tcg_temp_new_i64(); =20 - neon_load_reg64(vn, a->vn); - neon_load_reg64(vm, a->vm); + vfp_load_reg64(vn, a->vn); + vfp_load_reg64(vm, a->vm); if (neg_n) { /* VFNMS, VFMS */ gen_helper_vfp_negd(vn, vn); } - neon_load_reg64(vd, a->vd); + vfp_load_reg64(vd, a->vd); if (neg_d) { /* VFNMA, VFNMS */ gen_helper_vfp_negd(vd, vd); } fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_vfp_muladdd(vd, vn, vm, vd, fpst); - neon_store_reg64(vd, a->vd); + vfp_store_reg64(vd, a->vd); =20 tcg_temp_free_ptr(fpst); tcg_temp_free_i64(vn); @@ -2325,7 +2325,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) fd =3D tcg_const_i64(vfp_expand_imm(MO_64, a->imm)); =20 for (;;) { - neon_store_reg64(fd, vd); + vfp_store_reg64(fd, vd); =20 if (veclen =3D=3D 0) { break; @@ -2480,11 +2480,11 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP= _dp *a) vd =3D tcg_temp_new_i64(); vm =3D tcg_temp_new_i64(); =20 - neon_load_reg64(vd, a->vd); + vfp_load_reg64(vd, a->vd); if (a->z) { tcg_gen_movi_i64(vm, 0); } else { - neon_load_reg64(vm, a->vm); + vfp_load_reg64(vm, a->vm); } =20 if (a->e) { @@ -2557,7 +2557,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_V= CVT_f64_f16 *a) tcg_gen_ld16u_i32(tmp, cpu_env, vfp_f16_offset(a->vm, a->t)); vd =3D tcg_temp_new_i64(); gen_helper_vfp_fcvt_f16_to_f64(vd, tmp, fpst, ahp_mode); - neon_store_reg64(vd, a->vd); + vfp_store_reg64(vd, a->vd); tcg_temp_free_i32(ahp_mode); tcg_temp_free_ptr(fpst); tcg_temp_free_i32(tmp); @@ -2621,7 +2621,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_V= CVT_f16_f64 *a) tmp =3D tcg_temp_new_i32(); vm =3D tcg_temp_new_i64(); =20 - neon_load_reg64(vm, a->vm); + vfp_load_reg64(vm, a->vm); gen_helper_vfp_fcvt_f64_to_f16(tmp, vm, fpst, ahp_mode); tcg_temp_free_i64(vm); tcg_gen_st16_i32(tmp, cpu_env, vfp_f16_offset(a->vd, a->t)); @@ -2700,10 +2700,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VR= INTR_dp *a) } =20 tmp =3D tcg_temp_new_i64(); - neon_load_reg64(tmp, a->vm); + vfp_load_reg64(tmp, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rintd(tmp, tmp, fpst); - neon_store_reg64(tmp, a->vd); + vfp_store_reg64(tmp, a->vd); tcg_temp_free_ptr(fpst); tcg_temp_free_i64(tmp); return true; @@ -2789,13 +2789,13 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VR= INTZ_dp *a) } =20 tmp =3D tcg_temp_new_i64(); - neon_load_reg64(tmp, a->vm); + vfp_load_reg64(tmp, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR); tcg_rmode =3D tcg_const_i32(float_round_to_zero); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); gen_helper_rintd(tmp, tmp, fpst); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); - neon_store_reg64(tmp, a->vd); + vfp_store_reg64(tmp, a->vd); tcg_temp_free_ptr(fpst); tcg_temp_free_i64(tmp); tcg_temp_free_i32(tcg_rmode); @@ -2871,10 +2871,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VR= INTX_dp *a) } =20 tmp =3D tcg_temp_new_i64(); - neon_load_reg64(tmp, a->vm); + vfp_load_reg64(tmp, a->vm); fpst =3D fpstatus_ptr(FPST_FPCR); gen_helper_rintd_exact(tmp, tmp, fpst); - neon_store_reg64(tmp, a->vd); + vfp_store_reg64(tmp, a->vd); tcg_temp_free_ptr(fpst); tcg_temp_free_i64(tmp); return true; @@ -2902,7 +2902,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s= p *a) vd =3D tcg_temp_new_i64(); vfp_load_reg32(vm, a->vm); gen_helper_vfp_fcvtds(vd, vm, cpu_env); - neon_store_reg64(vd, a->vd); + vfp_store_reg64(vd, a->vd); tcg_temp_free_i32(vm); tcg_temp_free_i64(vd); return true; @@ -2928,7 +2928,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d= p *a) =20 vd =3D tcg_temp_new_i32(); vm =3D tcg_temp_new_i64(); - neon_load_reg64(vm, a->vm); + vfp_load_reg64(vm, a->vm); gen_helper_vfp_fcvtsd(vd, vm, cpu_env); vfp_store_reg32(vd, a->vd); tcg_temp_free_i32(vd); @@ -3024,7 +3024,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) /* u32 -> f64 */ gen_helper_vfp_uitod(vd, vm, fpst); } - neon_store_reg64(vd, a->vd); + vfp_store_reg64(vd, a->vd); tcg_temp_free_i32(vm); tcg_temp_free_i64(vd); tcg_temp_free_ptr(fpst); @@ -3055,7 +3055,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) =20 vm =3D tcg_temp_new_i64(); vd =3D tcg_temp_new_i32(); - neon_load_reg64(vm, a->vm); + vfp_load_reg64(vm, a->vm); gen_helper_vjcvt(vd, vm, cpu_env); vfp_store_reg32(vd, a->vd); tcg_temp_free_i64(vm); @@ -3204,7 +3204,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) frac_bits =3D (a->opc & 1) ? (32 - a->imm) : (16 - a->imm); =20 vd =3D tcg_temp_new_i64(); - neon_load_reg64(vd, a->vd); + vfp_load_reg64(vd, a->vd); =20 fpst =3D fpstatus_ptr(FPST_FPCR); shift =3D tcg_const_i32(frac_bits); @@ -3239,7 +3239,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) g_assert_not_reached(); } =20 - neon_store_reg64(vd, a->vd); + vfp_store_reg64(vd, a->vd); tcg_temp_free_i64(vd); tcg_temp_free_i32(shift); tcg_temp_free_ptr(fpst); @@ -3340,7 +3340,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) fpst =3D fpstatus_ptr(FPST_FPCR); vm =3D tcg_temp_new_i64(); vd =3D tcg_temp_new_i32(); - neon_load_reg64(vm, a->vm); + vfp_load_reg64(vm, a->vm); =20 if (a->s) { if (a->rz) { --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337546; cv=none; d=zohomail.com; s=zohoarc; b=QJsufvB6ZvbCsLmfw9IvwO0JfR9ZzohyhFIa7mryk2PEIt9e9F6OX4BcTMluNqUvA8vuP8RD7hFBc43c6aPS9yJd8Y3GSm1asrriJFZG3T3BIfKihxASSAKO1wUqtSVyoLrC41vYNeIA2IIZfRLK5NpgmXD9g5sQxCvjnhB9Z+A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337546; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ddc3YHEWydM8IrInAbVJszIYA0TZHXyS/v+Zbs+mUmc=; b=fLJg6qnFQa21DSY1ovbs+RAk6JTQNuQamdDkHAbcf9jT58yjN256sQSRcZ+P7KTMIv7t8d6YXQHvhNeau5lbx9mqr1Pym541m7yLUb0YKcNAsqez1+sTYM9WTFlzT9uR/WW4PuWCeV5qtEQvPxL9E4SLRgw+V2apKQtNcioll+E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337546750471.1969299399899; Mon, 2 Nov 2020 09:19:06 -0800 (PST) Received: from localhost ([::1]:40466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdU1-0004HX-Ex for importer@patchew.org; Mon, 02 Nov 2020 12:19:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53886) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLn-0000sl-Sa for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:35 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:33118) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLj-0006ZX-QQ for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:35 -0500 Received: by mail-wr1-x434.google.com with SMTP id b8so15525449wrn.0 for ; Mon, 02 Nov 2020 09:10:30 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ddc3YHEWydM8IrInAbVJszIYA0TZHXyS/v+Zbs+mUmc=; b=UTqJjLn4noqjXwzjUQY2mEvUC8aasVxYugDeo8R1WlJjxCC436FloXRYOvWDZLlrOK ai+yzCti+2Iri1te6jpDicU0LNtFTmnFHRM1xlxOZtZ6lkq4oF+xwUJJkuMjsTLN1ygT tdDjtdXKli9QsJ0O9N5JkbrVtqElch/zr/VjevVZ1jv82Ej/+03JEKYq4NZ5jFj5YHK8 J95EeDdBiQi5N2e3ekQBBkxECmlIOZVntU+VW/opnE7gkDzxYb7tDymTNsCpRANipUzk d5TM2FS3BYFACZoGpSIUAZ6G1Lnw0Hr/6pv2wKnbhTwKHuHIwDVefiozt56tJowJpcA0 5T/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ddc3YHEWydM8IrInAbVJszIYA0TZHXyS/v+Zbs+mUmc=; b=mO+uW+SPF8cv/+jl517o4wjjnDBOn+qYqf42UQWuhMRdv8RP8DxEHTgjsxwooyrAc6 XBG0Yc7wGqS1KD0zdzNFmQfUDvqG5Ii2cEsC4tu16f68NGNE04Qu8XRXLQn9mAj7pKnT i5v8bfKEqFFZd6eUJbtSGHmDcGV/Mxi0iUc5YWdpxOD3lVrKQfzt7OM6OrapmdGXsMN7 889M7UCUuPmNPCQPEr3Z1f5s/sLjW791tgwU+vYr0IFwc6+Z139C0G8TyhZm/vCtk85u ZKj+PZ4kLOlnf583E09Fr+vK2SXDueoRCHjGS6GmuDL8bzPv52K5wYsrA7IkeQ7a77w+ 8LZQ== X-Gm-Message-State: AOAM530IfGUN2FPLkyozusbPPJCyPxm4E1NuHhxcbVVGwmJDlQPLSFDn KH89PZ5/oQyZd+0MOO3VnNOEDRCVUcC+IA== X-Google-Smtp-Source: ABdhPJws6CUIea6XKfrECu/IcOgh3WXIH2KQJzOzMbjMmEQKsWQDzny1/oOr0vvIJ65K/J/uFSxQLQ== X-Received: by 2002:a5d:534d:: with SMTP id t13mr20582512wrv.69.1604337029421; Mon, 02 Nov 2020 09:10:29 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/26] target/arm: Simplify do_long_3d and do_2scalar_long Date: Mon, 2 Nov 2020 17:09:49 +0000 Message-Id: <20201102171005.30690-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson In both cases, we can sink the write-back and perform the accumulate into the normal destination temps. Signed-off-by: Richard Henderson Message-id: 20201030022618.785675-11-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-neon.c.inc | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index c2d67160f9e..1c16c56e7ec 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -2037,17 +2037,14 @@ static bool do_long_3d(DisasContext *s, arg_3diff *= a, if (accfn) { tmp =3D tcg_temp_new_i64(); read_neon_element64(tmp, a->vd, 0, MO_64); - accfn(tmp, tmp, rd0); - write_neon_element64(tmp, a->vd, 0, MO_64); + accfn(rd0, tmp, rd0); read_neon_element64(tmp, a->vd, 1, MO_64); - accfn(tmp, tmp, rd1); - write_neon_element64(tmp, a->vd, 1, MO_64); + accfn(rd1, tmp, rd1); tcg_temp_free_i64(tmp); - } else { - write_neon_element64(rd0, a->vd, 0, MO_64); - write_neon_element64(rd1, a->vd, 1, MO_64); } =20 + write_neon_element64(rd0, a->vd, 0, MO_64); + write_neon_element64(rd1, a->vd, 1, MO_64); tcg_temp_free_i64(rd0); tcg_temp_free_i64(rd1); =20 @@ -2670,16 +2667,14 @@ static bool do_2scalar_long(DisasContext *s, arg_2s= calar *a, if (accfn) { TCGv_i64 t64 =3D tcg_temp_new_i64(); read_neon_element64(t64, a->vd, 0, MO_64); - accfn(t64, t64, rn0_64); - write_neon_element64(t64, a->vd, 0, MO_64); + accfn(rn0_64, t64, rn0_64); read_neon_element64(t64, a->vd, 1, MO_64); - accfn(t64, t64, rn1_64); - write_neon_element64(t64, a->vd, 1, MO_64); + accfn(rn1_64, t64, rn1_64); tcg_temp_free_i64(t64); - } else { - write_neon_element64(rn0_64, a->vd, 0, MO_64); - write_neon_element64(rn1_64, a->vd, 1, MO_64); } + + write_neon_element64(rn0_64, a->vd, 0, MO_64); + write_neon_element64(rn1_64, a->vd, 1, MO_64); tcg_temp_free_i64(rn0_64); tcg_temp_free_i64(rn1_64); return true; --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337190; cv=none; d=zohomail.com; s=zohoarc; b=XucrRaq4XjiBnE4+93/l+lmlBbCxjTQtJDH7hMwyzlTeY0HVwkxYUPFFsTF4Jl99E+Im2jKdz9mhneNqCUtFss99w5sbl8IIT+G3cZ4N1RJpH+CdsUfBk2/C/LAF/6IM+Mp5m7iIiWNNeKrQ+OlCV/sJCNKVTXsX9cy9y7mQsjc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337190; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7fby/0TuuZpYxtRHhQs2DBDavF3wDEA6qD1fHKLIF9A=; b=HkhNWBleNIFXvIsnyOo7vRfhUGeJsc9lmN3fvaivaMEv0bFqW6fCPeyT8VDLJ4JxRiaAL16l8LwL5LujvXeQM8r1YxIIXZO1wg0bpy8/K4zzrBpCg6HGTfE5DywJyAMseuzy9tz6uiO6GrpTh4nZFmqX99AmXAoATJxwICthdWc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337190800748.7630567907421; Mon, 2 Nov 2020 09:13:10 -0800 (PST) Received: from localhost ([::1]:48024 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdOI-0003uW-0p for importer@patchew.org; Mon, 02 Nov 2020 12:13:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53914) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLr-0000vY-RY for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:39 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:37911) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLk-0006Zl-CM for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:37 -0500 Received: by mail-wm1-x343.google.com with SMTP id h62so5403179wme.3 for ; Mon, 02 Nov 2020 09:10:31 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7fby/0TuuZpYxtRHhQs2DBDavF3wDEA6qD1fHKLIF9A=; b=zhX270GYkb9gUVD5kQ1QWboUi4iVqUsk9q5vTs1tc//YBzWpyZg8X3KVo4JHRJjjBl c4n5ll9XJYbFQYVW1pSQIVOjiece/v/QOTuAznFDpWzBpKwBsDGphrJfK8sQxcTlQMXK t4XNefBNrc8VUxlInWmopxOVoSkcE506J21DRE6bD7Yqb0n8WtXGSLIF/95PKnH8HeSI jylWd08hP7+2/Z3qlmSYq3TK+1dONNO2d8BqE3t6WhD2uc8yI4I79Xq2yF+MpYRpZ5xW /SsEcVRhaGiTaqsIS1b6DoGILX1fDeX9P1cSsAYBsmIJweVV+m//lmwIZeq5i/aMdE3z Y4ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7fby/0TuuZpYxtRHhQs2DBDavF3wDEA6qD1fHKLIF9A=; b=OYG6udx95p/4e40YaF2TTE3q6AlcdBtZ3SJZF9h3v6oFpl8VVW9ph3BSq5eou/cs6V 4TpxtSDPC0dPXLns3LRUX68leVEGXEF18Ekar9mtXRYWtras6QcPi7KQfgBqYc0wTlQI og8NOOmzipOcuFi1hLQGaeORioMdc9vkYNV7Eyn0uxWCof9tzCyANYwWJZIV+/nbg0Mq siPVs12C4Jk0/7z5gvtVMEMkodqs6K3ep1Jc6XsOjh/q6YmNP4VhV/rDCKWCwl78HcNx 32iEiFDApEiPaPKKaGcC3ENgN6DKWD1tj9cCdhh1+btHjhQXwBK4IvPXWtCTtb8RPSST sBXw== X-Gm-Message-State: AOAM532viFNtIqVILvYYf5pwIh62jH539dmdFnODI4ASwBTBbOW6tq0s jB19c7ozyeayXqLaC1uxuBDD5wKrjObcdw== X-Google-Smtp-Source: ABdhPJywUHQdnaFIQ/lAaydRr5E3DfKY7Hn99KzeA2Jcn9K5/d6JO9tujQ6BBnkw0WKUqXynOZHOWw== X-Received: by 2002:a1c:9e0e:: with SMTP id h14mr18312868wme.18.1604337030649; Mon, 02 Nov 2020 09:10:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/26] target/arm: Improve do_prewiden_3d Date: Mon, 2 Nov 2020 17:09:50 +0000 Message-Id: <20201102171005.30690-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We can use proper widening loads to extend 32-bit inputs, and skip the "widenfn" step. Signed-off-by: Richard Henderson Message-id: 20201030022618.785675-12-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate.c | 6 +++ target/arm/translate-neon.c.inc | 66 ++++++++++++++++++--------------- 2 files changed, 43 insertions(+), 29 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 7611c1f0f15..29ea1eb7811 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1183,6 +1183,12 @@ static void read_neon_element64(TCGv_i64 dest, int r= eg, int ele, MemOp memop) long off =3D neon_element_offset(reg, ele, memop); =20 switch (memop) { + case MO_SL: + tcg_gen_ld32s_i64(dest, cpu_env, off); + break; + case MO_UL: + tcg_gen_ld32u_i64(dest, cpu_env, off); + break; case MO_Q: tcg_gen_ld_i64(dest, cpu_env, off); break; diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index 1c16c56e7ec..59368cb2436 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -1788,11 +1788,10 @@ static bool trans_Vimm_1r(DisasContext *s, arg_1reg= _imm *a) static bool do_prewiden_3d(DisasContext *s, arg_3diff *a, NeonGenWidenFn *widenfn, NeonGenTwo64OpFn *opfn, - bool src1_wide) + int src1_mop, int src2_mop) { /* 3-regs different lengths, prewidening case (VADDL/VSUBL/VAADW/VSUBW= ) */ TCGv_i64 rn0_64, rn1_64, rm_64; - TCGv_i32 rm; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -1804,12 +1803,12 @@ static bool do_prewiden_3d(DisasContext *s, arg_3di= ff *a, return false; } =20 - if (!widenfn || !opfn) { + if (!opfn) { /* size =3D=3D 3 case, which is an entirely different insn group */ return false; } =20 - if ((a->vd & 1) || (src1_wide && (a->vn & 1))) { + if ((a->vd & 1) || (src1_mop =3D=3D MO_Q && (a->vn & 1))) { return false; } =20 @@ -1821,40 +1820,48 @@ static bool do_prewiden_3d(DisasContext *s, arg_3di= ff *a, rn1_64 =3D tcg_temp_new_i64(); rm_64 =3D tcg_temp_new_i64(); =20 - if (src1_wide) { - read_neon_element64(rn0_64, a->vn, 0, MO_64); + if (src1_mop >=3D 0) { + read_neon_element64(rn0_64, a->vn, 0, src1_mop); } else { TCGv_i32 tmp =3D tcg_temp_new_i32(); read_neon_element32(tmp, a->vn, 0, MO_32); widenfn(rn0_64, tmp); tcg_temp_free_i32(tmp); } - rm =3D tcg_temp_new_i32(); - read_neon_element32(rm, a->vm, 0, MO_32); + if (src2_mop >=3D 0) { + read_neon_element64(rm_64, a->vm, 0, src2_mop); + } else { + TCGv_i32 tmp =3D tcg_temp_new_i32(); + read_neon_element32(tmp, a->vm, 0, MO_32); + widenfn(rm_64, tmp); + tcg_temp_free_i32(tmp); + } =20 - widenfn(rm_64, rm); - tcg_temp_free_i32(rm); opfn(rn0_64, rn0_64, rm_64); =20 /* * Load second pass inputs before storing the first pass result, to * avoid incorrect results if a narrow input overlaps with the result. */ - if (src1_wide) { - read_neon_element64(rn1_64, a->vn, 1, MO_64); + if (src1_mop >=3D 0) { + read_neon_element64(rn1_64, a->vn, 1, src1_mop); } else { TCGv_i32 tmp =3D tcg_temp_new_i32(); read_neon_element32(tmp, a->vn, 1, MO_32); widenfn(rn1_64, tmp); tcg_temp_free_i32(tmp); } - rm =3D tcg_temp_new_i32(); - read_neon_element32(rm, a->vm, 1, MO_32); + if (src2_mop >=3D 0) { + read_neon_element64(rm_64, a->vm, 1, src2_mop); + } else { + TCGv_i32 tmp =3D tcg_temp_new_i32(); + read_neon_element32(tmp, a->vm, 1, MO_32); + widenfn(rm_64, tmp); + tcg_temp_free_i32(tmp); + } =20 write_neon_element64(rn0_64, a->vd, 0, MO_64); =20 - widenfn(rm_64, rm); - tcg_temp_free_i32(rm); opfn(rn1_64, rn1_64, rm_64); write_neon_element64(rn1_64, a->vd, 1, MO_64); =20 @@ -1865,14 +1872,13 @@ static bool do_prewiden_3d(DisasContext *s, arg_3di= ff *a, return true; } =20 -#define DO_PREWIDEN(INSN, S, EXT, OP, SRC1WIDE) \ +#define DO_PREWIDEN(INSN, S, OP, SRC1WIDE, SIGN) \ static bool trans_##INSN##_3d(DisasContext *s, arg_3diff *a) \ { \ static NeonGenWidenFn * const widenfn[] =3D { \ gen_helper_neon_widen_##S##8, \ gen_helper_neon_widen_##S##16, \ - tcg_gen_##EXT##_i32_i64, \ - NULL, \ + NULL, NULL, \ }; \ static NeonGenTwo64OpFn * const addfn[] =3D { \ gen_helper_neon_##OP##l_u16, \ @@ -1880,18 +1886,20 @@ static bool do_prewiden_3d(DisasContext *s, arg_3di= ff *a, tcg_gen_##OP##_i64, \ NULL, \ }; \ - return do_prewiden_3d(s, a, widenfn[a->size], \ - addfn[a->size], SRC1WIDE); \ + int narrow_mop =3D a->size =3D=3D MO_32 ? MO_32 | SIGN : -1; = \ + return do_prewiden_3d(s, a, widenfn[a->size], addfn[a->size], \ + SRC1WIDE ? MO_Q : narrow_mop, \ + narrow_mop); \ } =20 -DO_PREWIDEN(VADDL_S, s, ext, add, false) -DO_PREWIDEN(VADDL_U, u, extu, add, false) -DO_PREWIDEN(VSUBL_S, s, ext, sub, false) -DO_PREWIDEN(VSUBL_U, u, extu, sub, false) -DO_PREWIDEN(VADDW_S, s, ext, add, true) -DO_PREWIDEN(VADDW_U, u, extu, add, true) -DO_PREWIDEN(VSUBW_S, s, ext, sub, true) -DO_PREWIDEN(VSUBW_U, u, extu, sub, true) +DO_PREWIDEN(VADDL_S, s, add, false, MO_SIGN) +DO_PREWIDEN(VADDL_U, u, add, false, 0) +DO_PREWIDEN(VSUBL_S, s, sub, false, MO_SIGN) +DO_PREWIDEN(VSUBL_U, u, sub, false, 0) +DO_PREWIDEN(VADDW_S, s, add, true, MO_SIGN) +DO_PREWIDEN(VADDW_U, u, add, true, 0) +DO_PREWIDEN(VSUBW_S, s, sub, true, MO_SIGN) +DO_PREWIDEN(VSUBW_U, u, sub, true, 0) =20 static bool do_narrow_3d(DisasContext *s, arg_3diff *a, NeonGenTwo64OpFn *opfn, NeonGenNarrowFn *narrowfn) --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337714; cv=none; d=zohomail.com; s=zohoarc; b=blgfkryhgpZVj+EqMxCeU+IehHeQk3aVhcKLzlpCKGPs4FFop+qKLJiBdWbJpAEYbls09zEs/2PMxY5ajBcKZ/x9nMxbhTvbqKVHWFIVmWCuBvMXKWZUza5evvlFAfy1jzdYRJWLfzuS78qJxPBEsBDbEaowQ21sTKNBRyUeMpQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337714; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zPF6mATGfZ3Q00cd72hKcOuI3Yqf5RM33+sscUSh8oA=; b=myyfkxwaQ0xgSxMwxLCYk6Og8GE/xJxU2kbvID23berSG0xOLbDVPuIsF/SBhkleEmjRRC7XC0lsmu5nldL+j99Ti5v9s6AeW7MbnxBbwUYxhsyhWyz7UqtevLkSoQaL+2XtUV2KAclfMv4AYrPxbxbRtswJu6jgtFagHhyWSes= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337714559532.7265404373769; Mon, 2 Nov 2020 09:21:54 -0800 (PST) Received: from localhost ([::1]:48938 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdWj-0007vh-Eh for importer@patchew.org; Mon, 02 Nov 2020 12:21:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53916) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLr-0000vb-Sl for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:41 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:39184) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLl-0006Zu-MZ for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:39 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 205so2471593wma.4 for ; Mon, 02 Nov 2020 09:10:33 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zPF6mATGfZ3Q00cd72hKcOuI3Yqf5RM33+sscUSh8oA=; b=mIHmdGY89oAsL8rM6wXS/HEZu0NUX0HyXPTgBgYVVznyvLYva/z2p0gUFKRp6qjJlV 2X1Es6ZUwCIIk8Xnt84WHBWyCj8480/o9XOidzyI9Z4UHAbYgLhdCjGrqa9tBhC2gK69 QISgJDMFNQ5O3KON8B1H/xrL03+aUGtXVrI/jb1Tdq4QNl9BqL/DQDWrytQ60qRrWuJP suJF5avIVoSCvk/INjxH2nAwVAErSPy1ZsqB8ir/ZDwK6cw5M1RpsBqWD98++8Var2OK GhnXa2xXxgMAPx8F7MZuqfEiuOUTvFseXAbJKs5ijcUhvGnlXZEuW8O4aKSwd4SCNCCC JGSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zPF6mATGfZ3Q00cd72hKcOuI3Yqf5RM33+sscUSh8oA=; b=hlwj9oJLhdFTFwrlZTuA+2TpvIZKjgbsKuvVS+4UGIkBKStIQnFuExx2cyVooOTyPd Xt4BF4SZEn4vQdGsG4ww0y1bGUW3C/mLNuAGe/7Y2sicrY7pqm8KQBNbzf/9lO8NOr6K Ibz5UpvCxcgpqX0RZyO4KnJnRymBdZiEIE8rCS0l7jkD/7JAPETvcR+NL9RdaBCr67hy Cea6erNaxKA3bqqpIfDV5MXGs0DcdItLSkisLR4qAs+TY2mRb2aDKrb5WQSEfC/N8o02 a12KAA6UXuau8XsJW5gDVQ1Dsdi/vuBCgyP0VagHrRqtLngPx0i0B2l0DuwJG2+nkgYJ APxQ== X-Gm-Message-State: AOAM530D8XMajh3kbgMo14Ccr/KUMrNyCU9FaLO1jULsOIRLu/dwRTtm SUpV75pIc4baTDPY8ICXYv2JtcyBK4yamg== X-Google-Smtp-Source: ABdhPJwBuJbkGdFnFF4IWTOS6NnZGJlwQKxIz9/+xvRxPMFWmGSRERjciLqBHqY0Bu847Wesvqv0xQ== X-Received: by 2002:a1c:2dc4:: with SMTP id t187mr18371235wmt.53.1604337031860; Mon, 02 Nov 2020 09:10:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/26] target/arm: Fix float16 pairwise Neon ops on big-endian hosts Date: Mon, 2 Nov 2020 17:09:51 +0000 Message-Id: <20201102171005.30690-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) In the neon_padd/pmax/pmin helpers for float16, a cut-and-paste error meant we were using the H4() address swizzler macro rather than the H2() which is required for 2-byte data. This had no effect on little-endian hosts but meant we put the result data into the destination Dreg in the wrong order on big-endian hosts. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20201028191712.4910-2-peter.maydell@linaro.org --- target/arm/vec_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index a973454e4f4..30d76d05beb 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -1858,10 +1858,10 @@ DO_ABA(gvec_uaba_d, uint64_t) r2 =3D float16_##OP(m[H2(0)], m[H2(1)], fpst); \ r3 =3D float16_##OP(m[H2(2)], m[H2(3)], fpst); \ \ - d[H4(0)] =3D r0; \ - d[H4(1)] =3D r1; \ - d[H4(2)] =3D r2; \ - d[H4(3)] =3D r3; \ + d[H2(0)] =3D r0; \ + d[H2(1)] =3D r1; \ + d[H2(2)] =3D r2; \ + d[H2(3)] =3D r3; \ } =20 DO_NEON_PAIRWISE(neon_padd, add) --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337351; cv=none; d=zohomail.com; s=zohoarc; b=JuZkaYyytENfbAwcy8nw4mY9VcAZ0lzO5XsLnwgldIaLUV3BVXA+gA/mYan7unZbs3h8m4v8fxqmiU2ejx3os68qlC/XulSAJQqxCNlgzndFQANXp6VLouQqDunmhdeIcdrma2HjNySyxt4tyR7Om2OqOMQVLQF0e/UpO7x2OOA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337351; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bF6PwLy/yI0XHBna/A/NHJlJMEtI1ZSu2nypD5iZDi0=; b=Wb22MSHywRASYXoSgLD4NJuYqQbktSS4rnWapEuPxXBgCIlEhvHCc0Q9EetRpDh5eztuIPr4CkYTmVJHtCZqmhXq7cGMfcDs+FE9l5Sr5LF3FlP9UomxrHf3fZZCmZqJ7pvKLPqM1hZpqTVBf1XEPZZriNgV8gdbN2EtNuK2Uzw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337351227143.66902504616337; Mon, 2 Nov 2020 09:15:51 -0800 (PST) Received: from localhost ([::1]:56182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdQs-0007JQ-FK for importer@patchew.org; Mon, 02 Nov 2020 12:15:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53948) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLt-0000vz-9D for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:41 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:45750) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLn-0006a3-Ie for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:40 -0500 Received: by mail-wr1-x42f.google.com with SMTP id a9so15467444wrg.12 for ; Mon, 02 Nov 2020 09:10:34 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bF6PwLy/yI0XHBna/A/NHJlJMEtI1ZSu2nypD5iZDi0=; b=HiTOm/aFhzuzQQnOnN3GhDnA5j3OcmgWkBlKj8w14AWt8I8f2rkdDo1xnVUmDXRYbn fE9eS0aYJzhWgdCtv5mWc6BMVlCKxWXDCfmZnfWajSdFqUne+sF2C+xAJl8LvrdDxRhK L+s3Q90CFYHCuamwmv6TxDf6MOs0tKIjt7/2PoyfSfvbCeNrIwV2AVj9fgIhNUlCXTk8 yshy2hG47HG3qT9MQVTeIc45k7Y3rds8rn/MySMtUQhIY70WB1MYAUdJF+U96q1sKOTV CSlnghGRawddats5p8jxwPg6Q5zs6fVXkU12OheZx+ZXeprrKJyxZs0yz0Zq+C1ZJ8to I/2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bF6PwLy/yI0XHBna/A/NHJlJMEtI1ZSu2nypD5iZDi0=; b=A5DJcgq4qUSZ3BlLc61gxCUsibHRQ9muHYP96Rrn6ndi1DNrbem/hr6SYlKMqhaQdA aDLyZZU2EJgxshg7SkRMxCm3Bq3Z3IJ5hKHjyuzjAjjO1ABJloJFZ3wl9falhcaAPcjV JDgo8f5l2uVYKMBbTbJrYcfpk3ajgl4QSp6POv9LTg0jNxtkLjazgxzyLmbpElalLAJ5 ioLWmvvYQ1Hp8ovpNOEerVwFRfzyDFdAKHheHnXpZGK5snV5S2iid9F19fSedH4Xsr0Y g7TcWBWZQ2CSUypZyIPBS2F28VnwjFMsaeh9ghB8D+iumQ6ONi3IKYG7uuTqa9cHUQ90 jyTw== X-Gm-Message-State: AOAM530CGjjo2isZSifu/3wJTPFML+mUfiU/bbgzzDMiHd0Z5EJnvCbN ukVD4NU+92lC4BMlIXT5ToZYYLpAGnU2aQ== X-Google-Smtp-Source: ABdhPJzPj8E5bykgwlMBxWB9FprtsHpXDuUKZqrn3TG0di0WNRFy8fa28qGIqIw2VLJ9outunfoNhg== X-Received: by 2002:adf:f74e:: with SMTP id z14mr21204569wrp.312.1604337033116; Mon, 02 Nov 2020 09:10:33 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/26] target/arm: Fix VUDOT/VSDOT (scalar) on big-endian hosts Date: Mon, 2 Nov 2020 17:09:52 +0000 Message-Id: <20201102171005.30690-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The helper functions for performing the udot/sdot operations against a scalar were not using an address-swizzling macro when converting the index of the scalar element into a pointer into the vm array. This had no effect on little-endian hosts but meant we generated incorrect results on big-endian hosts. For these insns, the index is indexing over group of 4 8-bit values, so 32 bits per indexed entity, and H4() is therefore what we want. (For Neon the only possible input indexes are 0 and 1.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20201028191712.4910-3-peter.maydell@linaro.org --- target/arm/vec_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 30d76d05beb..0f33127c4c4 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -293,7 +293,7 @@ void HELPER(gvec_sdot_idx_b)(void *vd, void *vn, void *= vm, uint32_t desc) intptr_t index =3D simd_data(desc); uint32_t *d =3D vd; int8_t *n =3D vn; - int8_t *m_indexed =3D (int8_t *)vm + index * 4; + int8_t *m_indexed =3D (int8_t *)vm + H4(index) * 4; =20 /* Notice the special case of opr_sz =3D=3D 8, from aa64/aa32 advsimd. * Otherwise opr_sz is a multiple of 16. @@ -324,7 +324,7 @@ void HELPER(gvec_udot_idx_b)(void *vd, void *vn, void *= vm, uint32_t desc) intptr_t index =3D simd_data(desc); uint32_t *d =3D vd; uint8_t *n =3D vn; - uint8_t *m_indexed =3D (uint8_t *)vm + index * 4; + uint8_t *m_indexed =3D (uint8_t *)vm + H4(index) * 4; =20 /* Notice the special case of opr_sz =3D=3D 8, from aa64/aa32 advsimd. * Otherwise opr_sz is a multiple of 16. --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337441; cv=none; d=zohomail.com; s=zohoarc; b=T5S+OA4RXnCFyjA4SwP7UEfAFiUZAMhOpeplkKqmWUShL7sWoondRM1zp9QZaeM1uM3NrE/eY/7hH7W1Pe7Iww0mQw25dKWZ8I8wrbyhHctgVbpB1bVd2MlmNyU6T9MzOpEmzAO6RPUKzpoQYirss9qMS8GsRZQiNC3/cjSBOaI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337441; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OEozF0m7quoDCvuv9KYsnQo/7jKMGFoMyuZr94zyBD4=; b=nkyMV1iqIMAFkC3HXPrfqFjJl+6iKYOYDAH5z2euWMaSW65r402/7y/Tgpqm2PjtfZI89RhaWA1/b6lDImGOM7PPCyS+tdo+HJ/S5KHJVljI3Z3HLt27LRqxZTDjAwQtMhxkqrugDySIyJ0PBg7MEECn4sNemkZ/7woI+aKhYQs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337441413457.96253871390525; Mon, 2 Nov 2020 09:17:21 -0800 (PST) Received: from localhost ([::1]:33184 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdSK-0001Hd-LI for importer@patchew.org; Mon, 02 Nov 2020 12:17:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLu-0000z3-IK for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:42 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:35358) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLp-0006aF-K6 for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:42 -0500 Received: by mail-wr1-x433.google.com with SMTP id n15so15538392wrq.2 for ; Mon, 02 Nov 2020 09:10:35 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OEozF0m7quoDCvuv9KYsnQo/7jKMGFoMyuZr94zyBD4=; b=HKpzIh2I6fjpdQ1XMY1MCHNOMt/nG1C3XMAXb6rv8aQLxxVn9TkO9kzyELw9cN3dLS GaPwXxs52FL4zxet+Kne0yMJSN+1sXWFjbe8XwICsC0bJ/jDBm6wiBxioswobTZNrQxT RCCA4hUQ+4Zkea2gUlG0wPbNx7K46HnHobiU2dxJjuE86ceAh2sNS99JczOCwFKBVBDd s0wmMKzEHgujwiVSLhkLWEsfu0y+67/yrT2rErq0PLaE32LMSKOQ3Ap+LjL/IMhnjucw BGpJlKUIAU+hw8X8BmJu18rp38IyE3uaINY5IcMb8SY2DZ1oPi83+DF29KRaTXEj2P6w U4yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OEozF0m7quoDCvuv9KYsnQo/7jKMGFoMyuZr94zyBD4=; b=cy5ZrK35c/2Ya2IWH7Zh56rRltNLkQNXUEbd+WTfDIdJdfNDGluzwRRmWGPwDbOKuU yy+SPRz+ngY1bbz9p5XDO9p1ahHpkxrU8jqcxOp+EfgCrgnVr8MSkxFNDZAUzjwyBrbw B0tGPrOjxS7PpJ1cxwS5P4e9atfgOLo0Ry967s1eQbQ2N0cVQiyGdua32437B6ZEra9a 9NMaAYQyqhzwDTVwoEPA6JCknBsO+uWwfy7WbuCc8j+wrPiXBBrv1geoSymDu7PuIOER Y1gh9UyIHZqNQbJ8nznOTa3mwIFQM5oNhH+7x+DGq74aei7pvMngl6vtEB8Xf1TOn0Oj r5kQ== X-Gm-Message-State: AOAM531vE/zgc+jpFUy+jWvooyd67nBOD5vxNFLDnaFr8jFlFPe/ik34 DiI3b/OpormQC6XRlQ6V/B/6hIG0OQWtuw== X-Google-Smtp-Source: ABdhPJxR2Zg/J62S0b/+T1Qhng7FsG4npXY6uT9qITyy+9QJ0sWDkE+ynHmcyuMXK1aPxrQOkbxmzQ== X-Received: by 2002:a5d:67ca:: with SMTP id n10mr21075052wrw.209.1604337034432; Mon, 02 Nov 2020 09:10:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/26] target/arm: fix handling of HCR.FB Date: Mon, 2 Nov 2020 17:09:53 +0000 Message-Id: <20201102171005.30690-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: R=C3=A9mi Denis-Courmont HCR should be applied when NS is set, not when it is cleared. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 97bb6b8c01b..dc51175bf05 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -731,13 +731,12 @@ static void tlbimvaa_is_write(CPUARMState *env, const= ARMCPRegInfo *ri, =20 /* * Non-IS variants of TLB operations are upgraded to - * IS versions if we are at NS EL1 and HCR_EL2.FB is set to + * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to * force broadcast of these operations. */ static bool tlb_force_broadcast(CPUARMState *env) { - return (env->cp15.hcr_el2 & HCR_FB) && - arm_current_el(env) =3D=3D 1 && arm_is_secure_below_el3(env); + return arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_FB); } =20 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337497; cv=none; d=zohomail.com; s=zohoarc; b=NYAHE+yFrk+TG2APdaNllGDr78eWUojL+6E8BV8gCeNwf1+8Ximvd0oL17837M83maLdadrqF3vMseVYf0fYQRml7afavWxEOe3nJlPOJ9Ty0Jp9NocUesvOtHQoV5/QUW4ZH9/c8y7AC63oZgfSGRTorJ9W+1y7bgHAwEybX04= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337497; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oS0wIyEvl6kAmgjQUcastyFGaftesb6oVP+8lJQGRmA=; b=Y1UPDeXy42d9lwMJT5hnV6kkx76Arrzfw+JuIVBMIuOgc65RYOH9SeVVeCjX1yaRURaZ73Zgm4FkcfM/ymn04JJW2GRMPDRtv/KOnuFkoTJpmui6Mepla7WtCHUNXM7scOoRfUr9GQnJgSlhvJjjC7hEwiblWBJPG5DcUY/WVQw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337497419322.4210485480495; Mon, 2 Nov 2020 09:18:17 -0800 (PST) Received: from localhost ([::1]:36388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdTE-0002ct-CW for importer@patchew.org; Mon, 02 Nov 2020 12:18:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53970) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLu-0000yB-6g for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:42 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:40587) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLr-0006at-JG for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:41 -0500 Received: by mail-wr1-x443.google.com with SMTP id 33so4707934wrl.7 for ; Mon, 02 Nov 2020 09:10:36 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oS0wIyEvl6kAmgjQUcastyFGaftesb6oVP+8lJQGRmA=; b=w6AK/ZU8E7lFeVE63BSJIzdZKFOLZf2Ex4ohEHQW3gUvWDN8Jvzh+EPSfjf9cBpLz7 KpNXTunV+/oY/ijxmkdP94ApH1c3tJxv7OX9y2lo6mI6Q5LTKuAWRxitVZtt35BlHp2L LPMiIUmVctrRK7UO/r+mWZ5RwnLgpC09dHMkPxd7K+SSGEFtV63iHFmkHk30dL0SYQRB Jd0oFNdY3FM+/oMlzSLnCu4bMjYZlQpMKlZ3hK6uE0gtirSOJUZHMZpUfx9HVXzulTjW 9Y+fSpe8Dib/mfMlL+Wcnd+yna5n5HqO6cTUK8cYP1oKP9AInJuVdKoPgTYndsUin0oD YwuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oS0wIyEvl6kAmgjQUcastyFGaftesb6oVP+8lJQGRmA=; b=s8iYz+9ku2DyjGtr5p3ExAq/EMVHl48habJ5ea6yjqE3mBj5dRz6eF6RGJfqY6Oz6v Y5qfMgcyhc8m6LpVMH/x4wfNfi8/e/2FlO8m3jhSR/tc3Hx0YyisPJjzB1khR3yZUkrO /oDySyEM0BO8pRvMsqEGUmKKvKblsg2q7ZpzXfHrPt0tQnPbkYhcG63HiAn9g6TxW18k Et92Z4WX/WQc+Jor8IXPWWzgNXZOtujyypLQNGdzAltK5j/VP7HloKjKBGIEmUs5HM7D IdVC/ZIiIviXZXNUYnEJGVuzUCGx3Fdoyp4KwjDzr3DUdub3T/4ZdFoJF+xCjGApXn8k Wlbg== X-Gm-Message-State: AOAM533gFkBS15AlyJcxSsKnejb/YdBeZq651Q8QVSK+F4qtzKhiPDq9 iJyi7wATrBRInE8bZWliFhhY4/9pjE+Ssg== X-Google-Smtp-Source: ABdhPJygreadJKuXOtZlJ9IkLEy6vxp5T8fWRWMRk4Sox4ohPl2vJZrjN+Klwr5VDEyID+poTYfwfA== X-Received: by 2002:adf:ba4f:: with SMTP id t15mr20633953wrg.335.1604337035495; Mon, 02 Nov 2020 09:10:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/26] target/arm: fix LORID_EL1 access check Date: Mon, 2 Nov 2020 17:09:54 +0000 Message-Id: <20201102171005.30690-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: R=C3=A9mi Denis-Courmont Secure mode is not exempted from checking SCR_EL3.TLOR, and in the future HCR_EL2.TLOR when S-EL2 is enabled. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index dc51175bf05..68545919865 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6679,9 +6679,10 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, c= onst ARMCPRegInfo *ri) #endif =20 /* Shared logic between LORID and the rest of the LOR* registers. - * Secure state has already been delt with. + * Secure state exclusion has already been dealt with. */ -static CPAccessResult access_lor_ns(CPUARMState *env) +static CPAccessResult access_lor_ns(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) { int el =3D arm_current_el(env); =20 @@ -6694,16 +6695,6 @@ static CPAccessResult access_lor_ns(CPUARMState *env) return CP_ACCESS_OK; } =20 -static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - if (arm_is_secure_below_el3(env)) { - /* Access ok in secure mode. */ - return CP_ACCESS_OK; - } - return access_lor_ns(env); -} - static CPAccessResult access_lor_other(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { @@ -6711,7 +6702,7 @@ static CPAccessResult access_lor_other(CPUARMState *e= nv, /* Access denied in secure mode. */ return CP_ACCESS_TRAP; } - return access_lor_ns(env); + return access_lor_ns(env, ri, isread); } =20 /* @@ -6738,7 +6729,7 @@ static const ARMCPRegInfo lor_reginfo[] =3D { .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 7, - .access =3D PL1_R, .accessfn =3D access_lorid, + .access =3D PL1_R, .accessfn =3D access_lor_ns, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, REGINFO_SENTINEL }; --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337929; cv=none; d=zohomail.com; s=zohoarc; b=mYLRm8ky253w98AjywLltsF94lV9N42hDXXWbv4beqiK+EWHePFZrApmWgH0aAEuqqNRfX9mHSa30YpV6FcgTaabEyR3gkkKjQFiFLpqQyfokGac8CWNC43RtNVVd1YWc4HDAMeXLlD8RdONpUSnh/b/5oUnGiwK0DBfJAAZjBc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337929; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bg1yVgXIhU8cNkSuYiD5wujRWcjW+EPEExJMC8FO3EU=; b=B7lcZ26/4BoxIRaIB2T/A/FQ/ApjfbQfXw4t4lJKhA9qQ9YFuDFIvQROjg7BNyOTFqhZ6vJyhBfRk/Z+pvLpoLE0/5aDRxD7FPIVTMQB10sqKHln6JOGFGAqOc0BCj6QKLptRL/051eijCh7jqIlWlsBfyDPcGqho397iwsCgEM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160433792983920.00557683579632; Mon, 2 Nov 2020 09:25:29 -0800 (PST) Received: from localhost ([::1]:58230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdaC-0003Ot-Lc for importer@patchew.org; Mon, 02 Nov 2020 12:25:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLv-00011m-Kr for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:43 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:50798) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLr-0006bN-Jk for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:43 -0500 Received: by mail-wm1-x332.google.com with SMTP id 13so10160138wmf.0 for ; Mon, 02 Nov 2020 09:10:37 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bg1yVgXIhU8cNkSuYiD5wujRWcjW+EPEExJMC8FO3EU=; b=FfItod380r8GFhUrvfdO2oC+R5iMdRkPL0yE9ITi01miSE5Vp6X+eIuAY8NBNSVzqd 49TzJgY1/hoGtbv64G95yJxSXzKMp97oubiV49ypDqHP0nwjgtvxzxshxGQDKFh3vxUo Su/xsouMu6IqytPsVCvEoJ4cSlgMGGN63LG4Kqu3Sr3MebQ3HA8w37mWEKGBPi/2HUPZ UO+iXfOCqSsLs5ioAnUJxXsP4CVKzGm/QsI77/MS9tbICAyRpuDoSnWW7dQ7DtS7tsQa plbh0ZYD1lazJi2/amU0N8R/n+EUGFtc8cT6ECV9boCZCdedhgNcyz1vyhGmyKmYVxlI Iw0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bg1yVgXIhU8cNkSuYiD5wujRWcjW+EPEExJMC8FO3EU=; b=hK6hUhW7qMDBkm8ILzScXZoV83qa/JYksOlkgdu4WS96qY4Dc/pdXDjEzJpmWufmMP gxLVfRgfkFm/AUhaAELChha98SYMsyZBwCdEOrflftiv7XB2ut3ZwkoXAcPc3CXQE2Pn q/dzswL4CxnNB/0B6ntcHseHnR0jXW94rDpJEyiKQX27GDqn5T9SCYnrLbIub+P0JLe5 6yL4id5yPlwjFbi93bfZwRBYu5SX5H3RaVAbZhAsSDlqCbpjXsI33O2yPX5nVSSm3mhp 6StsYBlvZheQTpanW9xPOTJdrTj/YYenjNBRC/S3O0Dq1MTCq/gH8Q94HGqIAqWORDoq nAQw== X-Gm-Message-State: AOAM532Nb7jhANhdv+dhnZYpYadePb+PRN9/YDaXLdkG0ul3kCaTMaZF ZGddOzyTDzlRCrBrhhN4nn/GAWyH17/CvA== X-Google-Smtp-Source: ABdhPJxDRwMB8Id+0cMXa5XNiDLumNhk4YUNmFQaqgWuqdAzVPUUQa1lxfMInJqCbFWBWC2dc3kZ8A== X-Received: by 2002:a1c:f604:: with SMTP id w4mr19088691wmc.87.1604337036503; Mon, 02 Nov 2020 09:10:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/26] disas/capstone: Fix monitor disassembly of >32 bytes Date: Mon, 2 Nov 2020 17:09:55 +0000 Message-Id: <20201102171005.30690-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) If we're using the capstone disassembler, disassembly of a run of instructions more than 32 bytes long disassembles the wrong data for instructions beyond the 32 byte mark: (qemu) xp /16x 0x100 0000000000000100: 0x00000005 0x54410001 0x00000001 0x00001000 0000000000000110: 0x00000000 0x00000004 0x54410002 0x3c000000 0000000000000120: 0x00000000 0x00000004 0x54410009 0x74736574 0000000000000130: 0x00000000 0x00000000 0x00000000 0x00000000 (qemu) xp /16i 0x100 0x00000100: 00000005 andeq r0, r0, r5 0x00000104: 54410001 strbpl r0, [r1], #-1 0x00000108: 00000001 andeq r0, r0, r1 0x0000010c: 00001000 andeq r1, r0, r0 0x00000110: 00000000 andeq r0, r0, r0 0x00000114: 00000004 andeq r0, r0, r4 0x00000118: 54410002 strbpl r0, [r1], #-2 0x0000011c: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c 0x00000120: 54410001 strbpl r0, [r1], #-1 0x00000124: 00000001 andeq r0, r0, r1 0x00000128: 00001000 andeq r1, r0, r0 0x0000012c: 00000000 andeq r0, r0, r0 0x00000130: 00000004 andeq r0, r0, r4 0x00000134: 54410002 strbpl r0, [r1], #-2 0x00000138: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c 0x0000013c: 00000000 andeq r0, r0, r0 Here the disassembly of 0x120..0x13f is using the data that is in 0x104..0x123. This is caused by passing the wrong value to the read_memory_func(). The intention is that at this point in the loop the 'cap_buf' buffer already contains 'csize' bytes of data for the instruction at guest addr 'pc', and we want to read in an extra 'tsize' bytes. Those extra bytes are therefore at 'pc + csize', not 'pc'. On the first time through the loop 'csize' happens to be zero, so the initial read of 32 bytes into cap_buf is correct and as long as the disassembly never needs to read more data we return the correct information. Use the correct guest address in the call to read_memory_func(). Cc: qemu-stable@nongnu.org Fixes: https://bugs.launchpad.net/qemu/+bug/1900779 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20201022132445.25039-1-peter.maydell@linaro.org --- disas/capstone.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/disas/capstone.c b/disas/capstone.c index 0a9ef9c8927..7462c0e3053 100644 --- a/disas/capstone.c +++ b/disas/capstone.c @@ -286,7 +286,7 @@ bool cap_disas_monitor(disassemble_info *info, uint64_t= pc, int count) =20 /* Make certain that we can make progress. */ assert(tsize !=3D 0); - info->read_memory_func(pc, cap_buf + csize, tsize, info); + info->read_memory_func(pc + csize, cap_buf + csize, tsize, info); csize +=3D tsize; =20 if (cs_disasm_iter(handle, &cbuf, &csize, &pc, insn)) { --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337559; cv=none; d=zohomail.com; s=zohoarc; b=iZbeuXmRCMkIO809usgA2HF4soLiJheYFiQuzNtBug9SBav8CgkxpW+WQn9WyQqK7B7oNgkyfB4Tl3rHQ54vjjJWh4paWXGGt1T+W7AGHyOPZZQyzmYsie3UmEptB/MVyqN9dt/hNq3EM8aSSbTMPEaicAVj/Yt3UJZpvHq193o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337559; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bsOcsFLrF4fremZGGn3w83VG5q1zGI8Vc4YzNY5qHV0=; b=cUuE3u8ceE8YVtfkygz6MaF8BtSUgmcdkoMQ7wZxnFEBwmlIS6mInYeFX7fCVqSYHQzMyDW5NfTm8VT/h2LDmtnTIH2Ji0xv7gKl9cHceL8uUlF4UwIlxRAhCUHJCgKFSEi+04V3c3XB4imHtU8GdhWWMdhyPt85DXk2iu5TRFw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337559312153.5464762619156; Mon, 2 Nov 2020 09:19:19 -0800 (PST) Received: from localhost ([::1]:41672 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdUD-0004lK-Ln for importer@patchew.org; Mon, 02 Nov 2020 12:19:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:53976) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLu-0000zg-Ra for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:42 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:33263) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLr-0006bn-Kt for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:42 -0500 Received: by mail-wm1-x331.google.com with SMTP id p19so1682060wmg.0 for ; Mon, 02 Nov 2020 09:10:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bsOcsFLrF4fremZGGn3w83VG5q1zGI8Vc4YzNY5qHV0=; b=mZd8NMuIp7Y8uEC7FswrXDeZmqhrNudvI8saNzmXLja17vqXxGb70SGeJ5zPjE2Ny+ I0i7vrUVXz+pyDbHAj4h1hGrynJxjo5QBm7PiEyONkNM25/5O9+dQQX1a64Rv76+bxkI AvnDnDEHAdyXlCLEOHOFmyAn3Mr5Qy6v4ChgeqWWl9xHyLcN5Qut8ARZaAgZQWj0SuH+ do3Q9LDAjyFt6nFlZnAYRp7EHeSxbUBgBKJTTtrWIwEgaM6yX91luJzyuxUS6huwfN89 7iEfG2w79azKuSxE3m17Hc6p1/HYzb/CdLzSgOVzgvwHCHxj97AA/Mm9D4NehtwW66Yl 3M6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bsOcsFLrF4fremZGGn3w83VG5q1zGI8Vc4YzNY5qHV0=; b=ogDZ+IDMUrT1fciXRuuYPGDqwscvFwyn3l8Ci89e2/9bYhaL8v5mUP88CSIrniMU17 laek17PhzjdzF+pwoJbiDhsQRGF6CQAnR/6ILGEyIuJp5j6bA4LwJaxB3lwRIYGoWmSz 43j+QD7ebxabe8g8Fw5oKFJ9D4hrEG0D9OsMRf59rytkHsz519RIYA2zj3TmW/7w+oGG ER8pLL2O49QttQgKvLziXLC5c0YWhTvjz0xBJVkSlclNneHjW8mlYAy5DcG7bztje0Tq 69/Xor5YySKlZmoHJHvjbQrlzVevqJu7qfqzgVLxsPndEVIRRiAjUX85tXWKTpveru28 mhXQ== X-Gm-Message-State: AOAM531OqTfvcW6HjumEzldtoHOF5GP1+0gN8qkePX3rE64UKDtlocbR ZT8HAJD68X50yijhedqF27UmMCcj73ATzA== X-Google-Smtp-Source: ABdhPJxcTF40fn/fDUopkWFpxLfLL7gDtXCdecYKosuK0A9/gbWxGX7oHNq5AQE5SROfm3RH7zHRuA== X-Received: by 2002:a7b:c201:: with SMTP id x1mr8239989wmi.42.1604337037641; Mon, 02 Nov 2020 09:10:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/26] hw/arm/smmuv3: Fix potential integer overflow (CID 1432363) Date: Mon, 2 Nov 2020 17:09:56 +0000 Message-Id: <20201102171005.30690-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 Use the BIT_ULL() macro to ensure we use 64-bit arithmetic. This fixes the following Coverity issue (OVERFLOW_BEFORE_WIDEN): CID 1432363 (#1 of 1): Unintentional integer overflow: overflow_before_widen: Potentially overflowing expression 1 << scale with type int (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type hwaddr (64 bits, unsigned). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Eric Auger Message-id: 20201030144617.1535064-1-philmd@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/smmuv3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 2017ba7a5a7..22607c37841 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -17,6 +17,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/bitops.h" #include "hw/irq.h" #include "hw/sysbus.h" #include "migration/vmstate.h" @@ -864,7 +865,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cm= d) scale =3D CMD_SCALE(cmd); num =3D CMD_NUM(cmd); ttl =3D CMD_TTL(cmd); - num_pages =3D (num + 1) * (1 << (scale)); + num_pages =3D (num + 1) * BIT_ULL(scale); } =20 if (type =3D=3D SMMU_CMD_TLBI_NH_VA) { --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337914; cv=none; d=zohomail.com; s=zohoarc; b=ZJ6rYyxOohbgAjU8g8gs9ETQePNTZtOdM83Hi6EkMyURQfnUeuutLIuwgo9L6NsdRnPQsyvmW9CuYFJUEnSnM6pJ3k7fKpp2p9qExw6w2GPn8IXtk0JWZpF3xvEfjssw9LufB1gSrstNVM5sV5ume2+pA/Qxr6AcLkK2l58wW/k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337914; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rwxRQ2VGsaY/8EHSjzxMZ0dJGo8ROLSJrdHaZKDxSh4=; b=m+Wm22AaFeuKw+4KqyvwdTM6sfdMSHp1C4jCtoK2OqQdyPH0M/5Py3n//hyoYRuWP5M9mweta053agg44psclSBGVyf7hhGoAN4hW01RQ7Ps2HSuX0uqcwBPN+YKADF53lhnZRPKMiiD/vZiy+NwquDbBa1u+8YB0iXxYD9DMF4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337914754308.5031252982616; Mon, 2 Nov 2020 09:25:14 -0800 (PST) Received: from localhost ([::1]:57374 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdZx-00031r-CL for importer@patchew.org; Mon, 02 Nov 2020 12:25:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54036) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLx-00014B-8v for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:45 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:35865) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLs-0006bw-VL for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:44 -0500 Received: by mail-wm1-x341.google.com with SMTP id e2so10222737wme.1 for ; Mon, 02 Nov 2020 09:10:40 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rwxRQ2VGsaY/8EHSjzxMZ0dJGo8ROLSJrdHaZKDxSh4=; b=I7+qtFh4PXoSMdPKlefZ0gBI0QuK0+Yli7RHv1nbiPdtmvaF63ewIEDLE5DZ+wZb5p 7rzTSkbZ3QzHhb64ECIyDaN2wEOKMzs4vw5g8CAY8ifqvtkuwPlfvVj3Htzbx9dPgCDo Ckg8T0zpAe+8v09uEmE7MNXaK7FE2enihFxAyQ8/dVA6vNwIBQpZINxSjIQbZQxK6RUt EONRn/9RM/wSt/SeJdXlu6+gf+cSXR8rEiZu5t8JlL6wKhLvkKI5iZbjSH9rbABcwxOK 2LuddmtKUPinVIKT6aq9V0VdWw7tGNsUapZCSUnWhtK5qMG9BCIqQrOg7f8zKz9aJYAf XDWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rwxRQ2VGsaY/8EHSjzxMZ0dJGo8ROLSJrdHaZKDxSh4=; b=oW/mwskpuD1wPKEMGJNALVfyrMaP3SNX2pdVid9DqQ0L5vF1447v6sMOtjxM+NTPDa +0b0mf8L/ZRk4mwR8ehiWd/tCiCdEkR9LRM7cQL40MU39ucTIuxhsrpJ1tG+fvMmBerR WRg+zFSYbntPVmCy7Ye0A+n/srmLkpvyePPQrLWdDYXeCQ7pM5/qHb8fTRUTD8BBAUV9 xL7/Bb4JAlfQiDGLs+YgbG2jnVudVMYHJV5CJkcCcDwS/1NER8q4412EA1cLEj/IYaGd eJJp2z7pNaHhqNPThmHOlpaPGZYqRVGXA9piQsIqhj8J6zw82CZuzwu2K82vDfl+am9F 5Jiw== X-Gm-Message-State: AOAM532QwZCWkzLyAZmzQPEBH0YKAokroBp812cwnb/MnQqwNWCcI1Ow 3/UB4GS6AaB286A2Ms8LMhSRt6aaFZuBBA== X-Google-Smtp-Source: ABdhPJxpGYP9dRK2J8pZp7wI3fv+wcctz0bh2qCH9OJt6UgU/UjGT8wVN/FJknbHr+lKf5Bj8qB6AQ== X-Received: by 2002:a1c:ed0b:: with SMTP id l11mr18316543wmh.46.1604337038708; Mon, 02 Nov 2020 09:10:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/26] hw/arm/boot: fix SVE for EL3 direct kernel boot Date: Mon, 2 Nov 2020 17:09:57 +0000 Message-Id: <20201102171005.30690-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: R=C3=A9mi Denis-Courmont When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so that SVE will not trap to EL3. Signed-off-by: R=C3=A9mi Denis-Courmont Reviewed-by: Richard Henderson Message-id: 20201030151541.11976-1-remi@remlab.net Signed-off-by: Peter Maydell --- hw/arm/boot.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 3e9816af803..cf97600a915 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -742,6 +742,9 @@ static void do_cpu_reset(void *opaque) if (cpu_isar_feature(aa64_mte, cpu)) { env->cp15.scr_el3 |=3D SCR_ATA; } + if (cpu_isar_feature(aa64_sve, cpu)) { + env->cp15.cptr_el[3] |=3D CPTR_EZ; + } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337748; cv=none; d=zohomail.com; s=zohoarc; b=cMWjvD5u//CeE7UYkNNypL7+1hwyDqeykjjOp5i3xaD0epbYHIAH7ei9S/sbvrHtTfWGm9gWSEb2Ffo41IE+8dklOxWcZ1ucTmmJ0FW9pgUQNbJ5faZit2XyiUbTyKe9/R6/7GsPvhQK5VGL3WgX4/0XnK75LECRTMY9l090Wqw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337748; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PHlIRH7863n7trY1b/lRLkeSRiEQjbh9eyt3Xp710GY=; b=X2e2qyNEUXbZVMm6AEEOYusVrN7aSHJcthg2B05anyTFyE5y7QfDtX2lQ17vXg74ne/EK3ZOWuBVSeANUiZl7xN0AyJchZHw5ztYuqPVTR36VsqYpwItg/ZwGMXD1w0EQ91G3ma122oKLmzSmgOoRbnYqMEtfKQaYzB6jW7lDIQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337748825986.7586513624286; Mon, 2 Nov 2020 09:22:28 -0800 (PST) Received: from localhost ([::1]:50120 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdXF-0008QI-Lb for importer@patchew.org; Mon, 02 Nov 2020 12:22:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLv-00012q-Vh for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:44 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:37543) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLt-0006c9-GK for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:43 -0500 Received: by mail-wm1-x342.google.com with SMTP id c16so10222648wmd.2 for ; Mon, 02 Nov 2020 09:10:41 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PHlIRH7863n7trY1b/lRLkeSRiEQjbh9eyt3Xp710GY=; b=svWAz9bWchfwgECY344PtiYeWsCE/Hm77JXZ1Rc3jOwwqcnLTVJ8WYU8Hn5PqDcZJN X3KGf+/U9dy1++42xBMZ+Sf7K4exyyBLgMA4XtHkncH+i8hkPWDclLOFT2ynv7sVc892 Z27lpyQcenwAMkhpLIL51A3w4vUG5rlh/SjJkO6HgTZtha6TmLUyFZ8lJCJPxlgTZD4W gZm/msABK5JeHZhotAunFnHCCdDBHSGN9K7oGxkY8klBzaueGEI6oEUUjRouqx9HRfai JSih+eyBeEqe9KTOZ+jZQBIIotmvJU0IlhyjnpPezXOhmKclbYWIj9k8IBk2TgnRXIhL QRpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PHlIRH7863n7trY1b/lRLkeSRiEQjbh9eyt3Xp710GY=; b=YYLNE3a2diEiAKU6+z+8EbOAQem5Sfjbe0wJG1CieCn96/LslESaMoxUrhSinFKdnQ gkuTnJyd4FGK9TRVgwJ4iUu0Kq2wzvYb0Y4ESNwvIJINzfB4Bu/nfdR+K9utgya7DKrF cj3exqPpmScNA3fv/KKjA/cNKetwy7AvHz+QTfWd2+ZyBsW7AUW4CphGXXg13iHvjjsB qSK1KLAoBxXFYeV8s/ab0mUf1gEUNWkv6S6js9IehdtuqkRHJIukzoXcbNpXoXAByBeN ZDKodFuWuHzsOsbLUeRmsfizMBHGDMKzyCaChtgqLVyH8hn0emskP0k6ECRIPVnEbenZ kwRA== X-Gm-Message-State: AOAM530n+H9GFmgf03PgvlK4YghmLT8Lmx/7pmtCxtSwIcT280bVPz5j HR+nrHBUb6jzm+cjZ2HVH0UEBahrQH7aFQ== X-Google-Smtp-Source: ABdhPJyfaNC8iq2bC+Fzv/VeJDQNtGjqsh6Gjps53kazktb8pMB0nyjUXaBx0E+0735k9qG+w5ymvw== X-Received: by 2002:a1c:ac87:: with SMTP id v129mr18630069wme.119.1604337039975; Mon, 02 Nov 2020 09:10:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/26] hw/display/omap_lcdc: Fix potential NULL pointer dereference Date: Mon, 2 Nov 2020 17:09:58 +0000 Message-Id: <20201102171005.30690-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: AlexChen In omap_lcd_interrupts(), the pointer omap_lcd is dereferinced before being check if it is valid, which may lead to NULL pointer dereference. So move the assignment to surface after checking that the omap_lcd is valid and move surface_bits_per_pixel(surface) to after the surface assignment. Reported-by: Euler Robot Signed-off-by: AlexChen Message-id: 5F9CDB8A.9000001@huawei.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/display/omap_lcdc.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c index fa4a381db64..58e659c94ff 100644 --- a/hw/display/omap_lcdc.c +++ b/hw/display/omap_lcdc.c @@ -78,14 +78,18 @@ static void omap_lcd_interrupts(struct omap_lcd_panel_s= *s) static void omap_update_display(void *opaque) { struct omap_lcd_panel_s *omap_lcd =3D (struct omap_lcd_panel_s *) opaq= ue; - DisplaySurface *surface =3D qemu_console_surface(omap_lcd->con); + DisplaySurface *surface; draw_line_func draw_line; int size, height, first, last; int width, linesize, step, bpp, frame_offset; hwaddr frame_base; =20 - if (!omap_lcd || omap_lcd->plm =3D=3D 1 || !omap_lcd->enable || - !surface_bits_per_pixel(surface)) { + if (!omap_lcd || omap_lcd->plm =3D=3D 1 || !omap_lcd->enable) { + return; + } + + surface =3D qemu_console_surface(omap_lcd->con); + if (!surface_bits_per_pixel(surface)) { return; } =20 --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604338023; cv=none; d=zohomail.com; s=zohoarc; b=UELVG1aBF75R+glqj+Wr3tT+Mh9WSH8H8quE9t8agUVAfN5TpTYUytzIsWFqroegCGQNnTTe4Bj8BShE0Sk5s7Y18DFgyFK8zoj2EzMiv4DDTKnhZOH1xZmXAG/NWKkheMJikuLQrZI25uUkqEPDQlv8tsHOX7zT2FOpAEDWaCw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604338023; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ed/BTbi7euqfL1hXrKVEmFWNJJJT/JBXDy33Yta9R7U=; b=m4AXUI9ewsBkzo719wxkRg0KZ8HbszmPZlsSlzop+odwJ2YPC3D1aPrfmpjIP44rrkk8iiSUHr4D0fy9ABNrV+4tm6InJK61+vmf/4E7dmJuNu0jEFn+L0G1TammJHYg+CpGgl/FZYbAMHUHiN/GfoxBmO2KamctjRr12DZSsT8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604338023317763.3918119359195; Mon, 2 Nov 2020 09:27:03 -0800 (PST) Received: from localhost ([::1]:35502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdbi-0005kS-1W for importer@patchew.org; Mon, 02 Nov 2020 12:27:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54060) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLy-00016b-3D for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:46 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:56090) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLu-0006cN-Q3 for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:45 -0500 Received: by mail-wm1-x342.google.com with SMTP id c9so8605713wml.5 for ; Mon, 02 Nov 2020 09:10:42 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ed/BTbi7euqfL1hXrKVEmFWNJJJT/JBXDy33Yta9R7U=; b=TvTnE7PwnkqUuwn6H7RD13+NfZIpEdUkznHeUQeFVQXh39/CqsOxp2fhwC1SbNGTt1 azfUfYe49rHZeaYdg2cA9XA2MyeaRN2Hfjg0bAYky7o1zlwT7kzHtf+uMEYssZQAD/jB D9hKTmHO8sv8ZSCnBqaKsum4fmhxUrnP3X+/ul0mBa6OVykRnRcQ7oT1q5GJ3lT8vgUZ 1rF0mCfsWpVwVJ5f/bDrYsV90h48ru4alLEOqnQ1wOIa4lSBiOq5yPDMWLU6vs8NmcSq 8hH7xb8zBjV/gQfuV+hIHLkidyTFEmTlH1w8jWijCXw1TecuraLh9UeqzCb53fTm592D O0Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ed/BTbi7euqfL1hXrKVEmFWNJJJT/JBXDy33Yta9R7U=; b=DcrhwdIBwiLreKbf6Pg0Uo9piqDoDVTmo6GWkZ3cXPFug25JE2aqi89DnCbMTWJt1W SzDAIZlCCvSy0Ie4c9zN/PDstF0KOcCVIgke4NmCA9MUIX+Fd1fSL+3z0IMPgNQwE/bJ LxPAMapd0gunk2fSnwsNUbLpxj3Of6PcpECfIQMsv8rv9ayTl89B2T3ZjZUQlPAEjLM9 G0REoAQM3jqwNfpFoV8TvrhOHW7KEclORyT+3/dgvHRtTWZTldo8fu1gNlsRT4ZtI1Dc bsjmUlqz44u850AwioZEaUFO9WtXQa5stMsljLEmYCyIFO6oVQYL4vR11sInkDff6t7n S3Bw== X-Gm-Message-State: AOAM531wuBkxSr7OLmJ7Wmp+tsAlN12DBIQ6+tKHnGkVA8jb9sIdvzLM fmOqoEC+0L+m4bscGwmOIx1HHUmSY/ekKg== X-Google-Smtp-Source: ABdhPJxNAaM7Rer+oJ5v+BdkOK1sKxhQLHn/lQa9rsJmRbTvMzSg9xxRtCjS+PI2DzGhweo6IOeCkg== X-Received: by 2002:a1c:4d14:: with SMTP id o20mr18197607wmh.72.1604337041221; Mon, 02 Nov 2020 09:10:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/26] hw/display/exynos4210_fimd: Fix potential NULL pointer dereference Date: Mon, 2 Nov 2020 17:09:59 +0000 Message-Id: <20201102171005.30690-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: AlexChen In exynos4210_fimd_update(), the pointer s is dereferinced before being check if it is valid, which may lead to NULL pointer dereference. So move the assignment to global_width after checking that the s is valid. Reported-by: Euler Robot Signed-off-by: Alex Chen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 5F9F8D88.9030102@huawei.com Signed-off-by: Peter Maydell --- hw/display/exynos4210_fimd.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c index 4c16e1f5a00..34a960a9765 100644 --- a/hw/display/exynos4210_fimd.c +++ b/hw/display/exynos4210_fimd.c @@ -1275,12 +1275,14 @@ static void exynos4210_fimd_update(void *opaque) bool blend =3D false; uint8_t *host_fb_addr; bool is_dirty =3D false; - const int global_width =3D (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) += 1; + int global_width; =20 if (!s || !s->console || !s->enabled || surface_bits_per_pixel(qemu_console_surface(s->console)) =3D=3D 0)= { return; } + + global_width =3D (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1; exynos4210_update_resolution(s); surface =3D qemu_console_surface(s->console); =20 --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604337929; cv=none; d=zohomail.com; s=zohoarc; b=YNwZ/Xbe/4mRK5W67if9CZ/dASS4uIYo4wgLTkw0wu7ZoOEHppAM0sQ889lYULfaKMoJiPtZe18WZtimNlSd3fOOw5LEVk5eTdVERoBV2+DIS95988ywMV0fT/Z6T4R9UUus+9TYvRcy+q8fX8BO9llVgz6Fz1rPZfId6OGXbPs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604337929; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jMjtfOiFG10GNhNUO0WFVBSDgvdA1bWEPrli5zIV9Do=; b=Vv4GqbWitd+TM1/R/BKZVHlAh32B+ZbB0/KUeIhUsasa3gd9ys4h40SX9Yun135zQIim/NtPDn3AnkX1vu8yFfI68MtYJBxqWHrMVUiHyvGwRZutKwMn55wrtDQ2KITpdaw5N39Hv5I1REoitdenBbBcPKLzXE0cU7QOzofkrdo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604337929879688.9434982526284; Mon, 2 Nov 2020 09:25:29 -0800 (PST) Received: from localhost ([::1]:58232 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdaC-0003Ov-Lf for importer@patchew.org; Mon, 02 Nov 2020 12:25:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54078) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdLy-00018B-P1 for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:46 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:40836) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLw-0006cf-N2 for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:46 -0500 Received: by mail-wm1-x32a.google.com with SMTP id k18so10219272wmj.5 for ; Mon, 02 Nov 2020 09:10:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jMjtfOiFG10GNhNUO0WFVBSDgvdA1bWEPrli5zIV9Do=; b=E57Tchret6x8g43AVWfwJNw6B8wgtPFmoT827ztHr+ZExQGGpFq4rDRoCwGzBqtvl8 mig708t098yaB9tJxgDgRBfZjfsj5TxZVfAf787KZpP15xGt7B5MJUXKOqi9n2XxXVWd /Ihj1uYjWkHxek/Mr4UnQaNRJvo17lCDN5bfm/ECKTKvqqX7a5GG6ZyQqr2WmlgC/ga8 aMbShkIx9XwtKXD9nblZYhGGqqJiHeZP8qFQq4LKXWv5UzTi1zIPNVkSP4jtPiKFiLIr KMkE/nr4UCIRhcVfJkVYT44je0hEdiswT+L2axzT7qu1l+X4/9MVS2AtwH2tD429EJbG p3Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jMjtfOiFG10GNhNUO0WFVBSDgvdA1bWEPrli5zIV9Do=; b=m1eXC42jZm7C8DP4WxfDIq+EojePT73NQYgrrloYd+Z/uH+J3jwjDl7i1NzIsUz5hT P2vXV4ul/hV3SVxPAHRFv4Qsy3Nt6SqO+QNcgd09DeDX2t7xV7OK/12xQAZKrSFHCeFg R9QdiHXh6S6kH89WHBKPiqlCRVnhhd+7J0S0ACNhhMLdUi68gid0r78AtevN49RFfdbZ LKS8HQs8yIj8LQYFVKpkiSh8rcuYis8Uuj83pbV9w2WLiD5AHDBF3p344AOQ8QmTw5Ma 8oT3+UBpUmjwim7tdvOHc/MJ1cglN7OqnywLyu89qy6Wa18Nv+pe9so+j29qJQ5JTTAo 4uQQ== X-Gm-Message-State: AOAM531P6kSNgW2XFcfMqhxTHo+ES9TQTbdnkwjmt572sDW0hROgJXYo 5XdP4W70OAacRXp+nri36oFQ3Mr9rVvT0Q== X-Google-Smtp-Source: ABdhPJwJ8K8QXAsBK3OA2S61bd+4Pu71MnXooat+Wjn8JRecktN1Sy/jQoiMhsCGteqZzx5fa1F/xA== X-Received: by 2002:a1c:f311:: with SMTP id q17mr18234987wmq.28.1604337042332; Mon, 02 Nov 2020 09:10:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/26] target/arm: Get correct MMU index for other-security-state Date: Mon, 2 Nov 2020 17:10:00 +0000 Message-Id: <20201102171005.30690-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In arm_v7m_mmu_idx_for_secstate() we get the 'priv' level to pass to armv7m_mmu_idx_for_secstate_and_priv() by calling arm_current_el(). This is incorrect when the security state being queried is not the current one, because arm_current_el() uses the current security state to determine which of the banked CONTROL.nPRIV bits to look at. The effect was that if (for instance) Secure state was in privileged mode but Non-Secure was not then we would return the wrong MMU index. The only places where we are using this function in a way that could trigger this bug are for the stack loads during a v8M function-return and for the instruction fetch of a v8M SG insn. Fix the bug by expanding out the M-profile version of the arm_current_el() logic inline so it can use the passed in secstate rather than env->v7m.secure. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201022164408.13214-1-peter.maydell@linaro.org --- target/arm/m_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 036454234c7..aad01ea0127 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2719,7 +2719,8 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUAR= MState *env, /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) { - bool priv =3D arm_current_el(env) !=3D 0; + bool priv =3D arm_v7m_is_handler_mode(env) || + !(env->v7m.control[secstate] & 1); =20 return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv); } --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604338185; cv=none; d=zohomail.com; s=zohoarc; b=IGIPokOUI43IFSXa3iErmMQgebmrH91e2AEsVnbGTdGKbZ9tE9+MayYXq2EGyiYrTHJ9SSOuACA4/ktNrdAAEamSSyvBUpTqV0CoO/YxhvH7GHM/ju2Gkwdn4f4+ZraPiHsdl4Mtr2chgr5pczrgWT+ezsQdjrJ5305oRMjp5wY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604338185; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1UkAowOgugs4Mdi7jPockoQV3dWs7h5MywTlHoiRgXg=; b=OOQpK2BxnqALXVWBS/pMgmjWo+4ELvCdgfPreOY+k1ek1N6Od9sCwvixL+ncA1h9AUqahibDdOC+WLKo7nalH/6t1BF5PlOpVXu9X2nzGrd1zxIxbHENIkpVO/6nbN7z+NqdXo/b+LB16HoraVe7dJZphO/BGqmiLSNkFQiHvIU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604338185367684.6355686802654; Mon, 2 Nov 2020 09:29:45 -0800 (PST) Received: from localhost ([::1]:42306 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdeK-0000EB-8t for importer@patchew.org; Mon, 02 Nov 2020 12:29:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdM2-0001GM-3I for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:50 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:38587) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLx-0006ct-6T for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:49 -0500 Received: by mail-wm1-x333.google.com with SMTP id h62so5403921wme.3 for ; Mon, 02 Nov 2020 09:10:44 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1UkAowOgugs4Mdi7jPockoQV3dWs7h5MywTlHoiRgXg=; b=Xb9LnuaQmW2ancLD3qM8/p0CHVO9XJLa+/V7oZq8zYIzIxWUwK/zHXLl2A3ZM88cMM dj8QLGPlvMJppaV7BnkpuAJhBZ2ogHxfMMUskvIXub/MHQ0E5nZEGobrg3RvVbRpXKIv bs0y9lEXa/XOFNZYFHpSCqQkO4mxlYvSfUb/L+TvxggSo5SRcqExqWRjp8f0Jd7e45s3 D7Ldz98C+4TFIuv3L2voCX3uQR5S0nONwynPw1p2vHR48tbyLYSBwP6fNFEYU8476RuQ qs7+05AzkPKPDOhmQWMf99Fzp5gdFioFmTXJbfU7ln0Mm+xVvUlqC/Aao9ycaaIivBPi j0/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1UkAowOgugs4Mdi7jPockoQV3dWs7h5MywTlHoiRgXg=; b=dZ7VbA/tDJXclfX3ZGwZoV4TakOR9KM7+rN+6iNPYVrCL5ZlqS6A9qy4wrkE1bMofX VvQ1kqSJhidGCCEjbB4SUek5ox7nBKuu3xiuOG7JhmZ41/zB3NKaquJ7lWeNCeCJNiGS 55jP6AaXUXTWnoi+bvztnMhaCd2W1Q/PLxmoUaeSwTigCchCSxS1dwv6qCHZo4BFndpi W2i7FilLMY60WLZZxXnImTRpvCErku8JQ2Ya8+uhSdDxnzlKdT9SHp9VWk2nLubYdpxn UPu8vfX8Dw+j0f3HDIa/wJg90WLVFNqpxkNVIX31M7JF5yRJOYmbmyy8pjbP9+qYhnZz YzvA== X-Gm-Message-State: AOAM5305QNRAvjt5W6NXHQbLkGECL9rnH9ci8tDTa2LvLQpYpVxAD2/J t77an1wij5R5tEspqnapi6NEj8cy76au+w== X-Google-Smtp-Source: ABdhPJy7K07qMXKJdoeO6hcdG6Z6II6mlHIvsfbhzqykcid0r9mZDCYNtu2v2ZDCP9kFZXLR688v9g== X-Received: by 2002:a7b:c7c3:: with SMTP id z3mr18417123wmk.43.1604337043584; Mon, 02 Nov 2020 09:10:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/26] configure: Test that gio libs from pkg-config work Date: Mon, 2 Nov 2020 17:10:01 +0000 Message-Id: <20201102171005.30690-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) On some hosts (eg Ubuntu Bionic) pkg-config returns a set of libraries for gio-2.0 which don't actually work when compiling statically. (Specifically, the returned library string includes -lmount, but not -lblkid which -lmount depends upon, so linking fails due to missing symbols.) Check that the libraries work, and don't enable gio if they don't, in the same way we do for gnutls. Signed-off-by: Peter Maydell Reviewed-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200928160402.7961-1-peter.maydell@linaro.org --- configure | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/configure b/configure index 6df4306c884..2c3c69f1188 100755 --- a/configure +++ b/configure @@ -3489,13 +3489,21 @@ if test "$static" =3D yes && test "$mingw32" =3D ye= s; then fi =20 if $pkg_config --atleast-version=3D$glib_req_ver gio-2.0; then - gio=3Dyes gio_cflags=3D$($pkg_config --cflags gio-2.0) gio_libs=3D$($pkg_config --libs gio-2.0) gdbus_codegen=3D$($pkg_config --variable=3Dgdbus_codegen gio-2.0) if [ ! -x "$gdbus_codegen" ]; then gdbus_codegen=3D fi + # Check that the libraries actually work -- Ubuntu 18.04 ships + # with pkg-config --static --libs data for gio-2.0 that is missing + # -lblkid and will give a link error. + write_c_skeleton + if compile_prog "" "gio_libs" ; then + gio=3Dyes + else + gio=3Dno + fi else gio=3Dno fi --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604338049; cv=none; d=zohomail.com; s=zohoarc; b=DsWfnCOgJZikT5TgVTayrmvDOottdp5Oz6i/z6gVtod5XO98fZUgv32HMi9N1m/ck7274vIZxIlKP1BOO+FtZ/3UJOIZYXzUTvkl2rOWhJ7Bam+RaO5STUe1N2Hof8rMcpzp/3Ux/6WoNF9dcRIEB9oTVYQfUM1GnKtHFcIVHK4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604338049; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dOaBvJdurD+84xPf+pPC2Y9lDQ6drzzzVrYottzGd7A=; b=c9t6HQ4p9rn1OIzivGBiBM1lox+DDmM75kRA3Wqg3TMSyEyZjH+weHb9PCP2EQzyruQgwhD3jZLCgZ9100fAI7BevR/+y66mBAb39N08KPSmnjic28HJ5sak/kyeI6d/aU3S5aUPIL0efrpED5K2Z8pOfe6Mhm7Cvx+3WfmaHP0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604338049571402.6492606284278; Mon, 2 Nov 2020 09:27:29 -0800 (PST) Received: from localhost ([::1]:36396 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdc8-00066b-BC for importer@patchew.org; Mon, 02 Nov 2020 12:27:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54110) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdM1-0001DY-5L for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:49 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:55352) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLy-0006d6-C0 for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:48 -0500 Received: by mail-wm1-x331.google.com with SMTP id c9so8605910wml.5 for ; Mon, 02 Nov 2020 09:10:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dOaBvJdurD+84xPf+pPC2Y9lDQ6drzzzVrYottzGd7A=; b=iAMqMRPCmtm0Sde3NfHc/VZ/YbcsryubxrXIsqXNe/J2Gdg4TByaanosW+JWGhQvgL dCbSiDz+2jRa8biQe82ThMRKDCFeuL41hxAP5R2qlF4X/YPd8N8MzOTYbzsLuIahQO3p HI8OXKa2t2bwiIzMTZ3rMxmZ1bekPhcYhfGDjXHh+Sb4GY9BM5aZpCQPLqz6yzHfzScM xZ1EUogrznibXRLnh+fTxTYQ7nXmm7z2f1dW2NY9nxmgEiVLtdHCLUaXrjYzWkeGfDBn 3kavUzZjnfuu8JmjJSXx7DV5G9O9hEDYWUssxQa71I4agrOdekVRK0kOp9ozRnd1R7xd 5Iqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dOaBvJdurD+84xPf+pPC2Y9lDQ6drzzzVrYottzGd7A=; b=YHEs95vY6IoEwRZgFfUzTiPjNqHDf7WxALpDPR7SUU1pV683a9339cMAFo8uWMfW9i YjafIPwngaX6kS1yzKALOt3Im9x1Xo0GSosNFpcSyx9XHxtQj1S0LtN/X91cGz5J0Wuj J/FEYzM9Sb85UcBQyXA0Rbj5NsyZQF0n2MO0xdyKYvfNK4IWPeZM/Ygs2jlBNQ6AYCel m4BqZfGcwF6q5zp/+SYMJMhiaJVrRsTbekqpjWAx30ep0YYM7EMfjERpVzHJU2mlEHdv h1C/89P3baGKmZa2lvj+ZYuDAfzhkr2MRDjqnyRGI9RLwgQbRb3crQanAP7EMqlII/a4 CQaA== X-Gm-Message-State: AOAM531+vSlv/ERDOGlIytT0GXmG7UEPCS4AU0oPL0UaHbXuVhiNi0Cz ToCE7efRWBBeIXch5zRu0unxzRoQnFYI7g== X-Google-Smtp-Source: ABdhPJyhaGxI8p+EbjeWfjowZ0vsU33vqeZKIhpMa/z/rPL6DycCQkfCa2OzTQjSxpwBIJzjvU4Etw== X-Received: by 2002:a7b:c201:: with SMTP id x1mr8240495wmi.42.1604337044754; Mon, 02 Nov 2020 09:10:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/26] hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work Date: Mon, 2 Nov 2020 17:10:02 +0000 Message-Id: <20201102171005.30690-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt into the GICv3CPUState struct's maintenance_irq field. This will only work if the board happens to have already wired up the CPU maintenance IRQ before the GIC was realized. Unfortunately this is not the case for the 'virt' board, and so the value that gets copied is NULL (since a qemu_irq is really a pointer to an IRQState struct under the hood). The effect is that the CPU interface code never actually raises the maintenance interrupt line. Instead, since the GICv3CPUState has a pointer to the CPUState, make the dereference at the point where we want to raise the interrupt, to avoid an implicit requirement on board code to wire things up in a particular order. Reported-by: Jose Martins Signed-off-by: Peter Maydell Message-id: 20201009153904.28529-1-peter.maydell@linaro.org Reviewed-by: Luc Michel --- include/hw/intc/arm_gicv3_common.h | 1 - hw/intc/arm_gicv3_cpuif.c | 5 ++--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 0331b0ffdb8..91491a2f664 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -153,7 +153,6 @@ struct GICv3CPUState { qemu_irq parent_fiq; qemu_irq parent_virq; qemu_irq parent_vfiq; - qemu_irq maintenance_irq; =20 /* Redistributor */ uint32_t level; /* Current IRQ level */ diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 08e000e33c6..43ef1d7a840 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -399,6 +399,7 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) int irqlevel =3D 0; int fiqlevel =3D 0; int maintlevel =3D 0; + ARMCPU *cpu =3D ARM_CPU(cs->cpu); =20 idx =3D hppvi_index(cs); trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx); @@ -424,7 +425,7 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) =20 qemu_set_irq(cs->parent_vfiq, fiqlevel); qemu_set_irq(cs->parent_virq, irqlevel); - qemu_set_irq(cs->maintenance_irq, maintlevel); + qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel); } =20 static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2624,8 +2625,6 @@ void gicv3_init_cpuif(GICv3State *s) && cpu->gic_num_lrs) { int j; =20 - cs->maintenance_irq =3D cpu->gicv3_maintenance_interrupt; - cs->num_list_regs =3D cpu->gic_num_lrs; cs->vpribits =3D cpu->gic_vpribits; cs->vprebits =3D cpu->gic_vprebits; --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604338295; cv=none; d=zohomail.com; s=zohoarc; b=abOtVn+Ty0EMq3XCtmpUpF4bihXiDz3/3o39jdb8g5dbXswIDgaaCw6+eI8SHLYKQm+k/ZoEQjZgtE5Zq0MET+4gA8h9oucNs2NDbKX3RxdHtCbP7+lVSXKw7zJsdhV1Y9do1f0t3YFOFYXPvyg0Us5HxxDJmj2VS77Q/+XuiXE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604338295; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KnPXJ6NqptesuWN0QOJA3/7JLRDcQ5MPX9LbhM6n5G4=; b=f1HnXHHtk5rFU487Hzd+rQiEt8Ufhmm0x/8Geqe5yKgW1GMlaEiKZk8AR1plaLihHTb9wfVjLYn2T99hsOr/toxj0+jlTCGIjk7kgIOIiO8T8wxZL2yDkf04JidPrYmYjNUPji18nGZDS7DWDgPkcvoZ4yfoA/ChUDY8z5QrJUQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604338295878881.9668730242337; Mon, 2 Nov 2020 09:31:35 -0800 (PST) Received: from localhost ([::1]:47028 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdg5-0002LW-Os for importer@patchew.org; Mon, 02 Nov 2020 12:31:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdM2-0001HH-Fo for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:50 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:39183) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdLz-0006dN-H1 for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:50 -0500 Received: by mail-wm1-x32a.google.com with SMTP id 205so2472310wma.4 for ; Mon, 02 Nov 2020 09:10:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=KnPXJ6NqptesuWN0QOJA3/7JLRDcQ5MPX9LbhM6n5G4=; b=JrLqcbFGMBk3yfGooxAODLMRIsLrQ2y2MW+X8r/4W5pIPI6dGQhVdVy/hFEwjKEuho tiSLZnw/5CFJAAjBgaPRiTChn/Bt6htSknaDCnww+0mo81aj2MMfgl5sIcZ9YgCj8+jw AQCB1CwaQP6k+e0a6bQD+HZ7VdlVtB0HshLH+x5GLI+BA8HGgYglw4veFYR7qxX5m2l9 I88gkIxrPRCuchtRrXpKtQ7DyS3BLhsmBle6/mDPesa6v2rONlwTbXwE88yR58ZZRefQ dr8xXBhur/9f6bwVZhZ8b+19m3YyR7sOyH1UBjeQCeNW+Ch5gUvjl9bVYLKi69yrwQMJ viRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KnPXJ6NqptesuWN0QOJA3/7JLRDcQ5MPX9LbhM6n5G4=; b=MU9d0rxkAE+G/kKGzpzjfAS8HKe4R1UeZH+3XpZIwK23IlOAz7UQwYI1GuGDiEW1ts W74ZTlG0P75+u/pe9QxkJjHUa/mvxuP+Nw2fQqArwjEa4SlKQEyUp1UPv6EuZDUJaMuN UJRadTBnnx8OtYOZw3HtmP8uqDEi57N085kiyBtbeFxG81GVY/D/cHo2+s8nVWSTroaB 3FP2UI7XsD3s1ZpameiK1YA52M+tKlgS/UlxFqKKeCkQpTm1Xvyw6UJhcGXX5oTcR+m4 qevXicJtnqZ4M4LpMFv3IWagkw6H/UZAW+0E++NK6/zeUrKAxMm3Avkhkombm+pYa8Xa LEyA== X-Gm-Message-State: AOAM532Mh4j11B75DJsuLdv/FFrene4+miCxAvOpHsjlv/McyU1znqqc JlSQugiFPIj/qsF22pNfB1nf1QcmNPJnmg== X-Google-Smtp-Source: ABdhPJzUlHkgxwrN3ysatg0fgf/GBQRFk8S0qZA+HCh9FPJjQVhw7OHuzn5dZTlhINSd7G0w4UdoGA== X-Received: by 2002:a1c:5946:: with SMTP id n67mr3550105wmb.162.1604337045863; Mon, 02 Nov 2020 09:10:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/26] scripts/kerneldoc: For Sphinx 3 use c:macro for macros with arguments Date: Mon, 2 Nov 2020 17:10:03 +0000 Message-Id: <20201102171005.30690-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The kerneldoc script currently emits Sphinx markup for a macro with arguments that uses the c:function directive. This is correct for Sphinx versions earlier than Sphinx 3, where c:macro doesn't allow documentation of macros with arguments and c:function is not picky about the syntax of what it is passed. However, in Sphinx 3 the c:macro directive was enhanced to support macros with arguments, and c:function was made more picky about what syntax it accepted. When kerneldoc is told that it needs to produce output for Sphinx 3 or later, make it emit c:function only for functions and c:macro for macros with arguments. We assume that anything with a return type is a function and anything without is a macro. This fixes the Sphinx error: /home/petmay01/linaro/qemu-from-laptop/qemu/docs/../include/qom/object.h:15= 5:Error in declarator If declarator-id with parameters (e.g., 'void f(int arg)'): Invalid C declaration: Expected identifier in nested name. [error at 25] DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME) -------------------------^ If parenthesis in noptr-declarator (e.g., 'void (*f(int arg))(double)'): Error in declarator or parameters Invalid C declaration: Expecting "(" in parameters. [error at 39] DECLARE_INSTANCE_CHECKER ( InstanceType, OBJ_NAME, TYPENAME) ---------------------------------------^ Signed-off-by: Peter Maydell Reviewed-by: Daniel P. Berrang=C3=A9 Tested-by: Stefan Hajnoczi Message-id: 20201030174700.7204-2-peter.maydell@linaro.org --- scripts/kernel-doc | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/scripts/kernel-doc b/scripts/kernel-doc index 0ff62bb6a2d..4fbaaa05e38 100755 --- a/scripts/kernel-doc +++ b/scripts/kernel-doc @@ -839,7 +839,23 @@ sub output_function_rst(%) { output_highlight_rst($args{'purpose'}); $start =3D "\n\n**Syntax**\n\n ``"; } else { - print ".. c:function:: "; + if ((split(/\./, $sphinx_version))[0] >=3D 3) { + # Sphinx 3 and later distinguish macros and functions and + # complain if you use c:function with something that's not + # syntactically valid as a function declaration. + # We assume that anything with a return type is a function + # and anything without is a macro. + if ($args{'functiontype'} ne "") { + print ".. c:function:: "; + } else { + print ".. c:macro:: "; + } + } else { + # Older Sphinx don't support documenting macros that take + # arguments with c:macro, and don't complain about the use + # of c:function for this. + print ".. c:function:: "; + } } if ($args{'functiontype'} ne "") { $start .=3D $args{'functiontype'} . " " . $args{'function'} . " ("; --=20 2.20.1 From nobody Fri May 17 11:58:48 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1604338049; cv=none; d=zohomail.com; s=zohoarc; b=T39eEEC8OPspG7pIG3HiVwS7KsK8vU4ETCl7Npz/bFw4JQcQjSa/0bCqEOt13qHifiBum30Uoy0G471gzKRoKPxCcK1GDN60CEMboC2pKAG2KpEfNZLDqcj37mHlC/MZjVatENtNmCyGFjk7D8toa4UpersirB6q9mBhQj9SmfU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604338049; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UP1n0K2qtWKcroM5xmLdq4+koLBx0NwxnaUUM2A/CGU=; b=lisJjXE6PMVMpaN4bSPH8QiEar5BxTo+W/Mp21eD/zRABpgdv8dj9FXoVFlTqrJaYfZXu/mpAG2DeVUQZIXpwg4Nq/gLD2ACp/JubqiQfdHvWe+DbY/OwjslMxfaLpQyF0MGTcmUzdDH00JQ+ELdIjwoB1wXfTVVmA7ZVmLm2l0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604338049175935.9223861424026; Mon, 2 Nov 2020 09:27:29 -0800 (PST) Received: from localhost ([::1]:36310 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZdc7-00064Y-Vp for importer@patchew.org; Mon, 02 Nov 2020 12:27:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:54152) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZdM5-0001PL-Hi for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:53 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:50799) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kZdM3-0006eX-QW for qemu-devel@nongnu.org; Mon, 02 Nov 2020 12:10:53 -0500 Received: by mail-wm1-x331.google.com with SMTP id 13so10160900wmf.0 for ; Mon, 02 Nov 2020 09:10:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c18sm22396540wrt.10.2020.11.02.09.10.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Nov 2020 09:10:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=UP1n0K2qtWKcroM5xmLdq4+koLBx0NwxnaUUM2A/CGU=; b=Cirx/Fu7gnDaFZx1nWzqOvrdDwioh2/I5VuLofjwmlxUTV3bUfTl7OZpq/ShmO5mmq ZrVyQ6qoBcRDhmKRbvmVXMrr7IP04VKrzcTq660QMTmKCOtocHy/Nfujw38neeYnsOF5 hUr5zstHTRgOLL3w+TwP2FjAnVCnkHPGwaDFIZpf15JBEo90l1Mc2UE4eS9sMA5esWlR G5tlRCh1NqRflBGVsnaUIcbUK2KeI65fdLGi8dl9lG6Tp5+/OqeYE7UcJhhl/ANC6pxH WyOZ2bHIrFciIcIzxvCePDGTwHm5Ck6ek6oCg98MEPEgmiesaZT3c7AN2O082zVQWGCR q4wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UP1n0K2qtWKcroM5xmLdq4+koLBx0NwxnaUUM2A/CGU=; b=UB9uRm81NPthFzaU20nK836WXfFzcMv8i/tOv1RB5+8+siK5uv7+15EG4Roob4a3vj 28XYLbfcvZoV8H5xF21fVnPpWyNB9vq+InDWShUrl2M9r7PLNT0+cMPxzQmHQq4pFx3L siDr7uaXZdKX3KyUvpVIFd/Esvsn90FrtmZuHMkq1UAEvkAQxNzxa7wGdFRIc1nkG+8u fIRZgd4s9kR4rHKD2weQL+1dPzDP81me7JOShF/8x5Lzy7L/ZjYydX4ddPBMAU24/+Mn W5mlnso+gJl0HtpoU7uZtbkG6etWkuYB792h/rLJfEjdPUgMWSoEl17oQb2aWaMKF0GS xorA== X-Gm-Message-State: AOAM532ydsa2rwG7YhGTmP4sjU5XNMb0QNICerh6NgYVFekf/YF60YC/ ogBbzIfE8Hhu6VLH0IMh7T1zqcbfYXgMlA== X-Google-Smtp-Source: ABdhPJwm9xC3EAt0OHfEC1G8Xm0RCgBhEpyucX8BBn6b8hhwkI9VNO5UYzc5bvaN9CIirQIC5Okfrw== X-Received: by 2002:a1c:ac87:: with SMTP id v129mr18630593wme.119.1604337047232; Mon, 02 Nov 2020 09:10:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/26] qemu-option-trace.rst.inc: Don't use option:: markup Date: Mon, 2 Nov 2020 17:10:04 +0000 Message-Id: <20201102171005.30690-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201102171005.30690-1-peter.maydell@linaro.org> References: <20201102171005.30690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Sphinx 3.2 is pickier than earlier versions about the option:: markup, and complains about our usage in qemu-option-trace.rst: ../../docs/qemu-option-trace.rst.inc:4:Malformed option description '[enable=3D]PATTERN', should look like "opt", "-opt args", "--opt args", "/opt args" or "+opt args" In this file, we're really trying to document the different parts of the top-level --trace option, which qemu-nbd.rst and qemu-img.rst have already introduced with an option:: markup. So it's not right to use option:: here anyway. Switch to a different markup (definition lists) which gives about the same formatted output. (Unlike option::, this markup doesn't produce index entries; but at the moment we don't do anything much with indexes anyway, and in any case I think it doesn't make much sense to have individual index entries for the sub-parts of the --trace option.) Signed-off-by: Peter Maydell Reviewed-by: Daniel P. Berrang=C3=A9 Tested-by: Stefan Hajnoczi Message-id: 20201030174700.7204-3-peter.maydell@linaro.org --- docs/qemu-option-trace.rst.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/qemu-option-trace.rst.inc b/docs/qemu-option-trace.rst.inc index 7e09773a9c5..d7acbe67f73 100644 --- a/docs/qemu-option-trace.rst.inc +++ b/docs/qemu-option-trace.rst.inc @@ -1,7 +1,7 @@ =20 Specify tracing options. =20 -.. option:: [enable=3D]PATTERN +``[enable=3D]PATTERN`` =20 Immediately enable events matching *PATTERN* (either event name or a globbing pattern). This option is only @@ -11,7 +11,7 @@ Specify tracing options. =20 Use :option:`-trace help` to print a list of names of trace points. =20 -.. option:: events=3DFILE +``events=3DFILE`` =20 Immediately enable events listed in *FILE*. The file must contain one event name (as listed in the ``trace-events-al= l`` @@ -19,7 +19,7 @@ Specify tracing options. available if QEMU has been compiled with the ``simple``, ``log`` or ``ftrace`` tracing backend. =20 -.. option:: file=3DFILE +``file=3DFILE`` =20 Log output traces to *FILE*. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The randomness tests in the NPCM7xx RNG test fail intermittently but fairly frequently. On my machine running the test in a loop: while QTEST_QEMU_BINARY=3D./qemu-system-aarch64 ./tests/qtest/npcm7xx_rng-= test; do true; done will fail in less than a minute with an error like: ERROR:../../tests/qtest/npcm7xx_rng-test.c:256:test_first_byte_runs: assertion failed (calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE) > 0.01): = (0.00286205989 > 0.01) (Failures have been observed on all 4 of the randomness tests, not just first_byte_runs.) It's not clear why these tests are failing like this, but intermittent failures make CI and merge testing awkward, so disable running them unless a developer specifically sets QEMU_TEST_FLAKY_RNG_TESTS when running the test suite, until we work out the cause. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20201102152454.8287-1-peter.maydell@linaro.org Reviewed-by: Havard Skinnemoen --- tests/qtest/npcm7xx_rng-test.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c index da6e639bf6f..e7cde85fbbc 100644 --- a/tests/qtest/npcm7xx_rng-test.c +++ b/tests/qtest/npcm7xx_rng-test.c @@ -265,10 +265,16 @@ int main(int argc, char **argv) =20 qtest_add_func("npcm7xx_rng/enable_disable", test_enable_disable); qtest_add_func("npcm7xx_rng/rosel", test_rosel); - qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_monob= it); - qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs); - qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_monob= it); - qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs); + /* + * These tests fail intermittently; only run them on explicit + * request until we figure out why. + */ + if (getenv("QEMU_TEST_FLAKY_RNG_TESTS")) { + qtest_add_func("npcm7xx_rng/continuous/monobit", test_continuous_m= onobit); + qtest_add_func("npcm7xx_rng/continuous/runs", test_continuous_runs= ); + qtest_add_func("npcm7xx_rng/first_byte/monobit", test_first_byte_m= onobit); + qtest_add_func("npcm7xx_rng/first_byte/runs", test_first_byte_runs= ); + } =20 qtest_start("-machine npcm750-evb"); ret =3D g_test_run(); --=20 2.20.1