From nobody Tue Feb 10 01:33:18 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1604296447; cv=none; d=zohomail.com; s=zohoarc; b=jh6BPZ3bjBBQpM3x2WJDlV4K921CJk6xhwO6h0O9/hfRXiTQ3B3XiQNfPMWMqd0FGSp9SOUMnC+57x2IgkICvBEErKzTiaVVA8nUaJjh2Pdf81Xz7H4aN2wRTmbmHfZIa9iWXVnbKBy/oTO/2s/3i/yeuood38wOEMi6lp14uPk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604296447; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q7SfHyc4hQvIwhLQeL2BCEOiUQCXt05ZwP+ljzZhDts=; b=YWkNz9C/6i5VT9BBIB+u5Lq0R/xORYFx2RUUqa6xAeZ0ZqaW6VqB5a/7651Zwpq8tqmuHFG560GSH2P791Wf0sEs0+12vZ8kgXgBykJpgiYtOYOpldOHrw4sMFxn2vCLLD6nPxnbzTMs6YptpkEEWNCNjnCBbv8aLsjoWq0LFbk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604296447805122.79533494006682; Sun, 1 Nov 2020 21:54:07 -0800 (PST) Received: from localhost ([::1]:36928 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kZSn8-0006wE-Nz for importer@patchew.org; Mon, 02 Nov 2020 00:54:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:51240) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZSdQ-0002We-3h; Mon, 02 Nov 2020 00:44:06 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2317) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kZSdM-0001NY-0z; Mon, 02 Nov 2020 00:44:03 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4CPhfy2TW4zkcJL; Mon, 2 Nov 2020 13:43:54 +0800 (CST) Received: from localhost.localdomain (10.175.124.27) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.487.0; Mon, 2 Nov 2020 13:43:48 +0800 From: Peng Liang To: , Subject: [RFC v3 09/10] target/arm: introduce CPU feature dependency mechanism Date: Mon, 2 Nov 2020 13:40:54 +0800 Message-ID: <20201102054055.686143-10-liangpeng10@huawei.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201102054055.686143-1-liangpeng10@huawei.com> References: <20201102054055.686143-1-liangpeng10@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.175.124.27] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=liangpeng10@huawei.com; helo=szxga04-in.huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/02 00:43:42 X-ACL-Warn: Detected OS = Linux 3.1-3.10 [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, zhang.zhanghailiang@huawei.com, mst@redhat.com, cohuck@redhat.com, xiexiangyou@huawei.com, Peng Liang , pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Some CPU features are dependent on other CPU features. For example, ID_AA64PFR0_EL1.FP field and ID_AA64PFR0_EL1.AdvSIMD must have the same value, which means FP and ADVSIMD are dependent on each other, FPHP and ADVSIMDHP are dependent on each other. This commit introduces a mechanism for CPU feature dependency in AArch64. We build a directed graph from the CPU feature dependency relationship, each edge from->to means the `to` CPU feature is dependent on the `from` CPU feature. And we will automatically enable/disable CPU feature according to the directed graph. For example, a and b CPU features are in relationship a->b, which means b is dependent on a. If b is enabled by user, then a is enabled automatically. And if a is disabled by user, then b is disabled automatically. Signed-off-by: zhanghailiang Signed-off-by: Peng Liang --- target/arm/cpu.c | 134 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8c84a16d92a8..9d5916719a24 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1266,6 +1266,107 @@ static struct CPUFeatureInfo cpu_features[] =3D { }, }; =20 +typedef struct CPUFeatureDep { + CPUFeatureInfo from, to; +} CPUFeatureDep; + +static const CPUFeatureDep feature_dependencies[] =3D { + { + .from =3D FIELD_INFO("fp", ID_AA64PFR0, FP, true, 0, 0xf, false), + .to =3D FIELD_INFO("asimd", ID_AA64PFR0, ADVSIMD, true, 0, 0xf, fa= lse), + }, + { + .from =3D FIELD_INFO("asimd", ID_AA64PFR0, ADVSIMD, true, 0, 0xf, = false), + .to =3D FIELD_INFO("fp", ID_AA64PFR0, FP, true, 0, 0xf, false), + }, + { + .from =3D { + .reg =3D ID_AA64PFR0, .length =3D R_ID_AA64PFR0_FP_LENGTH, + .shift =3D R_ID_AA64PFR0_FP_SHIFT, .sign =3D true, .min_value = =3D 1, + .ni_value =3D 0, .name =3D "fphp", .is_32bit =3D false, + }, + .to =3D { + .reg =3D ID_AA64PFR0, .length =3D R_ID_AA64PFR0_ADVSIMD_LENGTH, + .shift =3D R_ID_AA64PFR0_ADVSIMD_SHIFT, .sign =3D true, .min_v= alue =3D 1, + .ni_value =3D 0, .name =3D "asimdhp", .is_32bit =3D false, + }, + }, + { + .from =3D { + .reg =3D ID_AA64PFR0, .length =3D R_ID_AA64PFR0_ADVSIMD_LENGTH, + .shift =3D R_ID_AA64PFR0_ADVSIMD_SHIFT, .sign =3D true, .min_v= alue =3D 1, + .ni_value =3D 0, .name =3D "asimdhp", .is_32bit =3D false, + }, + .to =3D { + .reg =3D ID_AA64PFR0, .length =3D R_ID_AA64PFR0_FP_LENGTH, + .shift =3D R_ID_AA64PFR0_FP_SHIFT, .sign =3D true, .min_value = =3D 1, + .ni_value =3D 0, .name =3D "fphp", .is_32bit =3D false, + }, + }, + { + + .from =3D FIELD_INFO("aes", ID_AA64ISAR0, AES, false, 1, 0, false), + .to =3D { + .reg =3D ID_AA64ISAR0, .length =3D R_ID_AA64ISAR0_AES_LENGTH, + .shift =3D R_ID_AA64ISAR0_AES_SHIFT, .sign =3D false, .min_val= ue =3D 2, + .ni_value =3D 1, .name =3D "pmull", .is_32bit =3D false, + }, + }, + { + + .from =3D FIELD_INFO("sha2", ID_AA64ISAR0, SHA2, false, 1, 0, fals= e), + .to =3D { + .reg =3D ID_AA64ISAR0, .length =3D R_ID_AA64ISAR0_SHA2_LENGTH, + .shift =3D R_ID_AA64ISAR0_SHA2_SHIFT, .sign =3D false, .min_va= lue =3D 2, + .ni_value =3D 1, .name =3D "sha512", .is_32bit =3D false, + }, + }, + { + .from =3D FIELD_INFO("lrcpc", ID_AA64ISAR1, LRCPC, false, 1, 0, fa= lse), + .to =3D { + .reg =3D ID_AA64ISAR1, .length =3D R_ID_AA64ISAR1_LRCPC_LENGTH, + .shift =3D R_ID_AA64ISAR1_LRCPC_SHIFT, .sign =3D false, .min_v= alue =3D 2, + .ni_value =3D 1, .name =3D "ilrcpc", .is_32bit =3D false, + }, + }, + { + .from =3D FIELD_INFO("sm3", ID_AA64ISAR0, SM3, false, 1, 0, false), + .to =3D FIELD_INFO("sm4", ID_AA64ISAR0, SM4, false, 1, 0, false), + }, + { + .from =3D FIELD_INFO("sm4", ID_AA64ISAR0, SM4, false, 1, 0, false), + .to =3D FIELD_INFO("sm3", ID_AA64ISAR0, SM3, false, 1, 0, false), + }, + { + .from =3D FIELD_INFO("sha1", ID_AA64ISAR0, SHA1, false, 1, 0, fals= e), + .to =3D FIELD_INFO("sha2", ID_AA64ISAR0, SHA2, false, 1, 0, false), + }, + { + .from =3D FIELD_INFO("sha2", ID_AA64ISAR0, SHA2, false, 1, 0, fals= e), + .to =3D FIELD_INFO("sha1", ID_AA64ISAR0, SHA1, false, 1, 0, false), + }, + { + .from =3D FIELD_INFO("sha1", ID_AA64ISAR0, SHA1, false, 1, 0, fals= e), + .to =3D FIELD_INFO("sha3", ID_AA64ISAR0, SHA3, false, 1, 0, false), + }, + { + .from =3D FIELD_INFO("sha3", ID_AA64ISAR0, SHA3, false, 1, 0, fals= e), + .to =3D { + .reg =3D ID_AA64ISAR0, .length =3D R_ID_AA64ISAR0_SHA2_LENGTH, + .shift =3D R_ID_AA64ISAR0_SHA2_SHIFT, .sign =3D false, .min_va= lue =3D 2, + .ni_value =3D 1, .name =3D "sha512", .is_32bit =3D false, + }, + }, + { + .from =3D { + .reg =3D ID_AA64ISAR0, .length =3D R_ID_AA64ISAR0_SHA2_LENGTH, + .shift =3D R_ID_AA64ISAR0_SHA2_SHIFT, .sign =3D false, .min_va= lue =3D 2, + .ni_value =3D 1, .name =3D "sha512", .is_32bit =3D false, + }, + .to =3D FIELD_INFO("sha3", ID_AA64ISAR0, SHA3, false, 1, 0, false), + }, +}; + static void arm_cpu_get_feature_prop(Object *obj, Visitor *v, const char *= name, void *opaque, Error **errp) { @@ -1500,6 +1601,8 @@ static void arm_cpu_finalizefn(Object *obj) =20 void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) { + int i; + ARMISARegisters *isar =3D &cpu->isar; Error *local_err =3D NULL; =20 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { @@ -1517,6 +1620,37 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **= errp) return; } } + + if (!kvm_enabled() || !kvm_arm_cpu_feature_supported()) { + return; + } + + for (i =3D 0; i < ARRAY_SIZE(feature_dependencies); ++i) { + const CPUFeatureDep *d =3D &feature_dependencies[i]; + bool from_explicit =3D !!(isar->user_mask[d->from.reg] & + MAKE_64BIT_MASK(d->from.shift, d->from.len= gth)); + bool to_explicit =3D !!(isar->user_mask[d->to.reg] & + MAKE_64BIT_MASK(d->to.shift, d->to.length)); + bool from_enabled =3D object_property_get_bool(OBJECT(cpu), d->fro= m.name, + &error_abort); + bool to_enabled =3D object_property_get_bool(OBJECT(cpu), d->to.na= me, + &error_abort); + + if (!from_enabled && to_enabled) { + if (from_explicit && to_explicit) { + error_setg(errp, "The CPU feature '%s' dependes on CPU fea= ture " + "'%s' that is disabled explicitly", + d->to.name, d->from.name); + return; + } else if (from_explicit) { + isar->regs[d->to.reg] =3D deposit64(isar->regs[d->to.reg], + d->to.shift, d->to.length, d->to.ni_value); + } else if (to_explicit) { + isar->regs[d->from.reg] =3D deposit64(isar->regs[d->from.r= eg], + d->from.shift, d->from.length, d->from.min_value); + } + } + } } =20 static void arm_cpu_realizefn(DeviceState *dev, Error **errp) --=20 2.26.2