From nobody Mon Feb 9 23:03:59 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=wdc.com ARC-Seal: i=1; a=rsa-sha256; t=1604025486; cv=none; d=zohomail.com; s=zohoarc; b=Do1DqT72s4AJsjDIkHZ83SkNAFSLKTBxfghMsQjCGZtl3xywSCVdi3p/ZrSRH2xrBxSFlUWflq3zuW5iQYaimUWyKLuTb9syApPIn4DMM/6Zkb787tFe1TbJcmjpqhTjP2PxoOPLlZa4q8HqN+7rUqKKR+4n+GbooqRaX9lBDeU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1604025486; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hGNW24REj0Cc+s1FpRr1lJY3VhQEjOo3+32ZNd6RqtA=; b=JVSlwnVpgF/Fg66Sp05WPOWlGQQ4HnctTcc0OEzncjk1lmYRb64NbLDZ7m9Xm/PP37nHADY1ckfrZWalo/dk6Hr2Yt86cM9Aw9kPfBCZtlY3Ri/qsNf/07Km7pO2aZQMx1bgXo0mM3wuAmmAPer/3jE+94/ggFi4Co20t/BRz6E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@wdc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1604025486936220.3290469487938; Thu, 29 Oct 2020 19:38:06 -0700 (PDT) Received: from localhost ([::1]:59774 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kYKIn-00043M-Ns for importer@patchew.org; Thu, 29 Oct 2020 22:38:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41124) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kYKDp-0005f2-91; Thu, 29 Oct 2020 22:32:57 -0400 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:10984) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kYKDk-0006cy-Ln; Thu, 29 Oct 2020 22:32:56 -0400 Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 30 Oct 2020 10:32:50 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Oct 2020 19:17:55 -0700 Received: from unknown (HELO redsun50.ssa.fujisawa.hgst.com) ([10.149.66.24]) by uls-op-cesaip01.wdc.com with ESMTP; 29 Oct 2020 19:32:49 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1604025172; x=1635561172; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sJfeCQHJ4b6kZ7bQQ3zkoS9KoX1KA99USQyP+uPAQOw=; b=V91rBy5zW0TfdFobMzfBgfvtJlF7Qcn9/0oXhq4WAaZaad8xlCUhhxTF SEMBMyo0/L2rrVzqcfeJBy3w8+fCD/34wr1cN61H45CjxW3y98B3X3JH3 hQUnrPvX4A85f9DnRM99/KU3QMAeFa+JrnID4nf+Y+OqEzqIBftYpYZCI xMQyqzCsFnSN+73OcQUGDsaU46ZuED18TfzjYFZfUwmxuLyYdQOvgM+g1 FDMd3q7c7WweNxBLWJTdJKHU8+ZMCY1YYG1yVQ7P6QpaEEGPPvYyo4u5M Yw1owleiIlitq7jqT/CUJ5q2zXMYOQVKRBKyV5VSSgu/Wdi/4/9YTfYXA A==; IronPort-SDR: fhKMsVZX5edwhJokBs7u+21t4dWjzv6EpOR0uHC1vixWs+ddZ1TAAdUfsuyIgaEbWejl2umBle IW8qt/qCyMjxWN8UETP7UtYLcupDgxB2BnDujZdzm7ey8diXQoxgTYzHBIgpazArohzhH1uLNT YJrUaXsGDcQOFquKLNmCHygNTqHEoQQoniu9/6h3yBj2QtovbBKhxBW4dlzXxdNYpm61VvrZSx uROqw9DIWAWY9akmbFIxHpp3uhbcB3zB/t7v72N0eZVyrkWDFON5IEu4N+/SEuxQC1P3ep07oA Czc= X-IronPort-AV: E=Sophos;i="5.77,431,1596470400"; d="scan'208";a="155748051" IronPort-SDR: nTD7ZzpNzf6EajYeXFt/asRvgZXlYOWjXzmKWpWXVpMttrBasMnCjAlIqmFekYUGFIPhkIuTgV 4EeXkjw8+1Cmn9S/Ix7tjvFHSYNNHTfr8aKQ5ZdZYOJaXfC1B+Ul5oDxA/J376wQmxv+KW/5Zl LoQLb36DzRbwrGSOJ4bfRIUwArNQDeVR0sTAl8J8Pqo35iBFNbqau1znyG8PmmkvJ6pkOi5Bdw 9Kg4DMMbV6aKH043olduDmvvhvSJHc3nVIH3DchNwzwKFgj7Bdn6G6S72rFCKSAWcyPpoe3rpr tz8ARZcCsQ54Ar5+h/rWJQ+9 IronPort-SDR: zLveBajxHZpUiOO261ZfWfJlClHLWKyJrbRgm/HfcflCfHSRn6/y4Oqgv4TvA0KDDGnHDhmdsL yQGOV9tIkPRlev++LaYQBkMUbHrTd6sqdFvLXqKqwj6a8NF4yxQXMlk10ue6Z1m1tWGG1Np2l/ jh76CSXDSH6q00E9ORhoFppxb81ZOzaLN6UcRQmtmgAlfrjv+FoIvmvCMX48iKGEtHIVkAAihx 0ppsWfzJ7gMEUpxd8L7jSccPEkgc62l7AIHI+viQMZdCZJhY1ozvNk999H2UrKZSWrIWZohflm 6MA= WDCIronportException: Internal From: Dmitry Fomichev To: Keith Busch , Klaus Jensen , Kevin Wolf , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Maxim Levitsky , Fam Zheng Subject: [PATCH v8 01/11] hw/block/nvme: Add Commands Supported and Effects log Date: Fri, 30 Oct 2020 11:32:32 +0900 Message-Id: <20201030023242.5204-2-dmitry.fomichev@wdc.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20201030023242.5204-1-dmitry.fomichev@wdc.com> References: <20201030023242.5204-1-dmitry.fomichev@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.141; envelope-from=prvs=56530b5a8=dmitry.fomichev@wdc.com; helo=esa3.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 22:32:49 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Niklas Cassel , Damien Le Moal , qemu-block@nongnu.org, Dmitry Fomichev , qemu-devel@nongnu.org, Alistair Francis , Matias Bjorling Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This log page becomes necessary to implement to allow checking for Zone Append command support in Zoned Namespace Command Set. This commit adds the code to report this log page for NVM Command Set only. The parts that are specific to zoned operation will be added later in the series. All incoming admin and i/o commands are now only processed if their corresponding support bits are set in this log. This provides an easy way to control what commands to support and what not to depending on set CC.CSS. Signed-off-by: Dmitry Fomichev Reviewed-by: Niklas Cassel --- hw/block/nvme-ns.h | 1 + hw/block/nvme.c | 96 +++++++++++++++++++++++++++++++++++++++---- hw/block/trace-events | 1 + include/block/nvme.h | 19 +++++++++ 4 files changed, 108 insertions(+), 9 deletions(-) diff --git a/hw/block/nvme-ns.h b/hw/block/nvme-ns.h index 83734f4606..ea8c2f785d 100644 --- a/hw/block/nvme-ns.h +++ b/hw/block/nvme-ns.h @@ -29,6 +29,7 @@ typedef struct NvmeNamespace { int32_t bootindex; int64_t size; NvmeIdNs id_ns; + const uint32_t *iocs; =20 NvmeNamespaceParams params; } NvmeNamespace; diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 9d30ca69dc..9fed061a9d 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -111,6 +111,28 @@ static const uint32_t nvme_feature_cap[NVME_FID_MAX] = =3D { [NVME_TIMESTAMP] =3D NVME_FEAT_CAP_CHANGE, }; =20 +static const uint32_t nvme_cse_acs[256] =3D { + [NVME_ADM_CMD_DELETE_SQ] =3D NVME_CMD_EFF_CSUPP, + [NVME_ADM_CMD_CREATE_SQ] =3D NVME_CMD_EFF_CSUPP, + [NVME_ADM_CMD_GET_LOG_PAGE] =3D NVME_CMD_EFF_CSUPP, + [NVME_ADM_CMD_DELETE_CQ] =3D NVME_CMD_EFF_CSUPP, + [NVME_ADM_CMD_CREATE_CQ] =3D NVME_CMD_EFF_CSUPP, + [NVME_ADM_CMD_IDENTIFY] =3D NVME_CMD_EFF_CSUPP, + [NVME_ADM_CMD_ABORT] =3D NVME_CMD_EFF_CSUPP, + [NVME_ADM_CMD_SET_FEATURES] =3D NVME_CMD_EFF_CSUPP, + [NVME_ADM_CMD_GET_FEATURES] =3D NVME_CMD_EFF_CSUPP, + [NVME_ADM_CMD_ASYNC_EV_REQ] =3D NVME_CMD_EFF_CSUPP, +}; + +static const uint32_t nvme_cse_iocs_none[256]; + +static const uint32_t nvme_cse_iocs_nvm[256] =3D { + [NVME_CMD_FLUSH] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, + [NVME_CMD_WRITE_ZEROES] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, + [NVME_CMD_WRITE] =3D NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_= LBCC, + [NVME_CMD_READ] =3D NVME_CMD_EFF_CSUPP, +}; + static void nvme_process_sq(void *opaque); =20 static uint16_t nvme_cid(NvmeRequest *req) @@ -1032,10 +1054,6 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest= *req) trace_pci_nvme_io_cmd(nvme_cid(req), nsid, nvme_sqid(req), req->cmd.opcode, nvme_io_opc_str(req->cmd.opcode= )); =20 - if (NVME_CC_CSS(n->bar.cc) =3D=3D NVME_CC_CSS_ADMIN_ONLY) { - return NVME_INVALID_OPCODE | NVME_DNR; - } - if (!nvme_nsid_valid(n, nsid)) { return NVME_INVALID_NSID | NVME_DNR; } @@ -1045,6 +1063,11 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest= *req) return NVME_INVALID_FIELD | NVME_DNR; } =20 + if (!(req->ns->iocs[req->cmd.opcode] & NVME_CMD_EFF_CSUPP)) { + trace_pci_nvme_err_invalid_opc(req->cmd.opcode); + return NVME_INVALID_OPCODE | NVME_DNR; + } + switch (req->cmd.opcode) { case NVME_CMD_FLUSH: return nvme_flush(n, req); @@ -1054,8 +1077,7 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest = *req) case NVME_CMD_READ: return nvme_rw(n, req); default: - trace_pci_nvme_err_invalid_opc(req->cmd.opcode); - return NVME_INVALID_OPCODE | NVME_DNR; + assert(false); } } =20 @@ -1291,6 +1313,37 @@ static uint16_t nvme_error_info(NvmeCtrl *n, uint8_t= rae, uint32_t buf_len, DMA_DIRECTION_FROM_DEVICE, req); } =20 +static uint16_t nvme_cmd_effects(NvmeCtrl *n, uint32_t buf_len, + uint64_t off, NvmeRequest *req) +{ + NvmeEffectsLog log =3D {}; + const uint32_t *src_iocs =3D NULL; + uint32_t trans_len; + + if (off >=3D sizeof(log)) { + trace_pci_nvme_err_invalid_log_page_offset(off, sizeof(log)); + return NVME_INVALID_FIELD | NVME_DNR; + } + + switch (NVME_CC_CSS(n->bar.cc)) { + case NVME_CC_CSS_NVM: + src_iocs =3D nvme_cse_iocs_nvm; + case NVME_CC_CSS_ADMIN_ONLY: + break; + } + + memcpy(log.acs, nvme_cse_acs, sizeof(nvme_cse_acs)); + + if (src_iocs) { + memcpy(log.iocs, src_iocs, sizeof(log.iocs)); + } + + trans_len =3D MIN(sizeof(log) - off, buf_len); + + return nvme_dma(n, ((uint8_t *)&log) + off, trans_len, + DMA_DIRECTION_FROM_DEVICE, req); +} + static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req) { NvmeCmd *cmd =3D &req->cmd; @@ -1334,6 +1387,8 @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest= *req) return nvme_smart_info(n, rae, len, off, req); case NVME_LOG_FW_SLOT_INFO: return nvme_fw_log_info(n, len, off, req); + case NVME_LOG_CMD_EFFECTS: + return nvme_cmd_effects(n, len, off, req); default: trace_pci_nvme_err_invalid_log_page(nvme_cid(req), lid); return NVME_INVALID_FIELD | NVME_DNR; @@ -1920,6 +1975,11 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeRequ= est *req) trace_pci_nvme_admin_cmd(nvme_cid(req), nvme_sqid(req), req->cmd.opcod= e, nvme_adm_opc_str(req->cmd.opcode)); =20 + if (!(nvme_cse_acs[req->cmd.opcode] & NVME_CMD_EFF_CSUPP)) { + trace_pci_nvme_err_invalid_admin_opc(req->cmd.opcode); + return NVME_INVALID_OPCODE | NVME_DNR; + } + switch (req->cmd.opcode) { case NVME_ADM_CMD_DELETE_SQ: return nvme_del_sq(n, req); @@ -1942,8 +2002,7 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeReque= st *req) case NVME_ADM_CMD_ASYNC_EV_REQ: return nvme_aer(n, req); default: - trace_pci_nvme_err_invalid_admin_opc(req->cmd.opcode); - return NVME_INVALID_OPCODE | NVME_DNR; + assert(false); } } =20 @@ -2031,6 +2090,23 @@ static void nvme_clear_ctrl(NvmeCtrl *n) n->bar.cc =3D 0; } =20 +static void nvme_select_ns_iocs(NvmeCtrl *n) +{ + NvmeNamespace *ns; + int i; + + for (i =3D 1; i <=3D n->num_namespaces; i++) { + ns =3D nvme_ns(n, i); + if (!ns) { + continue; + } + ns->iocs =3D nvme_cse_iocs_none; + if (NVME_CC_CSS(n->bar.cc) !=3D NVME_CC_CSS_ADMIN_ONLY) { + ns->iocs =3D nvme_cse_iocs_nvm; + } + } +} + static int nvme_start_ctrl(NvmeCtrl *n) { uint32_t page_bits =3D NVME_CC_MPS(n->bar.cc) + 12; @@ -2129,6 +2205,8 @@ static int nvme_start_ctrl(NvmeCtrl *n) =20 QTAILQ_INIT(&n->aer_queue); =20 + nvme_select_ns_iocs(n); + return 0; } =20 @@ -2737,7 +2815,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pc= i_dev) id->acl =3D 3; id->aerl =3D n->params.aerl; id->frmw =3D (NVME_NUM_FW_SLOTS << 1) | NVME_FRMW_SLOT1_RO; - id->lpa =3D NVME_LPA_NS_SMART | NVME_LPA_EXTENDED; + id->lpa =3D NVME_LPA_NS_SMART | NVME_LPA_CSE | NVME_LPA_EXTENDED; =20 /* recommended default value (~70 C) */ id->wctemp =3D cpu_to_le16(NVME_TEMPERATURE_WARNING); diff --git a/hw/block/trace-events b/hw/block/trace-events index fac5995d94..3ea6c29926 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -104,6 +104,7 @@ pci_nvme_err_invalid_prp(void) "invalid PRP" pci_nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx= 8"" pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limi= t) "Invalid LBA start=3D%"PRIu64" len=3D%"PRIu64" limit=3D%"PRIu64"" +pci_nvme_err_invalid_log_page_offset(uint64_t ofs, uint64_t size) "must be= <=3D %"PRIu64", got %"PRIu64"" pci_nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue deleti= on, sid=3D%"PRIu16"" pci_nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating submis= sion queue, invalid cqid=3D%"PRIu16"" pci_nvme_err_invalid_create_sq_sqid(uint16_t sqid) "failed creating submis= sion queue, invalid sqid=3D%"PRIu16"" diff --git a/include/block/nvme.h b/include/block/nvme.h index 6de2d5aa75..4779495b7d 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -744,10 +744,27 @@ enum NvmeSmartWarn { NVME_SMART_FAILED_VOLATILE_MEDIA =3D 1 << 4, }; =20 +typedef struct NvmeEffectsLog { + uint32_t acs[256]; + uint32_t iocs[256]; + uint8_t resv[2048]; +} NvmeEffectsLog; + +enum { + NVME_CMD_EFF_CSUPP =3D 1 << 0, + NVME_CMD_EFF_LBCC =3D 1 << 1, + NVME_CMD_EFF_NCC =3D 1 << 2, + NVME_CMD_EFF_NIC =3D 1 << 3, + NVME_CMD_EFF_CCC =3D 1 << 4, + NVME_CMD_EFF_CSE_MASK =3D 3 << 16, + NVME_CMD_EFF_UUID_SEL =3D 1 << 19, +}; + enum NvmeLogIdentifier { NVME_LOG_ERROR_INFO =3D 0x01, NVME_LOG_SMART_INFO =3D 0x02, NVME_LOG_FW_SLOT_INFO =3D 0x03, + NVME_LOG_CMD_EFFECTS =3D 0x05, }; =20 typedef struct QEMU_PACKED NvmePSD { @@ -860,6 +877,7 @@ enum NvmeIdCtrlFrmw { =20 enum NvmeIdCtrlLpa { NVME_LPA_NS_SMART =3D 1 << 0, + NVME_LPA_CSE =3D 1 << 1, NVME_LPA_EXTENDED =3D 1 << 2, }; =20 @@ -1059,6 +1077,7 @@ static inline void _nvme_check_size(void) QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) !=3D 64); QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) !=3D 512); QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) !=3D 512); + QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) !=3D 4096); QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) !=3D 4096); QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) !=3D 4096); QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) !=3D 16); --=20 2.21.0