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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::643; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x643.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This function makes it clear that we're talking about the whole register, and not the 32-bit piece at index 0. This fixes a bug when running on a big-endian host. Signed-off-by: Richard Henderson --- target/arm/translate.c | 8 ++++++ target/arm/translate-neon.c.inc | 44 ++++++++++++++++----------------- target/arm/translate-vfp.c.inc | 2 +- 3 files changed, 31 insertions(+), 23 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 38371db540..1b61e50f9c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1094,6 +1094,14 @@ static inline void gen_hlt(DisasContext *s, int imm) unallocated_encoding(s); } =20 +/* + * Return the offset of a "full" NEON Dreg. + */ +static long neon_full_reg_offset(unsigned reg) +{ + return offsetof(CPUARMState, vfp.zregs[reg >> 1].d[reg & 1]); +} + static inline long vfp_reg_offset(bool dp, unsigned reg) { if (dp) { diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index 4d1a292981..e259e24c05 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -76,7 +76,7 @@ neon_element_offset(int reg, int element, MemOp size) ofs ^=3D 8 - element_size; } #endif - return neon_reg_offset(reg, 0) + ofs; + return neon_full_reg_offset(reg) + ofs; } =20 static void neon_load_element(TCGv_i32 var, int reg, int ele, MemOp mop) @@ -585,12 +585,12 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_= VLD_all_lanes *a) * We cannot write 16 bytes at once because the * destination is unaligned. */ - tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd), 8, 8, tmp); - tcg_gen_gvec_mov(0, neon_reg_offset(vd + 1, 0), - neon_reg_offset(vd, 0), 8, 8); + tcg_gen_gvec_mov(0, neon_full_reg_offset(vd + 1), + neon_full_reg_offset(vd), 8, 8); } else { - tcg_gen_gvec_dup_i32(size, neon_reg_offset(vd, 0), + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(vd), vec_size, vec_size, tmp); } tcg_gen_addi_i32(addr, addr, 1 << size); @@ -691,9 +691,9 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLD= ST_single *a) static bool do_3same(DisasContext *s, arg_3same *a, GVecGen3Fn fn) { int vec_size =3D a->q ? 16 : 8; - int rd_ofs =3D neon_reg_offset(a->vd, 0); - int rn_ofs =3D neon_reg_offset(a->vn, 0); - int rm_ofs =3D neon_reg_offset(a->vm, 0); + int rd_ofs =3D neon_full_reg_offset(a->vd); + int rn_ofs =3D neon_full_reg_offset(a->vn); + int rm_ofs =3D neon_full_reg_offset(a->vm); =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -1177,8 +1177,8 @@ static bool do_vector_2sh(DisasContext *s, arg_2reg_s= hift *a, GVecGen2iFn *fn) { /* Handle a 2-reg-shift insn which can be vectorized. */ int vec_size =3D a->q ? 16 : 8; - int rd_ofs =3D neon_reg_offset(a->vd, 0); - int rm_ofs =3D neon_reg_offset(a->vm, 0); + int rd_ofs =3D neon_full_reg_offset(a->vd); + int rm_ofs =3D neon_full_reg_offset(a->vm); =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -1620,8 +1620,8 @@ static bool do_fp_2sh(DisasContext *s, arg_2reg_shift= *a, { /* FP operations in 2-reg-and-shift group */ int vec_size =3D a->q ? 16 : 8; - int rd_ofs =3D neon_reg_offset(a->vd, 0); - int rm_ofs =3D neon_reg_offset(a->vm, 0); + int rd_ofs =3D neon_full_reg_offset(a->vd); + int rm_ofs =3D neon_full_reg_offset(a->vm); TCGv_ptr fpst; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { @@ -1756,7 +1756,7 @@ static bool do_1reg_imm(DisasContext *s, arg_1reg_imm= *a, return true; } =20 - reg_ofs =3D neon_reg_offset(a->vd, 0); + reg_ofs =3D neon_full_reg_offset(a->vd); vec_size =3D a->q ? 16 : 8; imm =3D asimd_imm_const(a->imm, a->cmode, a->op); =20 @@ -2300,9 +2300,9 @@ static bool trans_VMULL_P_3d(DisasContext *s, arg_3di= ff *a) return true; } =20 - tcg_gen_gvec_3_ool(neon_reg_offset(a->vd, 0), - neon_reg_offset(a->vn, 0), - neon_reg_offset(a->vm, 0), + tcg_gen_gvec_3_ool(neon_full_reg_offset(a->vd), + neon_full_reg_offset(a->vn), + neon_full_reg_offset(a->vm), 16, 16, 0, fn_gvec); return true; } @@ -2445,8 +2445,8 @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2s= calar *a, { /* Two registers and a scalar, using gvec */ int vec_size =3D a->q ? 16 : 8; - int rd_ofs =3D neon_reg_offset(a->vd, 0); - int rn_ofs =3D neon_reg_offset(a->vn, 0); + int rd_ofs =3D neon_full_reg_offset(a->vd); + int rn_ofs =3D neon_full_reg_offset(a->vn); int rm_ofs; int idx; TCGv_ptr fpstatus; @@ -2477,7 +2477,7 @@ static bool do_2scalar_fp_vec(DisasContext *s, arg_2s= calar *a, /* a->vm is M:Vm, which encodes both register and index */ idx =3D extract32(a->vm, a->size + 2, 2); a->vm =3D extract32(a->vm, 0, a->size + 2); - rm_ofs =3D neon_reg_offset(a->vm, 0); + rm_ofs =3D neon_full_reg_offset(a->vm); =20 fpstatus =3D fpstatus_ptr(a->size =3D=3D 1 ? FPST_STD_F16 : FPST_STD); tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, fpstatus, @@ -2923,7 +2923,7 @@ static bool trans_VDUP_scalar(DisasContext *s, arg_VD= UP_scalar *a) return true; } =20 - tcg_gen_gvec_dup_mem(a->size, neon_reg_offset(a->vd, 0), + tcg_gen_gvec_dup_mem(a->size, neon_full_reg_offset(a->vd), neon_element_offset(a->vm, a->index, a->size), a->q ? 16 : 8, a->q ? 16 : 8); return true; @@ -3412,8 +3412,8 @@ static bool trans_VCVT_F32_F16(DisasContext *s, arg_2= misc *a) static bool do_2misc_vec(DisasContext *s, arg_2misc *a, GVecGen2Fn *fn) { int vec_size =3D a->q ? 16 : 8; - int rd_ofs =3D neon_reg_offset(a->vd, 0); - int rm_ofs =3D neon_reg_offset(a->vm, 0); + int rd_ofs =3D neon_full_reg_offset(a->vd); + int rm_ofs =3D neon_full_reg_offset(a->vm); =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index a7ed9bc81b..368bae0a73 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -653,7 +653,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) } =20 tmp =3D load_reg(s, a->rt); - tcg_gen_gvec_dup_i32(size, neon_reg_offset(a->vn, 0), + tcg_gen_gvec_dup_i32(size, neon_full_reg_offset(a->vn), vec_size, vec_size, tmp); tcg_temp_free_i32(tmp); =20 --=20 2.25.1