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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, j@getutm.app, laurent@vivier.eu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" There is nothing within the translators that ought to be changing the TranslationBlock data, so make it const. This does not actually use the read-only copy of the data structure that exists within the rx mirror. Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 ++- target/arm/cpu.c | 3 ++- target/avr/cpu.c | 3 ++- target/hppa/cpu.c | 3 ++- target/i386/cpu.c | 3 ++- target/microblaze/cpu.c | 3 ++- target/mips/cpu.c | 3 ++- target/riscv/cpu.c | 3 ++- target/rx/cpu.c | 3 ++- target/sh4/cpu.c | 3 ++- target/sparc/cpu.c | 3 ++- target/tricore/cpu.c | 2 +- 12 files changed, 23 insertions(+), 12 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 9c3a45ad7b..67253e662b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -189,7 +189,8 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb= ); + void (*synchronize_from_tb)(CPUState *cpu, + const struct TranslationBlock *tb); bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 07492e9f9a..2f9be1c0ee 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -54,7 +54,8 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) } } =20 -static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void arm_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5d9c4ad5bf..6f3d5a9e4a 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -41,7 +41,8 @@ static bool avr_cpu_has_work(CPUState *cs) && cpu_interrupts_enabled(env); } =20 -static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void avr_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { AVRCPU *cpu =3D AVR_CPU(cs); CPUAVRState *env =3D &cpu->env; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 71b6aca45d..e28f047d10 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -35,7 +35,8 @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.iaoq_b =3D value + 4; } =20 -static void hppa_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *t= b) +static void hppa_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { HPPACPU *cpu =3D HPPA_CPU(cs); =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0d8606958e..01a8acafe3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7012,7 +7012,8 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.eip =3D value; } =20 -static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void x86_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { X86CPU *cpu =3D X86_CPU(cs); =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 9b2482159d..c8e754cfb1 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -83,7 +83,8 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.iflags =3D 0; } =20 -static void mb_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void mb_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 76d50b00b4..79eee215cf 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -44,7 +44,8 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value) } } =20 -static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *t= b) +static void mips_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { MIPSCPU *cpu =3D MIPS_CPU(cs); CPUMIPSState *env =3D &cpu->env; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f457..faaa9d1e8f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -282,7 +282,8 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value) env->pc =3D value; } =20 -static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *= tb) +static void riscv_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 23ee17a701..2bb14144a7 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -33,7 +33,8 @@ static void rx_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 -static void rx_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +static void rx_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { RXCPU *cpu =3D RX_CPU(cs); =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 3c68021c56..1e0f05a15b 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -34,7 +34,8 @@ static void superh_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.pc =3D value; } =20 -static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock = *tb) +static void superh_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { SuperHCPU *cpu =3D SUPERH_CPU(cs); =20 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index cf21efd85f..b9241208b1 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -691,7 +691,8 @@ static void sparc_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.npc =3D value + 4; } =20 -static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *= tb) +static void sparc_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) { SPARCCPU *cpu =3D SPARC_CPU(cs); =20 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 2f2e5b029f..4bff1d4718 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -42,7 +42,7 @@ static void tricore_cpu_set_pc(CPUState *cs, vaddr value) } =20 static void tricore_cpu_synchronize_from_tb(CPUState *cs, - TranslationBlock *tb) + const TranslationBlock *tb) { TriCoreCPU *cpu =3D TRICORE_CPU(cs); CPUTriCoreState *env =3D &cpu->env; --=20 2.25.1