From nobody Sat May 18 21:45:35 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1603983662; cv=none; d=zohomail.com; s=zohoarc; b=FHg4g9ecCCcq2N62CdddprQ5tM3uowd93fWVr1Euv7ll0CZCaoN4sFf0uFpptdpe73XSSOz+dSwtqq8n3XXVU96JlxLhuH6FCA1MDuNXsaoMZRcPqVlQZgKA8TznGkAGIPwqPXb7qjzlOiTrEBU6jQlTEXg/L52tx+70gYDb/U8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603983662; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=XtxBzT/D3DJNfRUU3UQsV0xdb1+r54x9XhvV1FwO1yc=; b=PWMOXttGlsHaKH4HlX3aH3AWVWDTwpUxFKeveD/i1UVyvb+Vb+KQrf3JTb0u/4Tc1+veaYz3Mjqqlb5AclZx1UBrBBof6EEBSsi5vsRB/tUtQtKCW7VuCyK0g60AfSto9j7KpAVCyIEn5AvdIXNpgxsbZalVqsqdpqsPu4WZ2uw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1603983662745736.6365506457776; Thu, 29 Oct 2020 08:01:02 -0700 (PDT) Received: from localhost ([::1]:48516 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kY9QC-0004Zp-4Q for importer@patchew.org; Thu, 29 Oct 2020 11:01:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33922) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kY6J1-0002jr-OT for qemu-devel@nongnu.org; Thu, 29 Oct 2020 07:41:26 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:2058) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kY6It-0002J3-93 for qemu-devel@nongnu.org; Thu, 29 Oct 2020 07:41:23 -0400 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4CMNmt4xLMzhZFX; Thu, 29 Oct 2020 19:41:02 +0800 (CST) Received: from huawei.com (10.174.187.148) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.487.0; Thu, 29 Oct 2020 19:40:49 +0800 From: Binfeng Wu To: Subject: [PATCH] vfio-pci: add Ascend devices passthrough quirks Date: Thu, 29 Oct 2020 19:40:48 +0800 Message-ID: <20201029114048.700-1-wubinfeng@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.187.148] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=wubinfeng@huawei.com; helo=szxga06-in.huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 07:41:00 X-ACL-Warn: Detected OS = Linux 3.1-3.10 [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 29 Oct 2020 10:57:05 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, qemu-devel@nongnu.org, Binfeng Wu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Ascend is a series of SoC processors developed by Huawei. Ascend310/910 are highly efficient, flexible, and programmable AI processors in this series and support device passthrough via vfio-pci. Ascends device xloader update is only allowed in host, because update triggered by vm users may affect other users when Ascend devices passthrough to vm. Set a bar quirk is an effective method to keep vm users from updating xloader. In this patch, two bar quirks were proposed to cover Ascend310/910 respectively. Signed-off-by: Binfeng Wu --- hw/vfio/pci-quirks.c | 104 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index 57150913b7..291a45d3ab 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1202,6 +1202,108 @@ int vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev, return 0; } =20 +#define PCI_VENDOR_ID_HUAWEI 0x19e5 +#define PCI_DEVICE_ID_ASCEND910 0xd801 +#define PCI_DEVICE_ID_ASCEND310 0xd100 +#define ASCEND910_XLOADER_SIZE 4 +#define ASCEND910_XLOADER_OFFSET 0x80400 +#define ASCEND310_XLOADER_SIZE 4 +#define ASCEND310_XLOADER_OFFSET 0x400 + +typedef struct VFIOAscendBarQuirk { + struct VFIOPCIDevice *vdev; + pcibus_t offset; + uint8_t bar; + MemoryRegion *mem; +} VFIOAscendBarQuirk; + +static uint64_t vfio_ascend_quirk_read(void *opaque, + hwaddr addr, unsigned size) +{ + VFIOAscendBarQuirk *quirk =3D opaque; + VFIOPCIDevice *vdev =3D quirk->vdev; + + return vfio_region_read(&vdev->bars[quirk->bar].region, + addr + quirk->offset, size); +} + +static void vfio_ascend_quirk_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ +} + +static const MemoryRegionOps vfio_ascend_intercept_regs_quirk =3D { + .read =3D vfio_ascend_quirk_read, + .write =3D vfio_ascend_quirk_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void vfio_probe_ascend_bar0_quirk(VFIOPCIDevice *vdev, int nr) +{ + VFIOQuirk *quirk; + VFIOAscendBarQuirk *bar0_quirk; + + if (!vfio_pci_is(vdev, PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ASCEND910) = || + nr !=3D 0) { + return; + } + + quirk =3D g_malloc0(sizeof(*quirk)); + quirk->nr_mem =3D 1; + quirk->mem =3D g_new0(MemoryRegion, quirk->nr_mem); + bar0_quirk =3D quirk->data =3D g_new0(typeof(*bar0_quirk), quirk->nr_m= em); + bar0_quirk[0].vdev =3D vdev; + bar0_quirk[0].offset =3D ASCEND910_XLOADER_OFFSET; + bar0_quirk[0].bar =3D nr; + + /* + * intercept w/r to the xloader-updating register, + * so the vm can't enable xloader-updating + */ + memory_region_init_io(&quirk->mem[0], OBJECT(vdev), + &vfio_ascend_intercept_regs_quirk, + &bar0_quirk[0], + "vfio-ascend-bar0-intercept-regs-quirk", + ASCEND910_XLOADER_SIZE); + memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, + bar0_quirk[0].offset, + &quirk->mem[0], 1); + QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); +} + +static void vfio_probe_ascend_bar4_quirk(VFIOPCIDevice *vdev, int nr) +{ + VFIOQuirk *quirk; + VFIOAscendBarQuirk *bar4_quirk; + + if (!vfio_pci_is(vdev, PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_ASCEND310) = || + nr !=3D 4) { + return; + } + + quirk =3D g_malloc0(sizeof(*quirk)); + quirk->nr_mem =3D 1; + quirk->mem =3D g_new0(MemoryRegion, quirk->nr_mem); + bar4_quirk =3D quirk->data =3D g_new0(typeof(*bar4_quirk), quirk->nr_m= em); + bar4_quirk[0].vdev =3D vdev; + bar4_quirk[0].offset =3D ASCEND310_XLOADER_OFFSET; + bar4_quirk[0].bar =3D nr; + + /* + * intercept w/r to the xloader-updating register, + * so the vm can't enable xloader-updating + */ + memory_region_init_io(&quirk->mem[0], OBJECT(vdev), + &vfio_ascend_intercept_regs_quirk, + &bar4_quirk[0], + "vfio-ascend-bar4-intercept-regs-quirk", + ASCEND310_XLOADER_SIZE); + memory_region_add_subregion_overlap(vdev->bars[nr].region.mem, + bar4_quirk[0].offset, + &quirk->mem[0], 1); + QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next); +} + /* * Common quirk probe entry points. */ @@ -1251,6 +1353,8 @@ void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr) vfio_probe_nvidia_bar5_quirk(vdev, nr); vfio_probe_nvidia_bar0_quirk(vdev, nr); vfio_probe_rtl8168_bar2_quirk(vdev, nr); + vfio_probe_ascend_bar0_quirk(vdev, nr); + vfio_probe_ascend_bar4_quirk(vdev, nr); #ifdef CONFIG_VFIO_IGD vfio_probe_igd_bar4_quirk(vdev, nr); #endif --=20 2.26.2.windows.1