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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.227.221.253; envelope-from=keithp@keithp.com; helo=elaine.keithp.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/28 14:57:36 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Keith Packard From: Keith Packard via X-ZohoMail-DKIM: fail (found 2 invalid signatures) Content-Type: text/plain; charset="utf-8" This commit renames two files which provide ARM semihosting support so that they can be shared by other architectures: 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c 2. linux-user/arm/semihost.c -> linux-user/semihost.c The build system was modified use a new config variable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard Reviewed-by: Alistair Francis ---- v2 Place common-semi.c name in arm_ss, just as arm-semi.c was v3 Create CONFIG_ARM_COMPATIBLE_SEMIHOSTING and assign in arm config files --- default-configs/devices/arm-softmmu.mak | 1 + default-configs/targets/aarch64-linux-user.mak | 1 + default-configs/targets/arm-linux-user.mak | 1 + hw/semihosting/Kconfig | 3 +++ target/arm/arm-semi.c =3D> hw/semihosting/common-semi.c | 0 hw/semihosting/meson.build | 3 +++ linux-user/arm/meson.build | 3 --- linux-user/meson.build | 1 + linux-user/{arm =3D> }/semihost.c | 0 target/arm/meson.build | 2 -- 10 files changed, 10 insertions(+), 5 deletions(-) rename target/arm/arm-semi.c =3D> hw/semihosting/common-semi.c (100%) rename linux-user/{arm =3D> }/semihost.c (100%) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devi= ces/arm-softmmu.mak index 08a32123b4..0500156a0c 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -42,4 +42,5 @@ CONFIG_FSL_IMX25=3Dy CONFIG_FSL_IMX7=3Dy CONFIG_FSL_IMX6UL=3Dy CONFIG_SEMIHOSTING=3Dy +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy CONFIG_ALLWINNER_H3=3Dy diff --git a/default-configs/targets/aarch64-linux-user.mak b/default-confi= gs/targets/aarch64-linux-user.mak index 163c9209f4..4713253709 100644 --- a/default-configs/targets/aarch64-linux-user.mak +++ b/default-configs/targets/aarch64-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=3Daarch64 TARGET_BASE_ARCH=3Darm TARGET_XML_FILES=3D gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-x= ml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-neon.x= ml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=3Dy +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy diff --git a/default-configs/targets/arm-linux-user.mak b/default-configs/t= argets/arm-linux-user.mak index c7cd872e86..e741ffd4d3 100644 --- a/default-configs/targets/arm-linux-user.mak +++ b/default-configs/targets/arm-linux-user.mak @@ -3,3 +3,4 @@ TARGET_SYSTBL_ABI=3Dcommon,oabi TARGET_SYSTBL=3Dsyscall.tbl TARGET_XML_FILES=3D gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-v= fp3.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml TARGET_HAS_BFLT=3Dy +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy diff --git a/hw/semihosting/Kconfig b/hw/semihosting/Kconfig index efe0a30734..4c30dc6b16 100644 --- a/hw/semihosting/Kconfig +++ b/hw/semihosting/Kconfig @@ -1,3 +1,6 @@ =20 config SEMIHOSTING bool + +config ARM_COMPATIBLE_SEMIHOSTING + bool diff --git a/target/arm/arm-semi.c b/hw/semihosting/common-semi.c similarity index 100% rename from target/arm/arm-semi.c rename to hw/semihosting/common-semi.c diff --git a/hw/semihosting/meson.build b/hw/semihosting/meson.build index f40ac574c4..5b4a170270 100644 --- a/hw/semihosting/meson.build +++ b/hw/semihosting/meson.build @@ -2,3 +2,6 @@ specific_ss.add(when: 'CONFIG_SEMIHOSTING', if_true: files( 'config.c', 'console.c', )) + +specific_ss.add(when: ['CONFIG_ARM_COMPATIBLE_SEMIHOSTING'], + if_true: files('common-semi.c')) diff --git a/linux-user/arm/meson.build b/linux-user/arm/meson.build index 432984b58e..5a93c925cf 100644 --- a/linux-user/arm/meson.build +++ b/linux-user/arm/meson.build @@ -1,6 +1,3 @@ -linux_user_ss.add(when: 'TARGET_AARCH64', if_true: files('semihost.c')) -linux_user_ss.add(when: 'TARGET_ARM', if_true: files('semihost.c')) - subdir('nwfpe') =20 syscall_nr_generators +=3D { diff --git a/linux-user/meson.build b/linux-user/meson.build index 2b94e4ba24..7fe28d659e 100644 --- a/linux-user/meson.build +++ b/linux-user/meson.build @@ -16,6 +16,7 @@ linux_user_ss.add(rt) =20 linux_user_ss.add(when: 'TARGET_HAS_BFLT', if_true: files('flatload.c')) linux_user_ss.add(when: 'TARGET_I386', if_true: files('vm86.c')) +linux_user_ss.add(when: 'CONFIG_ARM_COMPATIBLE_SEMIHOSTING', if_true: file= s('semihost.c')) =20 =20 syscall_nr_generators =3D {} diff --git a/linux-user/arm/semihost.c b/linux-user/semihost.c similarity index 100% rename from linux-user/arm/semihost.c rename to linux-user/semihost.c diff --git a/target/arm/meson.build b/target/arm/meson.build index f5de2a77b8..15b936c101 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -32,8 +32,6 @@ arm_ss.add(files( )) arm_ss.add(zlib) =20 -arm_ss.add(when: 'CONFIG_TCG', if_true: files('arm-semi.c')) - arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_fals= e: files('kvm-stub.c')) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( --=20 2.28.0 From nobody Sat May 18 22:14:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.227.221.253; envelope-from=keithp@keithp.com; helo=elaine.keithp.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/28 14:57:36 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Keith Packard From: Keith Packard via X-ZohoMail-DKIM: fail (found 2 invalid signatures) The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-by: Keith Packard Reviewed-by: Alistair Francis --- hw/semihosting/common-semi.c | 16 ++++++++++------ hw/semihosting/common-semi.h | 36 +++++++++++++++++++++++++++++++++++ linux-user/aarch64/cpu_loop.c | 3 ++- linux-user/arm/cpu_loop.c | 3 ++- target/arm/cpu.h | 8 -------- target/arm/helper.c | 5 +++-- target/arm/m_helper.c | 7 ++++++- 7 files changed, 59 insertions(+), 19 deletions(-) create mode 100644 hw/semihosting/common-semi.h diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index 8718fd0194..e0c59bc599 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -1,10 +1,14 @@ /* - * Arm "Angel" semihosting syscalls + * Semihosting support for systems modeled on the Arm "Angel" + * semihosting syscalls design. * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro * Written by Paul Brook. * + * Copyright =C2=A9 2020 by Keith Packard + * Adapted for systems other than ARM, including RISC-V, by Keith Packard + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -371,12 +375,12 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_= syscall_complete_cb cb, * do anything with its return value, because it is not necessarily * the result of the syscall, but could just be the old value of X0. * The only thing safe to do with this is that the callers of - * do_arm_semihosting() will write it straight back into X0. + * do_common_semihosting() will write it straight back into X0. * (In linux-user mode, the callback will have happened before * gdb_do_syscallv() returns.) * * We should tidy this up so neither this function nor - * do_arm_semihosting() return a value, so the mistake of + * do_common_semihosting() return a value, so the mistake of * doing something with the return value is not possible to make. */ =20 @@ -673,10 +677,10 @@ static const GuestFDFunctions guestfd_fns[] =3D { * leave the register unchanged. We use 0xdeadbeef as the return value * when there isn't a defined return value for the call. */ -target_ulong do_arm_semihosting(CPUARMState *env) +target_ulong do_common_semihosting(CPUState *cs) { - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D env_cpu(env); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; diff --git a/hw/semihosting/common-semi.h b/hw/semihosting/common-semi.h new file mode 100644 index 0000000000..bc53e92c79 --- /dev/null +++ b/hw/semihosting/common-semi.h @@ -0,0 +1,36 @@ +/* + * Semihosting support for systems modeled on the Arm "Angel" + * semihosting syscalls design. + * + * Copyright (c) 2005, 2007 CodeSourcery. + * Copyright (c) 2019 Linaro + * Written by Paul Brook. + * + * Copyright =C2=A9 2020 by Keith Packard + * Adapted for systems other than ARM, including RISC-V, by Keith Packard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + * + * ARM Semihosting is documented in: + * Semihosting for AArch32 and AArch64 Release 2.0 + * https://static.docs.arm.com/100863/0200/semihosting.pdf + * + */ + +#ifndef COMMON_SEMI_H +#define COMMON_SEMI_H + +target_ulong do_common_semihosting(CPUState *cs); + +#endif /* COMMON_SEMI_H */ diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index bbe9fefca8..42b9c15f53 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "cpu_loop-common.h" #include "qemu/guest-random.h" +#include "hw/semihosting/common-semi.h" =20 #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ @@ -129,7 +130,7 @@ void cpu_loop(CPUARMState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_SEMIHOST: - env->xregs[0] =3D do_arm_semihosting(env); + env->xregs[0] =3D do_common_semihosting(cs); env->pc +=3D 4; break; case EXCP_YIELD: diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 13629ee1f6..31dbb4d1af 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -22,6 +22,7 @@ #include "qemu.h" #include "elf.h" #include "cpu_loop-common.h" +#include "hw/semihosting/common-semi.h" =20 #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ @@ -393,7 +394,7 @@ void cpu_loop(CPUARMState *env) } break; case EXCP_SEMIHOST: - env->regs[0] =3D do_arm_semihosting(env); + env->regs[0] =3D do_common_semihosting(cs); env->regs[15] +=3D env->thumb ? 2 : 4; break; case EXCP_INTERRUPT: diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 49cd5cabcf..c7ece27c56 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1068,14 +1068,6 @@ static inline void aarch64_sve_change_el(CPUARMState= *env, int o, static inline void aarch64_add_sve_properties(Object *obj) { } #endif =20 -#if !defined(CONFIG_TCG) -static inline target_ulong do_arm_semihosting(CPUARMState *env) -{ - g_assert_not_reached(); -} -#else -target_ulong do_arm_semihosting(CPUARMState *env); -#endif void aarch64_sync_32_to_64(CPUARMState *env); void aarch64_sync_64_to_32(CPUARMState *env); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 97bb6b8c01..8dbb0ef5d3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -34,6 +34,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" +#include "hw/semihosting/common-semi.h" #endif =20 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ @@ -9889,13 +9890,13 @@ static void handle_semihosting(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%" PRIx64 "\n", env->xregs[0]); - env->xregs[0] =3D do_arm_semihosting(env); + env->xregs[0] =3D do_common_semihosting(cs); env->pc +=3D 4; } else { qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); - env->regs[0] =3D do_arm_semihosting(env); + env->regs[0] =3D do_common_semihosting(cs); env->regs[15] +=3D env->thumb ? 2 : 4; } } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 036454234c..ef897382de 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -31,6 +31,7 @@ #ifdef CONFIG_TCG #include "arm_ldst.h" #include "exec/cpu_ldst.h" +#include "hw/semihosting/common-semi.h" #endif =20 static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, @@ -2188,7 +2189,11 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); - env->regs[0] =3D do_arm_semihosting(env); +#ifdef CONFIG_TCG + env->regs[0] =3D do_common_semihosting(cs); +#else + g_assert_not_reached(); +#endif env->regs[15] +=3D env->thumb ? 2 : 4; return; case EXCP_BKPT: --=20 2.28.0 From nobody Sat May 18 22:14:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=wXCcSk+T2u5ROsVX0/StAJbrh67LJxFEfm/2EnysJuoZE+P6ELUVbthpbWv7hGWLi D19niDlPlVpu5iptPN9kJ+sw2p2Be4s3Gm1gbpsZN2e71YBrSODwqv6dKYG4Fo+PrT g4S9aTYnLSJZABMapt7xfrslfCxFBMV1hAwO/1/NdFlrm4CFg+ilUvxTAIitSp7cD6 QSzJ5YjijPJIHCZqa1QCTwRhL7z4G4/twPv4k02/+2GQbPttHhc/NCulsMVBG2QRB9 Q6xaCtgnEQ1yEFY0v4A34SLlbtAbeTCfSyEh9AZgNGAXgkCqUvirn5mD/NcnzcZ60S 2rJgxG6ElSSrg== To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Laurent Vivier , Peter Maydell , qemu-arm@nongnu.org, Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , qemu-riscv@nongnu.org, Keith Packard Subject: [PATCH 3/4] semihosting: Change internal common-semi interfaces to use CPUState * Date: Wed, 28 Oct 2020 11:57:21 -0700 Message-Id: <20201028185722.2783532-4-keithp@keithp.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201028185722.2783532-1-keithp@keithp.com> References: <20201028185722.2783532-1-keithp@keithp.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.227.221.253; envelope-from=keithp@keithp.com; helo=elaine.keithp.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/28 14:57:36 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Keith Packard From: Keith Packard via X-ZohoMail-DKIM: fail (found 2 invalid signatures) Content-Type: text/plain; charset="utf-8" This makes all of the internal interfaces architecture-independent and renames the internal functions to use the 'common_semi' prefix instead of 'arm' or 'arm_semi'. To do this, some new architecture-specific internal helper functions were created: static inline target_ulong common_semi_arg(CPUState *cs, int argno) Returns the argno'th semihosting argument, where argno can be either 0 or 1. static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) Sets the semihosting return value. static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr) This detects whether the specified semihosting call, which is either TARGET_SYS_EXIT or TARGET_SYS_EXIT_EXTENDED should be executed using the TARGET_SYS_EXIT_EXTENDED semantics. In addition, several existing functions have been changed to flag areas of code which are architecture specific: static target_ulong common_semi_flen_buf(CPUState *cs) Returns the current stack pointer minus 64, which is where a stat structure will be placed on the stack #define GET_ARG(n) This fetches arguments from the semihosting command's argument block. The address of this is available implicitly through the local 'args' variable. This is *mostly* architecture independent, but does depend on the current ABI's notion of the size of a 'long' parameter, which may need run-time checks (as it does on AARCH64) #define SET_ARG(n, val) This mirrors GET_ARG and stores data back into the argument block. Signed-off-by: Keith Packard Reviewed-by: Alistair Francis --- hw/semihosting/common-semi.c | 326 ++++++++++++++++++----------------- 1 file changed, 164 insertions(+), 162 deletions(-) diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index e0c59bc599..c77fb21bec 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -32,11 +32,12 @@ #include "cpu.h" #include "hw/semihosting/semihost.h" #include "hw/semihosting/console.h" +#include "hw/semihosting/common-semi.h" #include "qemu/log.h" #ifdef CONFIG_USER_ONLY #include "qemu.h" =20 -#define ARM_ANGEL_HEAP_SIZE (128 * 1024 * 1024) +#define COMMON_SEMI_HEAP_SIZE (128 * 1024 * 1024) #else #include "exec/gdbstub.h" #include "qemu/cutils.h" @@ -132,6 +133,36 @@ typedef struct GuestFD { =20 static GArray *guestfd_array; =20 +#ifdef TARGET_ARM +static inline target_ulong +common_semi_arg(CPUState *cs, int argno) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + if (is_a64(env)) + return env->xregs[argno]; + else + return env->regs[argno]; +} + +static inline void +common_semi_set_ret(CPUState *cs, target_ulong ret) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + if (is_a64(env)) + env->xregs[0] =3D ret; + else + env->regs[0] =3D ret; +} + +static inline bool +common_semi_sys_exit_extended(CPUState *cs, int nr) +{ + return (nr =3D=3D TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr)); +} +#endif /* TARGET_ARM */ + /* * Allocate a new guest file descriptor and return it; if we * couldn't allocate a new fd then return -1. @@ -237,11 +268,10 @@ static target_ulong syscall_err; #include "exec/softmmu-semi.h" #endif =20 -static inline uint32_t set_swi_errno(CPUARMState *env, uint32_t code) +static inline uint32_t set_swi_errno(CPUState *cs, uint32_t code) { if (code =3D=3D (uint32_t)-1) { #ifdef CONFIG_USER_ONLY - CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; =20 ts->swi_errno =3D errno; @@ -252,10 +282,9 @@ static inline uint32_t set_swi_errno(CPUARMState *env,= uint32_t code) return code; } =20 -static inline uint32_t get_swi_errno(CPUARMState *env) +static inline uint32_t get_swi_errno(CPUState *cs) { #ifdef CONFIG_USER_ONLY - CPUState *cs =3D env_cpu(env); TaskState *ts =3D cs->opaque; =20 return ts->swi_errno; @@ -264,24 +293,22 @@ static inline uint32_t get_swi_errno(CPUARMState *env) #endif } =20 -static target_ulong arm_semi_syscall_len; +static target_ulong common_semi_syscall_len; =20 -static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err) +static void common_semi_cb(CPUState *cs, target_ulong ret, target_ulong er= r) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - target_ulong reg0 =3D is_a64(env) ? env->xregs[0] : env->regs[0]; + target_ulong reg0 =3D common_semi_arg(cs, 0); =20 if (ret =3D=3D (target_ulong)-1) { errno =3D err; - set_swi_errno(env, -1); + set_swi_errno(cs, -1); reg0 =3D ret; } else { /* Fixup syscalls that use nonstardard return conventions. */ switch (reg0) { case TARGET_SYS_WRITE: case TARGET_SYS_READ: - reg0 =3D arm_semi_syscall_len - ret; + reg0 =3D common_semi_syscall_len - ret; break; case TARGET_SYS_SEEK: reg0 =3D 0; @@ -291,77 +318,62 @@ static void arm_semi_cb(CPUState *cs, target_ulong re= t, target_ulong err) break; } } - if (is_a64(env)) { - env->xregs[0] =3D reg0; - } else { - env->regs[0] =3D reg0; - } + common_semi_set_ret(cs, reg0); } =20 -static target_ulong arm_flen_buf(ARMCPU *cpu) +static target_ulong common_semi_flen_buf(CPUState *cs) { + target_ulong sp; +#ifdef TARGET_ARM /* Return an address in target memory of 64 bytes where the remote * gdb should write its stat struct. (The format of this structure * is defined by GDB's remote protocol and is not target-specific.) * We put this on the guest's stack just below SP. */ + ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; - target_ulong sp; =20 if (is_a64(env)) { sp =3D env->xregs[31]; } else { sp =3D env->regs[13]; } +#endif =20 return sp - 64; } =20 -static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong = err) +static void common_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulo= ng err) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; /* The size is always stored in big-endian order, extract the value. We assume the size always fit in 32 bits. */ uint32_t size; - cpu_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, (uint8_t *)&size, 4, 0= ); + cpu_memory_rw_debug(cs, common_semi_flen_buf(cs) + 32, (uint8_t *)&siz= e, 4, 0); size =3D be32_to_cpu(size); - if (is_a64(env)) { - env->xregs[0] =3D size; - } else { - env->regs[0] =3D size; - } + common_semi_set_ret(cs, size); errno =3D err; - set_swi_errno(env, -1); + set_swi_errno(cs, -1); } =20 -static int arm_semi_open_guestfd; +static int common_semi_open_guestfd; =20 -static void arm_semi_open_cb(CPUState *cs, target_ulong ret, target_ulong = err) +static void common_semi_open_cb(CPUState *cs, target_ulong ret, target_ulo= ng err) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; if (ret =3D=3D (target_ulong)-1) { errno =3D err; - set_swi_errno(env, -1); - dealloc_guestfd(arm_semi_open_guestfd); - } else { - associate_guestfd(arm_semi_open_guestfd, ret); - ret =3D arm_semi_open_guestfd; - } - - if (is_a64(env)) { - env->xregs[0] =3D ret; + set_swi_errno(cs, -1); + dealloc_guestfd(common_semi_open_guestfd); } else { - env->regs[0] =3D ret; + associate_guestfd(common_semi_open_guestfd, ret); + ret =3D common_semi_open_guestfd; } + common_semi_set_ret(cs, ret); } =20 -static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_syscall_complete_cb c= b, - const char *fmt, ...) +static target_ulong common_semi_gdb_syscall(CPUState *cs, gdb_syscall_comp= lete_cb cb, + const char *fmt, ...) { va_list va; - CPUARMState *env =3D &cpu->env; =20 va_start(va, fmt); gdb_do_syscallv(cb, fmt, va); @@ -384,7 +396,7 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_sy= scall_complete_cb cb, * doing something with the return value is not possible to make. */ =20 - return is_a64(env) ? env->xregs[0] : env->regs[0]; + return common_semi_arg(cs, 0); } =20 /* @@ -393,20 +405,18 @@ static target_ulong arm_gdb_syscall(ARMCPU *cpu, gdb_= syscall_complete_cb cb, * do the work and return the required return value for the guest, * setting the guest errno if appropriate. */ -typedef uint32_t sys_closefn(ARMCPU *cpu, GuestFD *gf); -typedef uint32_t sys_writefn(ARMCPU *cpu, GuestFD *gf, +typedef uint32_t sys_closefn(CPUState *cs, GuestFD *gf); +typedef uint32_t sys_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len); -typedef uint32_t sys_readfn(ARMCPU *cpu, GuestFD *gf, +typedef uint32_t sys_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len); -typedef uint32_t sys_isattyfn(ARMCPU *cpu, GuestFD *gf); -typedef uint32_t sys_seekfn(ARMCPU *cpu, GuestFD *gf, +typedef uint32_t sys_isattyfn(CPUState *cs, GuestFD *gf); +typedef uint32_t sys_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset); -typedef uint32_t sys_flenfn(ARMCPU *cpu, GuestFD *gf); +typedef uint32_t sys_flenfn(CPUState *cs, GuestFD *gf); =20 -static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) +static uint32_t host_closefn(CPUState *cs, GuestFD *gf) { - CPUARMState *env =3D &cpu->env; - /* * Only close the underlying host fd if it's one we opened on behalf * of the guest in SYS_OPEN. @@ -416,20 +426,21 @@ static uint32_t host_closefn(ARMCPU *cpu, GuestFD *gf) gf->hostfd =3D=3D STDERR_FILENO) { return 0; } - return set_swi_errno(env, close(gf->hostfd)); + return set_swi_errno(cs, close(gf->hostfd)); } =20 -static uint32_t host_writefn(ARMCPU *cpu, GuestFD *gf, +static uint32_t host_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { + CPUArchState *env =3D cs->env_ptr; uint32_t ret; - CPUARMState *env =3D &cpu->env; char *s =3D lock_user(VERIFY_READ, buf, len, 1); + (void) env; /* Used in arm softmmu lock_user implicitly */ if (!s) { /* Return bytes not written on error */ return len; } - ret =3D set_swi_errno(env, write(gf->hostfd, s, len)); + ret =3D set_swi_errno(cs, write(gf->hostfd, s, len)); unlock_user(s, buf, 0); if (ret =3D=3D (uint32_t)-1) { ret =3D 0; @@ -438,18 +449,19 @@ static uint32_t host_writefn(ARMCPU *cpu, GuestFD *gf, return len - ret; } =20 -static uint32_t host_readfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t host_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { + CPUArchState *env =3D cs->env_ptr; uint32_t ret; - CPUARMState *env =3D &cpu->env; char *s =3D lock_user(VERIFY_WRITE, buf, len, 0); + (void) env; /* Used in arm softmmu lock_user implicitly */ if (!s) { /* return bytes not read */ return len; } do { - ret =3D set_swi_errno(env, read(gf->hostfd, s, len)); + ret =3D set_swi_errno(cs, read(gf->hostfd, s, len)); } while (ret =3D=3D -1 && errno =3D=3D EINTR); unlock_user(s, buf, len); if (ret =3D=3D (uint32_t)-1) { @@ -459,68 +471,66 @@ static uint32_t host_readfn(ARMCPU *cpu, GuestFD *gf, return len - ret; } =20 -static uint32_t host_isattyfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t host_isattyfn(CPUState *cs, GuestFD *gf) { return isatty(gf->hostfd); } =20 -static uint32_t host_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) +static uint32_t host_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset) { - CPUARMState *env =3D &cpu->env; - uint32_t ret =3D set_swi_errno(env, lseek(gf->hostfd, offset, SEEK_SET= )); + uint32_t ret =3D set_swi_errno(cs, lseek(gf->hostfd, offset, SEEK_SET)= ); if (ret =3D=3D (uint32_t)-1) { return -1; } return 0; } =20 -static uint32_t host_flenfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t host_flenfn(CPUState *cs, GuestFD *gf) { - CPUARMState *env =3D &cpu->env; struct stat buf; - uint32_t ret =3D set_swi_errno(env, fstat(gf->hostfd, &buf)); + uint32_t ret =3D set_swi_errno(cs, fstat(gf->hostfd, &buf)); if (ret =3D=3D (uint32_t)-1) { return -1; } return buf.st_size; } =20 -static uint32_t gdb_closefn(ARMCPU *cpu, GuestFD *gf) +static uint32_t gdb_closefn(CPUState *cs, GuestFD *gf) { - return arm_gdb_syscall(cpu, arm_semi_cb, "close,%x", gf->hostfd); + return common_semi_gdb_syscall(cs, common_semi_cb, "close,%x", gf->hos= tfd); } =20 -static uint32_t gdb_writefn(ARMCPU *cpu, GuestFD *gf, +static uint32_t gdb_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { - arm_semi_syscall_len =3D len; - return arm_gdb_syscall(cpu, arm_semi_cb, "write,%x,%x,%x", - gf->hostfd, buf, len); + common_semi_syscall_len =3D len; + return common_semi_gdb_syscall(cs, common_semi_cb, "write,%x,%x,%x", + gf->hostfd, buf, len); } =20 -static uint32_t gdb_readfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t gdb_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { - arm_semi_syscall_len =3D len; - return arm_gdb_syscall(cpu, arm_semi_cb, "read,%x,%x,%x", - gf->hostfd, buf, len); + common_semi_syscall_len =3D len; + return common_semi_gdb_syscall(cs, common_semi_cb, "read,%x,%x,%x", + gf->hostfd, buf, len); } =20 -static uint32_t gdb_isattyfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t gdb_isattyfn(CPUState *cs, GuestFD *gf) { - return arm_gdb_syscall(cpu, arm_semi_cb, "isatty,%x", gf->hostfd); + return common_semi_gdb_syscall(cs, common_semi_cb, "isatty,%x", gf->ho= stfd); } =20 -static uint32_t gdb_seekfn(ARMCPU *cpu, GuestFD *gf, target_ulong offset) +static uint32_t gdb_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset) { - return arm_gdb_syscall(cpu, arm_semi_cb, "lseek,%x,%x,0", - gf->hostfd, offset); + return common_semi_gdb_syscall(cs, common_semi_cb, "lseek,%x,%x,0", + gf->hostfd, offset); } =20 -static uint32_t gdb_flenfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t gdb_flenfn(CPUState *cs, GuestFD *gf) { - return arm_gdb_syscall(cpu, arm_semi_flen_cb, "fstat,%x,%x", - gf->hostfd, arm_flen_buf(cpu)); + return common_semi_gdb_syscall(cs, common_semi_flen_cb, "fstat,%x,%x", + gf->hostfd, common_semi_flen_buf(cs)); } =20 #define SHFB_MAGIC_0 0x53 @@ -549,31 +559,29 @@ static void init_featurefile_guestfd(int guestfd) gf->featurefile_offset =3D 0; } =20 -static uint32_t featurefile_closefn(ARMCPU *cpu, GuestFD *gf) +static uint32_t featurefile_closefn(CPUState *cs, GuestFD *gf) { /* Nothing to do */ return 0; } =20 -static uint32_t featurefile_writefn(ARMCPU *cpu, GuestFD *gf, +static uint32_t featurefile_writefn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { /* This fd can never be open for writing */ - CPUARMState *env =3D &cpu->env; =20 errno =3D EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } =20 -static uint32_t featurefile_readfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t featurefile_readfn(CPUState *cs, GuestFD *gf, target_ulong buf, uint32_t len) { + CPUArchState *env =3D cs->env_ptr; uint32_t i; -#ifndef CONFIG_USER_ONLY - CPUARMState *env =3D &cpu->env; -#endif char *s; =20 + (void) env; /* Used in arm softmmu lock_user implicitly */ s =3D lock_user(VERIFY_WRITE, buf, len, 0); if (!s) { return len; @@ -593,19 +601,19 @@ static uint32_t featurefile_readfn(ARMCPU *cpu, Guest= FD *gf, return len - i; } =20 -static uint32_t featurefile_isattyfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t featurefile_isattyfn(CPUState *cs, GuestFD *gf) { return 0; } =20 -static uint32_t featurefile_seekfn(ARMCPU *cpu, GuestFD *gf, +static uint32_t featurefile_seekfn(CPUState *cs, GuestFD *gf, target_ulong offset) { gf->featurefile_offset =3D offset; return 0; } =20 -static uint32_t featurefile_flenfn(ARMCPU *cpu, GuestFD *gf) +static uint32_t featurefile_flenfn(CPUState *cs, GuestFD *gf) { return sizeof(featurefile_data); } @@ -649,16 +657,17 @@ static const GuestFDFunctions guestfd_fns[] =3D { /* Read the input value from the argument block; fail the semihosting * call if the memory read fails. */ +#ifdef TARGET_ARM #define GET_ARG(n) do { \ if (is_a64(env)) { \ if (get_user_u64(arg ## n, args + (n) * 8)) { \ errno =3D EFAULT; \ - return set_swi_errno(env, -1); \ + return set_swi_errno(cs, -1); \ } \ } else { \ if (get_user_u32(arg ## n, args + (n) * 4)) { \ errno =3D EFAULT; \ - return set_swi_errno(env, -1); \ + return set_swi_errno(cs, -1); \ } \ } \ } while (0) @@ -667,6 +676,7 @@ static const GuestFDFunctions guestfd_fns[] =3D { (is_a64(env) ? \ put_user_u64(val, args + (n) * 8) : \ put_user_u32(val, args + (n) * 4)) +#endif =20 /* * Do a semihosting call. @@ -679,8 +689,7 @@ static const GuestFDFunctions guestfd_fns[] =3D { */ target_ulong do_common_semihosting(CPUState *cs) { - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; + CPUArchState *env =3D cs->env_ptr; target_ulong args; target_ulong arg0, arg1, arg2, arg3; char * s; @@ -689,14 +698,9 @@ target_ulong do_common_semihosting(CPUState *cs) uint32_t len; GuestFD *gf; =20 - if (is_a64(env)) { - /* Note that the syscall number is in W0, not X0 */ - nr =3D env->xregs[0] & 0xffffffffU; - args =3D env->xregs[1]; - } else { - nr =3D env->regs[0]; - args =3D env->regs[1]; - } + (void) env; /* Used implicitly by arm lock_user macro */ + nr =3D common_semi_arg(cs, 0) & 0xffffffffU; + args =3D common_semi_arg(cs, 1); =20 switch (nr) { case TARGET_SYS_OPEN: @@ -709,19 +713,19 @@ target_ulong do_common_semihosting(CPUState *cs) s =3D lock_user_string(arg0); if (!s) { errno =3D EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } if (arg1 >=3D 12) { unlock_user(s, arg0, 0); errno =3D EINVAL; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } =20 guestfd =3D alloc_guestfd(); if (guestfd < 0) { unlock_user(s, arg0, 0); errno =3D EMFILE; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } =20 if (strcmp(s, ":tt") =3D=3D 0) { @@ -750,18 +754,18 @@ target_ulong do_common_semihosting(CPUState *cs) if (arg1 !=3D 0 && arg1 !=3D 1) { dealloc_guestfd(guestfd); errno =3D EACCES; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } init_featurefile_guestfd(guestfd); return guestfd; } =20 if (use_gdb_syscalls()) { - arm_semi_open_guestfd =3D guestfd; - ret =3D arm_gdb_syscall(cpu, arm_semi_open_cb, "open,%s,%x,1a4= ", arg0, - (int)arg2+1, gdb_open_modeflags[arg1]); + common_semi_open_guestfd =3D guestfd; + ret =3D common_semi_gdb_syscall(cs, common_semi_open_cb, "open= ,%s,%x,1a4", arg0, + (int)arg2+1, gdb_open_modeflags[= arg1]); } else { - ret =3D set_swi_errno(env, open(s, open_modeflags[arg1], 0644)= ); + ret =3D set_swi_errno(cs, open(s, open_modeflags[arg1], 0644)); if (ret =3D=3D (uint32_t)-1) { dealloc_guestfd(guestfd); } else { @@ -778,17 +782,17 @@ target_ulong do_common_semihosting(CPUState *cs) gf =3D get_guestfd(arg0); if (!gf) { errno =3D EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } =20 - ret =3D guestfd_fns[gf->type].closefn(cpu, gf); + ret =3D guestfd_fns[gf->type].closefn(cs, gf); dealloc_guestfd(arg0); return ret; case TARGET_SYS_WRITEC: - qemu_semihosting_console_outc(env, args); + qemu_semihosting_console_outc(cs->env_ptr, args); return 0xdeadbeef; case TARGET_SYS_WRITE0: - return qemu_semihosting_console_outs(env, args); + return qemu_semihosting_console_outs(cs->env_ptr, args); case TARGET_SYS_WRITE: GET_ARG(0); GET_ARG(1); @@ -798,10 +802,10 @@ target_ulong do_common_semihosting(CPUState *cs) gf =3D get_guestfd(arg0); if (!gf) { errno =3D EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } =20 - return guestfd_fns[gf->type].writefn(cpu, gf, arg1, len); + return guestfd_fns[gf->type].writefn(cs, gf, arg1, len); case TARGET_SYS_READ: GET_ARG(0); GET_ARG(1); @@ -811,22 +815,22 @@ target_ulong do_common_semihosting(CPUState *cs) gf =3D get_guestfd(arg0); if (!gf) { errno =3D EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } =20 - return guestfd_fns[gf->type].readfn(cpu, gf, arg1, len); + return guestfd_fns[gf->type].readfn(cs, gf, arg1, len); case TARGET_SYS_READC: - return qemu_semihosting_console_inc(env); + return qemu_semihosting_console_inc(cs->env_ptr); case TARGET_SYS_ISTTY: GET_ARG(0); =20 gf =3D get_guestfd(arg0); if (!gf) { errno =3D EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } =20 - return guestfd_fns[gf->type].isattyfn(cpu, gf); + return guestfd_fns[gf->type].isattyfn(cs, gf); case TARGET_SYS_SEEK: GET_ARG(0); GET_ARG(1); @@ -834,20 +838,20 @@ target_ulong do_common_semihosting(CPUState *cs) gf =3D get_guestfd(arg0); if (!gf) { errno =3D EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } =20 - return guestfd_fns[gf->type].seekfn(cpu, gf, arg1); + return guestfd_fns[gf->type].seekfn(cs, gf, arg1); case TARGET_SYS_FLEN: GET_ARG(0); =20 gf =3D get_guestfd(arg0); if (!gf) { errno =3D EBADF; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } =20 - return guestfd_fns[gf->type].flenfn(cpu, gf); + return guestfd_fns[gf->type].flenfn(cs, gf); case TARGET_SYS_TMPNAM: qemu_log_mask(LOG_UNIMP, "%s: SYS_TMPNAM not implemented", __func_= _); return -1; @@ -855,15 +859,15 @@ target_ulong do_common_semihosting(CPUState *cs) GET_ARG(0); GET_ARG(1); if (use_gdb_syscalls()) { - ret =3D arm_gdb_syscall(cpu, arm_semi_cb, "unlink,%s", - arg0, (int)arg1+1); + ret =3D common_semi_gdb_syscall(cs, common_semi_cb, "unlink,%s= ", + arg0, (int)arg1+1); } else { s =3D lock_user_string(arg0); if (!s) { errno =3D EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - ret =3D set_swi_errno(env, remove(s)); + ret =3D set_swi_errno(cs, remove(s)); unlock_user(s, arg0, 0); } return ret; @@ -873,17 +877,17 @@ target_ulong do_common_semihosting(CPUState *cs) GET_ARG(2); GET_ARG(3); if (use_gdb_syscalls()) { - return arm_gdb_syscall(cpu, arm_semi_cb, "rename,%s,%s", - arg0, (int)arg1+1, arg2, (int)arg3+1); + return common_semi_gdb_syscall(cs, common_semi_cb, "rename,%s,= %s", + arg0, (int)arg1+1, arg2, (int)a= rg3+1); } else { char *s2; s =3D lock_user_string(arg0); s2 =3D lock_user_string(arg2); if (!s || !s2) { errno =3D EFAULT; - ret =3D set_swi_errno(env, -1); + ret =3D set_swi_errno(cs, -1); } else { - ret =3D set_swi_errno(env, rename(s, s2)); + ret =3D set_swi_errno(cs, rename(s, s2)); } if (s2) unlock_user(s2, arg2, 0); @@ -894,25 +898,25 @@ target_ulong do_common_semihosting(CPUState *cs) case TARGET_SYS_CLOCK: return clock() / (CLOCKS_PER_SEC / 100); case TARGET_SYS_TIME: - return set_swi_errno(env, time(NULL)); + return set_swi_errno(cs, time(NULL)); case TARGET_SYS_SYSTEM: GET_ARG(0); GET_ARG(1); if (use_gdb_syscalls()) { - return arm_gdb_syscall(cpu, arm_semi_cb, "system,%s", - arg0, (int)arg1+1); + return common_semi_gdb_syscall(cs, common_semi_cb, "system,%s", + arg0, (int)arg1+1); } else { s =3D lock_user_string(arg0); if (!s) { errno =3D EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } - ret =3D set_swi_errno(env, system(s)); + ret =3D set_swi_errno(cs, system(s)); unlock_user(s, arg0, 0); return ret; } case TARGET_SYS_ERRNO: - return get_swi_errno(env); + return get_swi_errno(cs); case TARGET_SYS_GET_CMDLINE: { /* Build a command-line from the original argv. @@ -964,21 +968,21 @@ target_ulong do_common_semihosting(CPUState *cs) if (output_size > input_size) { /* Not enough space to store command-line arguments. */ errno =3D E2BIG; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } =20 /* Adjust the command-line length. */ if (SET_ARG(1, output_size - 1)) { /* Couldn't write back to argument block */ errno =3D EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } =20 /* Lock the buffer on the ARM side. */ output_buffer =3D lock_user(VERIFY_WRITE, arg0, output_size, 0= ); if (!output_buffer) { errno =3D EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } =20 /* Copy the command-line arguments. */ @@ -994,7 +998,7 @@ target_ulong do_common_semihosting(CPUState *cs) if (copy_from_user(output_buffer, ts->info->arg_start, output_size)) { errno =3D EFAULT; - status =3D set_swi_errno(env, -1); + status =3D set_swi_errno(cs, -1); goto out; } =20 @@ -1031,7 +1035,7 @@ target_ulong do_common_semihosting(CPUState *cs) abi_ulong ret; =20 ts->heap_base =3D do_brk(0); - limit =3D ts->heap_base + ARM_ANGEL_HEAP_SIZE; + limit =3D ts->heap_base + COMMON_SEMI_HEAP_SIZE; /* Try a big heap, and reduce the size if that fails. */ for (;;) { ret =3D do_brk(limit); @@ -1059,23 +1063,19 @@ target_ulong do_common_semihosting(CPUState *cs) for (i =3D 0; i < ARRAY_SIZE(retvals); i++) { bool fail; =20 - if (is_a64(env)) { - fail =3D put_user_u64(retvals[i], arg0 + i * 8); - } else { - fail =3D put_user_u32(retvals[i], arg0 + i * 4); - } + fail =3D SET_ARG(i, retvals[i]); =20 if (fail) { /* Couldn't write back to argument block */ errno =3D EFAULT; - return set_swi_errno(env, -1); + return set_swi_errno(cs, -1); } } return 0; } case TARGET_SYS_EXIT: case TARGET_SYS_EXIT_EXTENDED: - if (nr =3D=3D TARGET_SYS_EXIT_EXTENDED || is_a64(env)) { + if (common_semi_sys_exit_extended(cs, nr)) { /* * The A64 version of SYS_EXIT takes a parameter block, * so the application-exit type can return a subcode which @@ -1100,7 +1100,7 @@ target_ulong do_common_semihosting(CPUState *cs) */ ret =3D (args =3D=3D ADP_Stopped_ApplicationExit) ? 0 : 1; } - gdb_exit(env, ret); + gdb_exit(cs->env_ptr, ret); exit(ret); case TARGET_SYS_SYNCCACHE: /* @@ -1108,9 +1108,11 @@ target_ulong do_common_semihosting(CPUState *cs) * virtual address range. This is a nop for us since we don't * implement caches. This is only present on A64. */ - if (is_a64(env)) { +#ifdef TARGET_ARM + if (is_a64(cs->env_ptr)) { return 0; } +#endif /* fall through -- invalid for A32/T32 */ default: fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr); --=20 2.28.0 From nobody Sat May 18 22:14:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1603911933; cv=none; d=zohomail.com; s=zohoarc; b=f/I4lrzVx8PUJlfaWoXlsuq0SIlzmiaj8bwZclBySS5CbX1U0BaDu7d6sPYMAA59eSyY9kBHZOukdGnvOUE1Xl+YAjRNk0aZrEdAcUOmkkVDszW5g5bPEdr3QE720ZM0DOxO02mH2SO/CAwCE+sBKWDvHfmIPyNUsLl009ZS3CU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603911933; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.227.221.253; envelope-from=keithp@keithp.com; helo=elaine.keithp.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/28 14:57:36 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Keith Packard From: Keith Packard via X-ZohoMail-DKIM: fail (found 2 invalid signatures) Content-Type: text/plain; charset="utf-8" Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard --- v2: Update PC after exception is handled to follow change in the ARM version for SYS_READC v3: Disallow semihosting in user mode; report a regular breakpoint in that case. v4: Fix errors reported by checkpatch v5: Reference current RISC-V semihosting specification v6: Add support for semihosting in riscv64-linux-user and riscv32-linux-user v7: Add meson build support v8: Fix errors reported by checkpatch that crept in. v9: Changes suggested by Alistair Francis : Don't add me to the MAINTAINERS file. Remove duplicate #include in target/riscv/cpu.h Reference RISC-V semihosting spec in target/riscv/riscv-semi.c v10: Use common semihosting implementation instead of a separate copy. Make sure addresses of the three breakpoint-signaling instructions all lie within the same page. Change suggested by Richard Henderson v11: Use CONFIG_ARM_COMPATIBLE_SEMIHOSTING --- default-configs/devices/riscv32-softmmu.mak | 2 + default-configs/devices/riscv64-softmmu.mak | 2 + .../targets/riscv32-linux-user.mak | 1 + .../targets/riscv64-linux-user.mak | 1 + hw/semihosting/common-semi.c | 51 ++++++++++++++++++- hw/semihosting/common-semi.h | 5 +- linux-user/qemu.h | 4 +- linux-user/semihost.c | 8 +-- qemu-options.hx | 10 ++-- target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 10 ++++ .../riscv/insn_trans/trans_privileged.c.inc | 37 +++++++++++++- target/riscv/translate.c | 11 ++++ 13 files changed, 131 insertions(+), 12 deletions(-) diff --git a/default-configs/devices/riscv32-softmmu.mak b/default-configs/= devices/riscv32-softmmu.mak index 94a236c9c2..d847bd5692 100644 --- a/default-configs/devices/riscv32-softmmu.mak +++ b/default-configs/devices/riscv32-softmmu.mak @@ -3,6 +3,8 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=3Dn +CONFIG_SEMIHOSTING=3Dy +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy =20 # Boards: # diff --git a/default-configs/devices/riscv64-softmmu.mak b/default-configs/= devices/riscv64-softmmu.mak index 76b6195648..d5eec75f05 100644 --- a/default-configs/devices/riscv64-softmmu.mak +++ b/default-configs/devices/riscv64-softmmu.mak @@ -3,6 +3,8 @@ # Uncomment the following lines to disable these optional devices: # #CONFIG_PCI_DEVICES=3Dn +CONFIG_SEMIHOSTING=3Dy +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy =20 # Boards: # diff --git a/default-configs/targets/riscv32-linux-user.mak b/default-confi= gs/targets/riscv32-linux-user.mak index dfb259e8aa..6a9d1b1bc1 100644 --- a/default-configs/targets/riscv32-linux-user.mak +++ b/default-configs/targets/riscv32-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=3Driscv32 TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv TARGET_XML_FILES=3D gdb-xml/riscv-32bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-32bit-csr.xml gdb-xml/riscv-32b= it-virtual.xml +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy diff --git a/default-configs/targets/riscv64-linux-user.mak b/default-confi= gs/targets/riscv64-linux-user.mak index b13895f3b0..0a92849a1b 100644 --- a/default-configs/targets/riscv64-linux-user.mak +++ b/default-configs/targets/riscv64-linux-user.mak @@ -2,3 +2,4 @@ TARGET_ARCH=3Driscv64 TARGET_BASE_ARCH=3Driscv TARGET_ABI_DIR=3Driscv TARGET_XML_FILES=3D gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xm= l gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-csr.xml gdb-xml/riscv-64b= it-virtual.xml +CONFIG_ARM_COMPATIBLE_SEMIHOSTING=3Dy diff --git a/hw/semihosting/common-semi.c b/hw/semihosting/common-semi.c index c77fb21bec..8675934a71 100644 --- a/hw/semihosting/common-semi.c +++ b/hw/semihosting/common-semi.c @@ -1,6 +1,6 @@ /* * Semihosting support for systems modeled on the Arm "Angel" - * semihosting syscalls design. + * semihosting syscalls design. This includes Arm and RISC-V processors * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro @@ -25,6 +25,10 @@ * ARM Semihosting is documented in: * Semihosting for AArch32 and AArch64 Release 2.0 * https://static.docs.arm.com/100863/0200/semihosting.pdf + * + * RISC-V Semihosting is documented in: + * RISC-V Semihosting + * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-sem= ihosting-spec.adoc */ =20 #include "qemu/osdep.h" @@ -163,6 +167,30 @@ common_semi_sys_exit_extended(CPUState *cs, int nr) } #endif /* TARGET_ARM */ =20 +#ifdef TARGET_RISCV +static inline target_ulong +common_semi_arg(CPUState *cs, int argno) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + return env->gpr[xA0 + argno]; +} + +static inline void +common_semi_set_ret(CPUState *cs, target_ulong ret) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + env->gpr[xA0] =3D ret; +} + +static inline bool +common_semi_sys_exit_extended(CPUState *cs, int nr) +{ + return (nr =3D=3D TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) =3D= =3D 0); +} +#endif + /* * Allocate a new guest file descriptor and return it; if we * couldn't allocate a new fd then return -1. @@ -339,6 +367,12 @@ static target_ulong common_semi_flen_buf(CPUState *cs) sp =3D env->regs[13]; } #endif +#ifdef TARGET_RISCV + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + sp =3D env->gpr[xSP]; +#endif =20 return sp - 64; } @@ -678,6 +712,18 @@ static const GuestFDFunctions guestfd_fns[] =3D { put_user_u32(val, args + (n) * 4)) #endif =20 +#ifdef TARGET_RISCV +#define GET_ARG(n) do { \ + if (get_user_ual(arg ## n, args + (n) * sizeof(target_ulong))) { \ + errno =3D EFAULT; \ + return set_swi_errno(cs, -1); \ + } \ + } while (0) + +#define SET_ARG(n, val) \ + put_user_ual(val, args + (n) * sizeof(target_ulong)) +#endif + /* * Do a semihosting call. * @@ -1112,6 +1158,9 @@ target_ulong do_common_semihosting(CPUState *cs) if (is_a64(cs->env_ptr)) { return 0; } +#endif +#ifdef TARGET_RISCV + return 0; #endif /* fall through -- invalid for A32/T32 */ default: diff --git a/hw/semihosting/common-semi.h b/hw/semihosting/common-semi.h index bc53e92c79..0bfab1c669 100644 --- a/hw/semihosting/common-semi.h +++ b/hw/semihosting/common-semi.h @@ -1,6 +1,6 @@ /* * Semihosting support for systems modeled on the Arm "Angel" - * semihosting syscalls design. + * semihosting syscalls design. This includes Arm and RISC-V processors * * Copyright (c) 2005, 2007 CodeSourcery. * Copyright (c) 2019 Linaro @@ -26,6 +26,9 @@ * Semihosting for AArch32 and AArch64 Release 2.0 * https://static.docs.arm.com/100863/0200/semihosting.pdf * + * RISC-V Semihosting is documented in: + * RISC-V Semihosting + * https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-sem= ihosting-spec.adoc */ =20 #ifndef COMMON_SEMI_H diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 941ca99722..faeaab9614 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -105,6 +105,8 @@ typedef struct TaskState { /* FPA state */ FPA11 fpa; # endif +#endif +#if defined(TARGET_ARM) || defined(TARGET_RISCV) int swi_errno; #endif #if defined(TARGET_I386) && !defined(TARGET_X86_64) @@ -118,7 +120,7 @@ typedef struct TaskState { #ifdef TARGET_M68K abi_ulong tp_value; #endif -#if defined(TARGET_ARM) || defined(TARGET_M68K) +#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_RISCV) /* Extra fields for semihosted binaries. */ abi_ulong heap_base; abi_ulong heap_limit; diff --git a/linux-user/semihost.c b/linux-user/semihost.c index a1f0f6050e..c0015ee7f6 100644 --- a/linux-user/semihost.c +++ b/linux-user/semihost.c @@ -1,11 +1,11 @@ /* - * ARM Semihosting Console Support + * ARM Compatible Semihosting Console Support. * * Copyright (c) 2019 Linaro Ltd * - * Currently ARM is unique in having support for semihosting support - * in linux-user. So for now we implement the common console API but - * just for arm linux-user. + * Currently ARM and RISC-V are unique in having support for + * semihosting support in linux-user. So for now we implement the + * common console API but just for arm and risc-v linux-user. * * SPDX-License-Identifier: GPL-2.0-or-later */ diff --git a/qemu-options.hx b/qemu-options.hx index 2c83390504..9a606946c4 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -4184,10 +4184,10 @@ ERST DEF("semihosting", 0, QEMU_OPTION_semihosting, "-semihosting semihosting mode\n", QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | QEMU_ARCH_LM32 | - QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2) + QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2 | QEMU_ARCH_RISCV) SRST ``-semihosting`` - Enable semihosting mode (ARM, M68K, Xtensa, MIPS, Nios II only). + Enable semihosting mode (ARM, M68K, Xtensa, MIPS, Nios II, RISC-V only= ). =20 Note that this allows guest direct access to the host filesystem, so should only be used with a trusted guest OS. @@ -4199,10 +4199,10 @@ DEF("semihosting-config", HAS_ARG, QEMU_OPTION_semi= hosting_config, "-semihosting-config [enable=3Don|off][,target=3Dnative|gdb|auto][,cha= rdev=3Did][,arg=3Dstr[,...]]\n" \ " semihosting configuration\n", QEMU_ARCH_ARM | QEMU_ARCH_M68K | QEMU_ARCH_XTENSA | QEMU_ARCH_LM32 | -QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2) +QEMU_ARCH_MIPS | QEMU_ARCH_NIOS2 | QEMU_ARCH_RISCV) SRST ``-semihosting-config [enable=3Don|off][,target=3Dnative|gdb|auto][,charde= v=3Did][,arg=3Dstr[,...]]`` - Enable and configure semihosting (ARM, M68K, Xtensa, MIPS, Nios II + Enable and configure semihosting (ARM, M68K, Xtensa, MIPS, Nios II, RI= SC-V only). =20 Note that this allows guest direct access to the host filesystem, so @@ -4217,6 +4217,8 @@ SRST open/read/write/seek/select. Tensilica baremetal libc for ISS and linux platform "sim" use this interface. =20 + On RISC-V this implements the standard semihosting API, version 0.2. + ``target=3Dnative|gdb|auto`` Defines where the semihosting calls will be addressed, to QEMU (``native``) or to GDB (``gdb``). The default is ``auto``, which diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bd36062877..26a60b9e27 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -556,6 +556,7 @@ #define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0= */ #define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0= */ #define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0= */ +#define RISCV_EXCP_SEMIHOST 0x10 #define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14 #define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15 #define RISCV_EXCP_VIRT_INSTRUCTION_FAULT 0x16 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4652082df1..d71611ec02 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "trace.h" +#include "hw/semihosting/common-semi.h" =20 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -875,6 +876,15 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong htval =3D 0; target_ulong mtval2 =3D 0; =20 + if (cause =3D=3D RISCV_EXCP_SEMIHOST) { + if (env->priv >=3D PRV_S) { + env->gpr[xA0] =3D do_common_semihosting(cs); + env->pc +=3D 4; + return; + } + cause =3D RISCV_EXCP_BREAKPOINT; + } + if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 2a61a853bf..32312be202 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -29,7 +29,42 @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a) =20 static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) { - generate_exception(ctx, RISCV_EXCP_BREAKPOINT); + target_ulong ebreak_addr =3D ctx->base.pc_next; + target_ulong pre_addr =3D ebreak_addr - 4; + target_ulong post_addr =3D ebreak_addr + 4; + uint32_t pre =3D 0; + uint32_t ebreak =3D 0; + uint32_t post =3D 0; + + /* + * The RISC-V semihosting spec specifies the following + * three-instruction sequence to flag a semihosting call: + * + * slli zero, zero, 0x1f 0x01f01013 + * ebreak 0x00100073 + * srai zero, zero, 0x7 0x40705013 + * + * The two shift operations on the zero register are no-ops, used + * here to signify a semihosting exception, rather than a breakpoint. + * + * Uncompressed instructions are required so that the sequence is easy + * to validate. + * + * The three instructions are required to lie in the same page so + * that no exception will be raised when fetching them. + */ + + if ((pre_addr & TARGET_PAGE_MASK) =3D=3D (post_addr & TARGET_PAGE_MASK= )) { + pre =3D opcode_at(&ctx->base, pre_addr); + ebreak =3D opcode_at(&ctx->base, ebreak_addr); + post =3D opcode_at(&ctx->base, post_addr); + } + + if (pre =3D=3D 0x01f01013 && ebreak =3D=3D 0x00100073 && post =3D=3D = 0x40705013) { + generate_exception(ctx, RISCV_EXCP_SEMIHOST); + } else { + generate_exception(ctx, RISCV_EXCP_BREAKPOINT); + } exit_tb(ctx); /* no chaining */ ctx->base.is_jmp =3D DISAS_NORETURN; return true; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 79dca2291b..ecf594babc 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -63,6 +63,7 @@ typedef struct DisasContext { uint16_t vlen; uint16_t mlen; bool vl_eq_vlmax; + CPUState *cs; } DisasContext; =20 #ifdef TARGET_RISCV64 @@ -746,6 +747,15 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, return true; } =20 +static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + CPUState *cpu =3D ctx->cs; + CPURISCVState *env =3D cpu->env_ptr; + + return cpu_ldl_code(env, pc); +} + /* Include insn module translation function */ #include "insn_trans/trans_rvi.c.inc" #include "insn_trans/trans_rvm.c.inc" @@ -812,6 +822,7 @@ static void riscv_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) ctx->lmul =3D FIELD_EX32(tb_flags, TB_FLAGS, LMUL); ctx->mlen =3D 1 << (ctx->sew + 3 - ctx->lmul); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->cs =3D cs; } =20 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) --=20 2.28.0