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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 41/48] hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer
Date: Tue, 27 Oct 2020 11:44:31 +0000
Message-Id: <20201027114438.17662-42-peter.maydell@linaro.org>
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From: Luc Michel <luc@lmichel.fr>
This simple mux sits between the PLL channels and the DSI0E and DSI0P
clock muxes. This mux selects between PLLA-DSI0 and PLLD-DSI0 channel
and outputs the selected signal to source number 4 of DSI0E/P clock
muxes. It is controlled by the cm_dsi0hsck register.
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/misc/bcm2835_cprman.h | 15 +++++
include/hw/misc/bcm2835_cprman_internals.h | 6 ++
hw/misc/bcm2835_cprman.c | 74 +++++++++++++++++++++-
3 files changed, 94 insertions(+), 1 deletion(-)
diff --git a/include/hw/misc/bcm2835_cprman.h b/include/hw/misc/bcm2835_cpr=
man.h
index 0fc8f688457..3df4ceedd2e 100644
--- a/include/hw/misc/bcm2835_cprman.h
+++ b/include/hw/misc/bcm2835_cprman.h
@@ -174,6 +174,20 @@ typedef struct CprmanClockMuxState {
struct CprmanClockMuxState *backref[CPRMAN_NUM_CLOCK_MUX_SRC];
} CprmanClockMuxState;
=20
+typedef struct CprmanDsi0HsckMuxState {
+ /*< private >*/
+ DeviceState parent_obj;
+
+ /*< public >*/
+ CprmanClockMux id;
+
+ uint32_t *reg_cm;
+
+ Clock *plla_in;
+ Clock *plld_in;
+ Clock *out;
+} CprmanDsi0HsckMuxState;
+
struct BCM2835CprmanState {
/*< private >*/
SysBusDevice parent_obj;
@@ -184,6 +198,7 @@ struct BCM2835CprmanState {
CprmanPllState plls[CPRMAN_NUM_PLL];
CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL];
CprmanClockMuxState clock_muxes[CPRMAN_NUM_CLOCK_MUX];
+ CprmanDsi0HsckMuxState dsi0hsck_mux;
=20
uint32_t regs[CPRMAN_NUM_REGS];
uint32_t xosc_freq;
diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/b=
cm2835_cprman_internals.h
index 0305448bbc7..a6e799075f7 100644
--- a/include/hw/misc/bcm2835_cprman_internals.h
+++ b/include/hw/misc/bcm2835_cprman_internals.h
@@ -15,6 +15,7 @@
#define TYPE_CPRMAN_PLL "bcm2835-cprman-pll"
#define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel"
#define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux"
+#define TYPE_CPRMAN_DSI0HSCK_MUX "bcm2835-cprman-dsi0hsck-mux"
=20
DECLARE_INSTANCE_CHECKER(CprmanPllState, CPRMAN_PLL,
TYPE_CPRMAN_PLL)
@@ -22,6 +23,8 @@ DECLARE_INSTANCE_CHECKER(CprmanPllChannelState, CPRMAN_PL=
L_CHANNEL,
TYPE_CPRMAN_PLL_CHANNEL)
DECLARE_INSTANCE_CHECKER(CprmanClockMuxState, CPRMAN_CLOCK_MUX,
TYPE_CPRMAN_CLOCK_MUX)
+DECLARE_INSTANCE_CHECKER(CprmanDsi0HsckMuxState, CPRMAN_DSI0HSCK_MUX,
+ TYPE_CPRMAN_DSI0HSCK_MUX)
=20
/* Register map */
=20
@@ -223,6 +226,9 @@ REG32(CM_LOCK, 0x114)
FIELD(CM_LOCK, FLOCKB, 9, 1)
FIELD(CM_LOCK, FLOCKA, 8, 1)
=20
+REG32(CM_DSI0HSCK, 0x120)
+ FIELD(CM_DSI0HSCK, SELPLLD, 0, 1)
+
/*
* This field is common to all registers. Each register write value must m=
atch
* the CPRMAN_PASSWORD magic value in its 8 MSB.
diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
index 919a55aa23f..7a7401963d5 100644
--- a/hw/misc/bcm2835_cprman.c
+++ b/hw/misc/bcm2835_cprman.c
@@ -339,6 +339,58 @@ static const TypeInfo cprman_clock_mux_info =3D {
};
=20
=20
+/* DSI0HSCK mux */
+
+static void dsi0hsck_mux_update(CprmanDsi0HsckMuxState *s)
+{
+ bool src_is_plld =3D FIELD_EX32(*s->reg_cm, CM_DSI0HSCK, SELPLLD);
+ Clock *src =3D src_is_plld ? s->plld_in : s->plla_in;
+
+ clock_update(s->out, clock_get(src));
+}
+
+static void dsi0hsck_mux_in_update(void *opaque)
+{
+ dsi0hsck_mux_update(CPRMAN_DSI0HSCK_MUX(opaque));
+}
+
+static void dsi0hsck_mux_init(Object *obj)
+{
+ CprmanDsi0HsckMuxState *s =3D CPRMAN_DSI0HSCK_MUX(obj);
+ DeviceState *dev =3D DEVICE(obj);
+
+ s->plla_in =3D qdev_init_clock_in(dev, "plla-in", dsi0hsck_mux_in_upda=
te, s);
+ s->plld_in =3D qdev_init_clock_in(dev, "plld-in", dsi0hsck_mux_in_upda=
te, s);
+ s->out =3D qdev_init_clock_out(DEVICE(s), "out");
+}
+
+static const VMStateDescription dsi0hsck_mux_vmstate =3D {
+ .name =3D TYPE_CPRMAN_DSI0HSCK_MUX,
+ .version_id =3D 1,
+ .minimum_version_id =3D 1,
+ .fields =3D (VMStateField[]) {
+ VMSTATE_CLOCK(plla_in, CprmanDsi0HsckMuxState),
+ VMSTATE_CLOCK(plld_in, CprmanDsi0HsckMuxState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void dsi0hsck_mux_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+
+ dc->vmsd =3D &dsi0hsck_mux_vmstate;
+}
+
+static const TypeInfo cprman_dsi0hsck_mux_info =3D {
+ .name =3D TYPE_CPRMAN_DSI0HSCK_MUX,
+ .parent =3D TYPE_DEVICE,
+ .instance_size =3D sizeof(CprmanDsi0HsckMuxState),
+ .class_init =3D dsi0hsck_mux_class_init,
+ .instance_init =3D dsi0hsck_mux_init,
+};
+
+
/* CPRMAN "top level" model */
=20
static uint32_t get_cm_lock(const BCM2835CprmanState *s)
@@ -501,6 +553,10 @@ static void cprman_write(void *opaque, hwaddr offset,
case R_CM_EMMC2CTL ... R_CM_EMMC2DIV:
update_mux_from_cm(s, idx);
break;
+
+ case R_CM_DSI0HSCK:
+ dsi0hsck_mux_update(&s->dsi0hsck_mux);
+ break;
}
}
=20
@@ -540,6 +596,8 @@ static void cprman_reset(DeviceState *dev)
device_cold_reset(DEVICE(&s->channels[i]));
}
=20
+ device_cold_reset(DEVICE(&s->dsi0hsck_mux));
+
for (i =3D 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
device_cold_reset(DEVICE(&s->clock_muxes[i]));
}
@@ -565,6 +623,10 @@ static void cprman_init(Object *obj)
set_pll_channel_init_info(s, &s->channels[i], i);
}
=20
+ object_initialize_child(obj, "dsi0hsck-mux",
+ &s->dsi0hsck_mux, TYPE_CPRMAN_DSI0HSCK_MUX);
+ s->dsi0hsck_mux.reg_cm =3D &s->regs[R_CM_DSI0HSCK];
+
for (i =3D 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
char *alias;
=20
@@ -612,7 +674,7 @@ static void connect_mux_sources(BCM2835CprmanState *s,
if (mapping =3D=3D CPRMAN_CLOCK_SRC_FORCE_GROUND) {
src =3D s->gnd;
} else if (mapping =3D=3D CPRMAN_CLOCK_SRC_DSI0HSCK) {
- src =3D s->gnd; /* TODO */
+ src =3D s->dsi0hsck_mux.out;
} else if (i < CPRMAN_CLOCK_SRC_PLLA) {
src =3D CLK_SRC_MAPPING[i];
} else {
@@ -650,6 +712,15 @@ static void cprman_realize(DeviceState *dev, Error **e=
rrp)
}
}
=20
+ clock_set_source(s->dsi0hsck_mux.plla_in,
+ s->channels[CPRMAN_PLLA_CHANNEL_DSI0].out);
+ clock_set_source(s->dsi0hsck_mux.plld_in,
+ s->channels[CPRMAN_PLLD_CHANNEL_DSI0].out);
+
+ if (!qdev_realize(DEVICE(&s->dsi0hsck_mux), NULL, errp)) {
+ return;
+ }
+
for (i =3D 0; i < CPRMAN_NUM_CLOCK_MUX; i++) {
CprmanClockMuxState *clock_mux =3D &s->clock_muxes[i];
=20
@@ -700,6 +771,7 @@ static void cprman_register_types(void)
type_register_static(&cprman_pll_info);
type_register_static(&cprman_pll_channel_info);
type_register_static(&cprman_clock_mux_info);
+ type_register_static(&cprman_dsi0hsck_mux_info);
}
=20
type_init(cprman_register_types);
--=20
2.20.1