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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 40/48] hw/misc/bcm2835_cprman: implement clock mux behaviour
Date: Tue, 27 Oct 2020 11:44:30 +0000
Message-Id: <20201027114438.17662-41-peter.maydell@linaro.org>
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From: Luc Michel <luc@lmichel.fr>
A clock mux can be configured to select one of its 10 sources through
the CM_CTL register. It also embeds yet another clock divider, composed
of an integer part and a fractional part. The number of bits of each
part is mux dependent.
Tested-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Signed-off-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/bcm2835_cprman.c | 53 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
index b22170f3bc2..919a55aa23f 100644
--- a/hw/misc/bcm2835_cprman.c
+++ b/hw/misc/bcm2835_cprman.c
@@ -231,15 +231,66 @@ static const TypeInfo cprman_pll_channel_info =3D {
=20
/* clock mux */
=20
+static bool clock_mux_is_enabled(CprmanClockMuxState *mux)
+{
+ return FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, ENABLE);
+}
+
static void clock_mux_update(CprmanClockMuxState *mux)
{
- clock_update(mux->out, 0);
+ uint64_t freq;
+ uint32_t div, src =3D FIELD_EX32(*mux->reg_ctl, CM_CLOCKx_CTL, SRC);
+ bool enabled =3D clock_mux_is_enabled(mux);
+
+ *mux->reg_ctl =3D FIELD_DP32(*mux->reg_ctl, CM_CLOCKx_CTL, BUSY, enabl=
ed);
+
+ if (!enabled) {
+ clock_update(mux->out, 0);
+ return;
+ }
+
+ freq =3D clock_get_hz(mux->srcs[src]);
+
+ if (mux->int_bits =3D=3D 0 && mux->frac_bits =3D=3D 0) {
+ clock_update_hz(mux->out, freq);
+ return;
+ }
+
+ /*
+ * The divider has an integer and a fractional part. The size of each =
part
+ * varies with the muxes (int_bits and frac_bits). Both parts are
+ * concatenated, with the integer part always starting at bit 12.
+ *
+ * 31 12 11 0
+ * ------------------------------
+ * CM_DIV | | int | frac | |
+ * ------------------------------
+ * <-----> <------>
+ * int_bits frac_bits
+ */
+ div =3D extract32(*mux->reg_div,
+ R_CM_CLOCKx_DIV_FRAC_LENGTH - mux->frac_bits,
+ mux->int_bits + mux->frac_bits);
+
+ if (!div) {
+ clock_update(mux->out, 0);
+ return;
+ }
+
+ freq =3D muldiv64(freq, 1 << mux->frac_bits, div);
+
+ clock_update_hz(mux->out, freq);
}
=20
static void clock_mux_src_update(void *opaque)
{
CprmanClockMuxState **backref =3D opaque;
CprmanClockMuxState *s =3D *backref;
+ CprmanClockMuxSource src =3D backref - s->backref;
+
+ if (FIELD_EX32(*s->reg_ctl, CM_CLOCKx_CTL, SRC) !=3D src) {
+ return;
+ }
=20
clock_mux_update(s);
}
--=20
2.20.1