From nobody Sun May 12 22:25:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1603764140; cv=none; d=zohomail.com; s=zohoarc; b=UFrUwBvc7Ly+mn2JI4MRDig5MYpu2NoGb+/sQoH4X6/cMOpNLE7I9x3JnRKSfpBBGkmLmD2xrSnZCXlj15pS0RP/OYMNsbKcxWJTwPxBRjVDkKlQkcahyDsPZSwXzpW+YL0PvTDJRx6nOBkQSiVNUY0dPbYCIMR/ri45eQOkf7o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603764140; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=9Mf50yUYZ/3jVFW39UF6D+RCMZ4zdnsGlzvSeR7Kt0A=; b=GksAMfGSwE0gyjMRH98DU9nBT/YUzXeKhch5uyEwxnB+3xdYbvYYBmnVKIdk46LQmsBCXiMbx1/Wsn427lCD4GVf4AQuuRU5AejEyCdRwVtPOJXjVdwP777E+DmxDjzMjHSWwCoM+lUr3i0SaggkK5QcLtIYRZToAyTtJHtA1kM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1603764140735224.0803972736485; Mon, 26 Oct 2020 19:02:20 -0700 (PDT) Received: from localhost ([::1]:48488 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kXEJX-0003sB-Gw for importer@patchew.org; Mon, 26 Oct 2020 22:02:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58022) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kXEGs-0002PY-8p for qemu-devel@nongnu.org; Mon, 26 Oct 2020 21:59:34 -0400 Received: from mail-qv1-xf33.google.com ([2607:f8b0:4864:20::f33]:33192) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kXEGp-0000zR-2n for qemu-devel@nongnu.org; Mon, 26 Oct 2020 21:59:33 -0400 Received: by mail-qv1-xf33.google.com with SMTP id w9so3541qvj.0 for ; Mon, 26 Oct 2020 18:59:30 -0700 (PDT) Received: from localhost.localdomain ([142.114.143.244]) by smtp.googlemail.com with ESMTPSA id 61sm19317qta.19.2020.10.26.18.59.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2020 18:59:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9Mf50yUYZ/3jVFW39UF6D+RCMZ4zdnsGlzvSeR7Kt0A=; b=PAOeORKDy0rMbcYpXJLCvX19pOlH605V9Q/CZqVvhnbA4+MOnsdpDkpfhuAC7FY1V/ GZ6J2IBd3EWHdcEHCYUixvXMfLzfCDI6QXtvupeZb2DWY2XgOCgZMj/Z/kKjn0vOiZh8 vh12ZyYQM4zO41X++PdzxNOAj5m6r2wpigTKR9gKLdkfubufKLGXHIcO8gCT7i6dFHdW SYBcv1AKIM8p24plUQQJNbIeMxKW3HPGpWWrI0aSZHR9/CJ7YBEuv+PSNG3JdQc1RtRK mfL6AJ4tyPTmPRjACJKVjjLrH4IlvDhJuXAU3zR6dZl73ZhIfoiWy2ykoi8BoVfhJ8Ka aJHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9Mf50yUYZ/3jVFW39UF6D+RCMZ4zdnsGlzvSeR7Kt0A=; b=TWP8EKAB1dmLEYIKdMf+9ezyCEKKhP1ohRtPvYMcgrs871bRt5hCT3qJkggcgILgF0 fhfWfasTZRnERJYS59FnKnKAIIwJnosnmUxS1pqcMFqBkiUUgu6dhM78srzgSeN2+W9o cHeFrzpp+VZUm6vc9ARlMsb/Xe6vbkfditkuklx5kwOhcX/3NMh0IyBy8u+So0NVGV6W XdnaDSRDVXh2U4dvV/U3fURXSbtHKbyM6TEkyDMzRGstbYVZ4CNMkebwTjdNvcg55dfu /sTKybwqbb0ocvNsruTqhCNX97RhVLDzK1SEcg1/3O4hKXrq9qmTby7JtjlZCIoGw4H8 JqzA== X-Gm-Message-State: AOAM530Rl605a/qn18NQOUzS/bdEaSAVoNLPOIgayhssQ9kXZifD7gPn pxB9BIJMR70dsf2+sRfhfAq7Mw== X-Google-Smtp-Source: ABdhPJwftJ3Zxkr6hR3j2emMOwSyTy8I+PDINjb9udGtKyB8N5c3cU62zAJBIz6lv/0bWE2Oe0Md8Q== X-Received: by 2002:a05:6214:180d:: with SMTP id o13mr155976qvw.34.1603763970120; Mon, 26 Oct 2020 18:59:30 -0700 (PDT) From: Shashi Mallela To: peter.maydell@linaro.org, leif@nuviainc.com, rad@semihalf.com Subject: [PATCH v8 1/2] hw/watchdog: Implement SBSA watchdog device Date: Mon, 26 Oct 2020 21:59:26 -0400 Message-Id: <20201027015927.29495-2-shashi.mallela@linaro.org> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20201027015927.29495-1-shashi.mallela@linaro.org> References: <20201027015927.29495-1-shashi.mallela@linaro.org> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f33; envelope-from=shashi.mallela@linaro.org; helo=mail-qv1-xf33.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Generic watchdog device model implementation as per ARM SBSA v6.0 Signed-off-by: Shashi Mallela --- hw/arm/Kconfig | 1 + hw/watchdog/Kconfig | 3 + hw/watchdog/meson.build | 1 + hw/watchdog/sbsa_gwdt.c | 293 ++++++++++++++++++++++++++++++++ include/hw/watchdog/sbsa_gwdt.h | 79 +++++++++ 5 files changed, 377 insertions(+) create mode 100644 hw/watchdog/sbsa_gwdt.c create mode 100644 include/hw/watchdog/sbsa_gwdt.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7d040827af4f..0ef9e3c1d5f5 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -211,6 +211,7 @@ config SBSA_REF select PL031 # RTC select PL061 # GPIO select USB_EHCI_SYSBUS + select WDT_SBSA =20 config SABRELITE bool diff --git a/hw/watchdog/Kconfig b/hw/watchdog/Kconfig index 293209b291d6..66e1d029e32e 100644 --- a/hw/watchdog/Kconfig +++ b/hw/watchdog/Kconfig @@ -17,3 +17,6 @@ config WDT_DIAG288 =20 config WDT_IMX2 bool + +config WDT_SBSA + bool diff --git a/hw/watchdog/meson.build b/hw/watchdog/meson.build index 9b8725e64288..054c403dea7c 100644 --- a/hw/watchdog/meson.build +++ b/hw/watchdog/meson.build @@ -5,3 +5,4 @@ softmmu_ss.add(when: 'CONFIG_WDT_IB700', if_true: files('wd= t_ib700.c')) softmmu_ss.add(when: 'CONFIG_WDT_DIAG288', if_true: files('wdt_diag288.c')) softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('wdt_aspeed.c')) softmmu_ss.add(when: 'CONFIG_WDT_IMX2', if_true: files('wdt_imx2.c')) +softmmu_ss.add(when: 'CONFIG_WDT_SBSA', if_true: files('sbsa_gwdt.c')) diff --git a/hw/watchdog/sbsa_gwdt.c b/hw/watchdog/sbsa_gwdt.c new file mode 100644 index 000000000000..d0998f8489cb --- /dev/null +++ b/hw/watchdog/sbsa_gwdt.c @@ -0,0 +1,293 @@ +/* + * Generic watchdog device model for SBSA + * + * The watchdog device has been implemented as revision 1 variant of + * the ARM SBSA specification v6.0 + * (https://developer.arm.com/documentation/den0029/d?lang=3Den) + * + * Copyright Linaro.org 2020 + * + * Authors: + * Shashi Mallela + * + * This work is licensed under the terms of the GNU GPL, version 2 or (at = your + * option) any later version. See the COPYING file in the top-level direc= tory. + * + */ + +#include "qemu/osdep.h" +#include "sysemu/reset.h" +#include "sysemu/watchdog.h" +#include "hw/watchdog/sbsa_gwdt.h" +#include "qemu/timer.h" +#include "migration/vmstate.h" +#include "qemu/log.h" +#include "qemu/module.h" + +static WatchdogTimerModel model =3D { + .wdt_name =3D TYPE_WDT_SBSA, + .wdt_description =3D "SBSA-compliant generic watchdog device", +}; + +static const VMStateDescription vmstate_sbsa_gwdt =3D { + .name =3D "sbsa-gwdt", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_TIMER_PTR(timer, SBSA_GWDTState), + VMSTATE_UINT32(wcs, SBSA_GWDTState), + VMSTATE_UINT32(worl, SBSA_GWDTState), + VMSTATE_UINT32(woru, SBSA_GWDTState), + VMSTATE_UINT32(wcvl, SBSA_GWDTState), + VMSTATE_UINT32(wcvu, SBSA_GWDTState), + VMSTATE_END_OF_LIST() + } +}; + +typedef enum WdtRefreshType { + EXPLICIT_REFRESH =3D 0, + TIMEOUT_REFRESH =3D 1, +} WdtRefreshType; + +static uint64_t sbsa_gwdt_rread(void *opaque, hwaddr addr, unsigned int si= ze) +{ + SBSA_GWDTState *s =3D SBSA_GWDT(opaque); + uint32_t ret =3D 0; + + switch (addr) { + case SBSA_GWDT_WRR: + /* watch refresh read has no effect and returns 0 */ + ret =3D 0; + break; + case SBSA_GWDT_W_IIDR: + ret =3D s->id; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "bad address in refresh frame read = :" + " 0x%x\n", (int)addr); + } + return ret; +} + +static uint64_t sbsa_gwdt_read(void *opaque, hwaddr addr, unsigned int siz= e) +{ + SBSA_GWDTState *s =3D SBSA_GWDT(opaque); + uint32_t ret =3D 0; + + switch (addr) { + case SBSA_GWDT_WCS: + ret =3D s->wcs; + break; + case SBSA_GWDT_WOR: + ret =3D s->worl; + break; + case SBSA_GWDT_WORU: + ret =3D s->woru; + break; + case SBSA_GWDT_WCV: + ret =3D s->wcvl; + break; + case SBSA_GWDT_WCVU: + ret =3D s->wcvu; + break; + case SBSA_GWDT_W_IIDR: + ret =3D s->id; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "bad address in control frame read = :" + " 0x%x\n", (int)addr); + } + return ret; +} + +static void sbsa_gwdt_update_timer(SBSA_GWDTState *s, WdtRefreshType rtype) +{ + uint64_t timeout =3D 0; + + timer_del(s->timer); + + if (s->wcs & SBSA_GWDT_WCS_EN) { + /* + * Extract the upper 16 bits from woru & 32 bits from worl + * registers to construct the 48 bit offset value + */ + timeout =3D s->woru; + timeout <<=3D 32; + timeout |=3D s->worl; + timeout =3D muldiv64(timeout, NANOSECONDS_PER_SECOND, SBSA_TIMER_F= REQ); + timeout +=3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + + if ((rtype =3D=3D EXPLICIT_REFRESH) || ((rtype =3D=3D TIMEOUT_REFR= ESH) && + (!(s->wcs & SBSA_GWDT_WCS_WS0)))) { + /* store the current timeout value into compare registers */ + s->wcvu =3D timeout >> 32; + s->wcvl =3D timeout; + } + timer_mod(s->timer, timeout); + } +} + +static void sbsa_gwdt_rwrite(void *opaque, hwaddr offset, uint64_t data, + unsigned size) { + SBSA_GWDTState *s =3D SBSA_GWDT(opaque); + + if (offset =3D=3D SBSA_GWDT_WRR) { + s->wcs &=3D ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1); + + sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "bad address in refresh frame write= :" + " 0x%x\n", (int)offset); + } +} + +static void sbsa_gwdt_write(void *opaque, hwaddr offset, uint64_t data, + unsigned size) { + SBSA_GWDTState *s =3D SBSA_GWDT(opaque); + + switch (offset) { + case SBSA_GWDT_WCS: + s->wcs =3D data & SBSA_GWDT_WCS_EN; + qemu_set_irq(s->irq, 0); + sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH); + break; + + case SBSA_GWDT_WOR: + s->worl =3D data; + s->wcs &=3D ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1); + qemu_set_irq(s->irq, 0); + sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH); + break; + + case SBSA_GWDT_WORU: + s->woru =3D data & SBSA_GWDT_WOR_MASK; + s->wcs &=3D ~(SBSA_GWDT_WCS_WS0 | SBSA_GWDT_WCS_WS1); + qemu_set_irq(s->irq, 0); + sbsa_gwdt_update_timer(s, EXPLICIT_REFRESH); + break; + + case SBSA_GWDT_WCV: + s->wcvl =3D data; + break; + + case SBSA_GWDT_WCVU: + s->wcvu =3D data; + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "bad address in control frame write= :" + " 0x%x\n", (int)offset); + } + return; +} + +static void wdt_sbsa_gwdt_reset(DeviceState *dev) +{ + SBSA_GWDTState *s =3D SBSA_GWDT(dev); + + timer_del(s->timer); + + s->wcs =3D 0; + s->wcvl =3D 0; + s->wcvu =3D 0; + s->worl =3D 0; + s->woru =3D 0; + s->id =3D SBSA_GWDT_ID; +} + +static void sbsa_gwdt_timer_sysinterrupt(void *opaque) +{ + SBSA_GWDTState *s =3D SBSA_GWDT(opaque); + + if (!(s->wcs & SBSA_GWDT_WCS_WS0)) { + s->wcs |=3D SBSA_GWDT_WCS_WS0; + sbsa_gwdt_update_timer(s, TIMEOUT_REFRESH); + qemu_set_irq(s->irq, 1); + } else { + s->wcs |=3D SBSA_GWDT_WCS_WS1; + qemu_log_mask(CPU_LOG_RESET, "Watchdog timer expired.\n"); + /* + * Reset the watchdog only if the guest gets notified about + * expiry. watchdog_perform_action() may temporarily relinquish + * the BQL; reset before triggering the action to avoid races with + * sbsa_gwdt instructions. + */ + switch (get_watchdog_action()) { + case WATCHDOG_ACTION_DEBUG: + case WATCHDOG_ACTION_NONE: + case WATCHDOG_ACTION_PAUSE: + break; + default: + wdt_sbsa_gwdt_reset(DEVICE(s)); + } + watchdog_perform_action(); + } +} + +static const MemoryRegionOps sbsa_gwdt_rops =3D { + .read =3D sbsa_gwdt_rread, + .write =3D sbsa_gwdt_rwrite, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .valid.unaligned =3D false, +}; + +static const MemoryRegionOps sbsa_gwdt_ops =3D { + .read =3D sbsa_gwdt_read, + .write =3D sbsa_gwdt_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .valid.unaligned =3D false, +}; + +static void wdt_sbsa_gwdt_realize(DeviceState *dev, Error **errp) +{ + SBSA_GWDTState *s =3D SBSA_GWDT(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + + memory_region_init_io(&s->rmmio, OBJECT(dev), + &sbsa_gwdt_rops, s, + "sbsa_gwdt.refresh", + SBSA_GWDT_RMMIO_SIZE); + + memory_region_init_io(&s->cmmio, OBJECT(dev), + &sbsa_gwdt_ops, s, + "sbsa_gwdt.control", + SBSA_GWDT_CMMIO_SIZE); + + sysbus_init_mmio(sbd, &s->rmmio); + sysbus_init_mmio(sbd, &s->cmmio); + + sysbus_init_irq(sbd, &s->irq); + + s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, sbsa_gwdt_timer_sysinter= rupt, + dev); +} + +static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D wdt_sbsa_gwdt_realize; + dc->reset =3D wdt_sbsa_gwdt_reset; + dc->hotpluggable =3D false; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + dc->vmsd =3D &vmstate_sbsa_gwdt; +} + +static const TypeInfo wdt_sbsa_gwdt_info =3D { + .class_init =3D wdt_sbsa_gwdt_class_init, + .parent =3D TYPE_SYS_BUS_DEVICE, + .name =3D TYPE_WDT_SBSA, + .instance_size =3D sizeof(SBSA_GWDTState), +}; + +static void wdt_sbsa_gwdt_register_types(void) +{ + watchdog_add_model(&model); + type_register_static(&wdt_sbsa_gwdt_info); +} + +type_init(wdt_sbsa_gwdt_register_types) diff --git a/include/hw/watchdog/sbsa_gwdt.h b/include/hw/watchdog/sbsa_gwd= t.h new file mode 100644 index 000000000000..70b137de3016 --- /dev/null +++ b/include/hw/watchdog/sbsa_gwdt.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2020 Linaro Limited + * + * Authors: + * Shashi Mallela + * + * This work is licensed under the terms of the GNU GPL, version 2 or (at = your + * option) any later version. See the COPYING file in the top-level direc= tory. + * + */ + +#ifndef WDT_SBSA_GWDT_H +#define WDT_SBSA_GWDT_H + +#include "qemu/bitops.h" +#include "hw/sysbus.h" +#include "hw/irq.h" + +#define TYPE_WDT_SBSA "sbsa_gwdt" +#define SBSA_GWDT(obj) \ + OBJECT_CHECK(SBSA_GWDTState, (obj), TYPE_WDT_SBSA) +#define SBSA_GWDT_CLASS(klass) \ + OBJECT_CLASS_CHECK(SBSA_GWDTClass, (klass), TYPE_WDT_SBSA) +#define SBSA_GWDT_GET_CLASS(obj) \ + OBJECT_GET_CLASS(SBSA_GWDTClass, (obj), TYPE_WDT_SBSA) + +/* SBSA Generic Watchdog register definitions */ +/* refresh frame */ +#define SBSA_GWDT_WRR 0x000 + +/* control frame */ +#define SBSA_GWDT_WCS 0x000 +#define SBSA_GWDT_WOR 0x008 +#define SBSA_GWDT_WORU 0x00C +#define SBSA_GWDT_WCV 0x010 +#define SBSA_GWDT_WCVU 0x014 + +/* Watchdog Interface Identification Register */ +#define SBSA_GWDT_W_IIDR 0xFCC + +/* Watchdog Control and Status Register Bits */ +#define SBSA_GWDT_WCS_EN BIT(0) +#define SBSA_GWDT_WCS_WS0 BIT(1) +#define SBSA_GWDT_WCS_WS1 BIT(2) + +#define SBSA_GWDT_WOR_MASK 0x0000FFFF + +/* + * Watchdog Interface Identification Register definition + * considering JEP106 code for ARM in Bits [11:0] + */ +#define SBSA_GWDT_ID 0x1043B + +/* 2 Separate memory regions for each of refresh & control register frames= */ +#define SBSA_GWDT_RMMIO_SIZE 0x1000 +#define SBSA_GWDT_CMMIO_SIZE 0x1000 + +#define SBSA_TIMER_FREQ 62500000 /* Hz */ + +typedef struct SBSA_GWDTState { + /* */ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion rmmio; + MemoryRegion cmmio; + qemu_irq irq; + + QEMUTimer *timer; + + uint32_t id; + uint32_t wcs; + uint32_t worl; + uint32_t woru; + uint32_t wcvl; + uint32_t wcvu; +} SBSA_GWDTState; + +#endif /* WDT_SBSA_GWDT_H */ --=20 2.18.4 From nobody Sun May 12 22:25:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1603764268; cv=none; d=zohomail.com; s=zohoarc; b=Rh2mFbcSC1r44jgvAAHFs2ce7ZKLtOAZC+yBH9c3nblPBP4LUALe4xYxEtk1+C2mmYQOufJyomWx7dwqTgTnHGbcXOJyvFYWZcrqsfI78fWNBnhoA4v1tjSM58Ynfgt9FegOKa9SeztSnrCO4gF5gKooGd2u5iaqe9tnZmxhFB4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603764268; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::742; envelope-from=shashi.mallela@linaro.org; helo=mail-qk1-x742.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Included the newly implemented SBSA generic watchdog device model into SBSA platform Signed-off-by: Shashi Mallela Reviewed-by: Peter Maydell --- hw/arm/sbsa-ref.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 01863510d0f5..7d9e180c0db0 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -40,6 +40,7 @@ #include "hw/qdev-properties.h" #include "hw/usb.h" #include "hw/char/pl011.h" +#include "hw/watchdog/sbsa_gwdt.h" #include "net/net.h" #include "qom/object.h" =20 @@ -64,6 +65,9 @@ enum { SBSA_GIC_DIST, SBSA_GIC_REDIST, SBSA_SECURE_EC, + SBSA_GWDT, + SBSA_GWDT_REFRESH, + SBSA_GWDT_CONTROL, SBSA_SMMU, SBSA_UART, SBSA_RTC, @@ -104,6 +108,8 @@ static const MemMapEntry sbsa_ref_memmap[] =3D { [SBSA_GIC_DIST] =3D { 0x40060000, 0x00010000 }, [SBSA_GIC_REDIST] =3D { 0x40080000, 0x04000000 }, [SBSA_SECURE_EC] =3D { 0x50000000, 0x00001000 }, + [SBSA_GWDT_REFRESH] =3D { 0x50010000, 0x00001000 }, + [SBSA_GWDT_CONTROL] =3D { 0x50011000, 0x00001000 }, [SBSA_UART] =3D { 0x60000000, 0x00001000 }, [SBSA_RTC] =3D { 0x60010000, 0x00001000 }, [SBSA_GPIO] =3D { 0x60020000, 0x00001000 }, @@ -134,6 +140,7 @@ static const int sbsa_ref_irqmap[] =3D { [SBSA_AHCI] =3D 10, [SBSA_EHCI] =3D 11, [SBSA_SMMU] =3D 12, /* ... to 15 */ + [SBSA_GWDT] =3D 16, }; =20 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) @@ -448,6 +455,20 @@ static void create_rtc(const SBSAMachineState *sms) sysbus_create_simple("pl031", base, qdev_get_gpio_in(sms->gic, irq)); } =20 +static void create_wdt(const SBSAMachineState *sms) +{ + hwaddr rbase =3D sbsa_ref_memmap[SBSA_GWDT_REFRESH].base; + hwaddr cbase =3D sbsa_ref_memmap[SBSA_GWDT_CONTROL].base; + DeviceState *dev =3D qdev_new(TYPE_WDT_SBSA); + SysBusDevice *s =3D SYS_BUS_DEVICE(dev); + int irq =3D sbsa_ref_irqmap[SBSA_GWDT]; + + sysbus_realize_and_unref(s, &error_fatal); + sysbus_mmio_map(s, 0, rbase); + sysbus_mmio_map(s, 1, cbase); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(sms->gic, irq)); +} + static DeviceState *gpio_key_dev; static void sbsa_ref_powerdown_req(Notifier *n, void *opaque) { @@ -731,6 +752,8 @@ static void sbsa_ref_init(MachineState *machine) =20 create_rtc(sms); =20 + create_wdt(sms); + create_gpio(sms); =20 create_ahci(sms); --=20 2.18.4