From nobody Fri Sep 5 22:26:36 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1603707061; cv=none; d=zohomail.com; s=zohoarc; b=eVscxFmTupQHyl1Nm1c1t1GOFDaFSzXHh4Wf0KQha67fciKeDzQi+k3Npm2c3QxzJ/TRP2T4bEYLIXyA8rJLoQiwvv0HSFVjyzXYia+tu4yYlW6Dj9+cGTeLMY8FYmQZEFQxv+FQWZpamd+eg2W4BNt1S5Gxhy2xTxO2WhvDF2c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603707061; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=ost2cOMGRJVru/pzvO+4OND1a7zyzspU2BgErPSvgd8=; b=BE4BON73AeC4Z+M3xrBwOODWxQI/yFaFqOzmNWv1KDCH846lv++vmhTT5tKqo5/Z237GZPwF0It1sDJ6rEQuOK4jmp2P7tT8yqB+c1pXrnwqYWmtRWraTq1BKkvFK++f04XT0lmh8l+YkHwv+ryby0LQr535G//WgF3RiSvthWQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1603707061313805.3098741165757; Mon, 26 Oct 2020 03:11:01 -0700 (PDT) Received: from localhost ([::1]:41404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kWzSu-0007eX-4m for importer@patchew.org; Mon, 26 Oct 2020 06:11:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38882) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kWzPC-0002eU-P1 for qemu-devel@nongnu.org; Mon, 26 Oct 2020 06:07:12 -0400 Received: from us-smtp-delivery-124.mimecast.com ([63.128.21.124]:35071) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kWzP2-0006gO-RX for qemu-devel@nongnu.org; Mon, 26 Oct 2020 06:07:10 -0400 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-340-Z-cmIUCSP2q54TDkPC28bQ-1; Mon, 26 Oct 2020 06:06:56 -0400 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 13898107ACF7; Mon, 26 Oct 2020 10:06:55 +0000 (UTC) Received: from thuth.com (ovpn-112-104.ams2.redhat.com [10.36.112.104]) by smtp.corp.redhat.com (Postfix) with ESMTP id 05D908B84A; Mon, 26 Oct 2020 10:06:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1603706819; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:content-type:content-type:in-reply-to:in-reply-to: references:references; bh=ost2cOMGRJVru/pzvO+4OND1a7zyzspU2BgErPSvgd8=; b=N6WUtvLjbFtwx1sNq4rRq/YK7WoDPBEUG+jELbllAKJopkA6G6A2TTnQtk7pvoM2BGG48r l2SG/aBNe/8Uo7jaZgz8KuhKeqvpYUZ1apbvGqEYYk/cInvjWTAwrecCcCA3RSdLS8LKFU 3/sTlQcdq3LOzt3e5OfmEbNmH44rUZs= X-MC-Unique: Z-cmIUCSP2q54TDkPC28bQ-1 From: Thomas Huth To: qemu-devel@nongnu.org, Peter Maydell Subject: [PULL 12/31] fuzz: Add DMA support to the generic-fuzzer Date: Mon, 26 Oct 2020 11:06:13 +0100 Message-Id: <20201026100632.212530-13-thuth@redhat.com> In-Reply-To: <20201026100632.212530-1-thuth@redhat.com> References: <20201026100632.212530-1-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=thuth@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.128.21.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/25 21:03:19 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexander Bulekov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @redhat.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Alexander Bulekov When a virtual-device tries to access some buffer in memory over DMA, we add call-backs into the fuzzer(next commit). The fuzzer checks verifies that the DMA request maps to a physical RAM address and fills the memory with fuzzer-provided data. The patterns that we use to fill this memory are specified using add_dma_pattern and clear_dma_patterns operations. Signed-off-by: Alexander Bulekov Reviewed-by: Darren Kenny Message-Id: <20201023150746.107063-5-alxndr@bu.edu> [thuth: Reformatted one comment according to the QEMU coding style] Signed-off-by: Thomas Huth --- include/exec/memory.h | 7 + tests/qtest/fuzz/generic_fuzz.c | 230 ++++++++++++++++++++++++++++++++ 2 files changed, 237 insertions(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 042918dd16..93d27bff26 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -42,6 +42,13 @@ typedef struct IOMMUMemoryRegionClass IOMMUMemoryRegionC= lass; DECLARE_OBJ_CHECKERS(IOMMUMemoryRegion, IOMMUMemoryRegionClass, IOMMU_MEMORY_REGION, TYPE_IOMMU_MEMORY_REGION) =20 +#ifdef CONFIG_FUZZ +void fuzz_dma_read_cb(size_t addr, + size_t len, + MemoryRegion *mr, + bool is_write); +#endif + extern bool global_dirty_log; =20 typedef struct MemoryRegionOps MemoryRegionOps; diff --git a/tests/qtest/fuzz/generic_fuzz.c b/tests/qtest/fuzz/generic_fuz= z.c index 483d41fb2c..62a94de9dd 100644 --- a/tests/qtest/fuzz/generic_fuzz.c +++ b/tests/qtest/fuzz/generic_fuzz.c @@ -25,6 +25,7 @@ #include "exec/address-spaces.h" #include "hw/qdev-core.h" #include "hw/pci/pci.h" +#include "hw/boards.h" =20 /* * SEPARATOR is used to separate "operations" in the fuzz input @@ -38,12 +39,16 @@ enum cmds { OP_WRITE, OP_PCI_READ, OP_PCI_WRITE, + OP_ADD_DMA_PATTERN, + OP_CLEAR_DMA_PATTERNS, OP_CLOCK_STEP, }; =20 #define DEFAULT_TIMEOUT_US 100000 #define USEC_IN_SEC 1000000000 =20 +#define MAX_DMA_FILL_SIZE 0x10000 + #define PCI_HOST_BRIDGE_CFG 0xcf8 #define PCI_HOST_BRIDGE_DATA 0xcfc =20 @@ -56,6 +61,24 @@ static useconds_t timeout =3D DEFAULT_TIMEOUT_US; =20 static bool qtest_log_enabled; =20 +/* + * A pattern used to populate a DMA region or perform a memwrite. This is + * useful for e.g. populating tables of unique addresses. + * Example {.index =3D 1; .stride =3D 2; .len =3D 3; .data =3D "\x00\x01\x= 02"} + * Renders as: 00 01 02 00 03 02 00 05 02 00 07 02 ... + */ +typedef struct { + uint8_t index; /* Index of a byte to increment by stride */ + uint8_t stride; /* Increment each index'th byte by this amount */ + size_t len; + const uint8_t *data; +} pattern; + +/* Avoid filling the same DMA region between MMIO/PIO commands ? */ +static bool avoid_double_fetches; + +static QTestState *qts_global; /* Need a global for the DMA callback */ + /* * List of memory regions that are children of QOM objects specified by the * user for fuzzing. @@ -84,6 +107,169 @@ static int get_io_address_cb(Int128 start, Int128 size, return 0; } =20 +/* + * List of dma regions populated since the last fuzzing command. Used to e= nsure + * that we only write to each DMA address once, to avoid race conditions w= hen + * building reproducers. + */ +static GArray *dma_regions; + +static GArray *dma_patterns; +static int dma_pattern_index; + +/* + * Allocate a block of memory and populate it with a pattern. + */ +static void *pattern_alloc(pattern p, size_t len) +{ + int i; + uint8_t *buf =3D g_malloc(len); + uint8_t sum =3D 0; + + for (i =3D 0; i < len; ++i) { + buf[i] =3D p.data[i % p.len]; + if ((i % p.len) =3D=3D p.index) { + buf[i] +=3D sum; + sum +=3D p.stride; + } + } + return buf; +} + +static int memory_access_size(MemoryRegion *mr, unsigned l, hwaddr addr) +{ + unsigned access_size_max =3D mr->ops->valid.max_access_size; + + /* + * Regions are assumed to support 1-4 byte accesses unless + * otherwise specified. + */ + if (access_size_max =3D=3D 0) { + access_size_max =3D 4; + } + + /* Bound the maximum access by the alignment of the address. */ + if (!mr->ops->impl.unaligned) { + unsigned align_size_max =3D addr & -addr; + if (align_size_max !=3D 0 && align_size_max < access_size_max) { + access_size_max =3D align_size_max; + } + } + + /* Don't attempt accesses larger than the maximum. */ + if (l > access_size_max) { + l =3D access_size_max; + } + l =3D pow2floor(l); + + return l; +} + +/* + * Call-back for functions that perform DMA reads from guest memory. Confi= rm + * that the region has not already been populated since the last loop in + * generic_fuzz(), avoiding potential race-conditions, which we don't have + * a good way for reproducing right now. + */ +void fuzz_dma_read_cb(size_t addr, size_t len, MemoryRegion *mr, bool is_w= rite) +{ + /* Are we in the generic-fuzzer or are we using another fuzz-target? */ + if (!qts_global) { + return; + } + + /* + * Return immediately if: + * - We have no DMA patterns defined + * - The length of the DMA read request is zero + * - The DMA read is hitting an MR other than the machine's main RAM + * - The DMA request is not a read (what happens for a address_space_m= ap + * with is_write=3DTrue? Can the device use the same pointer to do r= eads?) + * - The DMA request hits past the bounds of our RAM + */ + if (dma_patterns->len =3D=3D 0 + || len =3D=3D 0 + /* || mr !=3D MACHINE(qdev_get_machine())->ram */ + || is_write + || addr > current_machine->ram_size) { + return; + } + + /* + * If we overlap with any existing dma_regions, split the range and on= ly + * populate the non-overlapping parts. + */ + address_range region; + bool double_fetch =3D false; + for (int i =3D 0; + i < dma_regions->len && (avoid_double_fetches || qtest_log_enable= d); + ++i) { + region =3D g_array_index(dma_regions, address_range, i); + if (addr < region.addr + region.size && addr + len > region.addr) { + double_fetch =3D true; + if (addr < region.addr + && avoid_double_fetches) { + fuzz_dma_read_cb(addr, region.addr - addr, mr, is_write); + } + if (addr + len > region.addr + region.size + && avoid_double_fetches) { + fuzz_dma_read_cb(region.addr + region.size, + addr + len - (region.addr + region.size), mr, is_w= rite); + } + return; + } + } + + /* Cap the length of the DMA access to something reasonable */ + len =3D MIN(len, MAX_DMA_FILL_SIZE); + + address_range ar =3D {addr, len}; + g_array_append_val(dma_regions, ar); + pattern p =3D g_array_index(dma_patterns, pattern, dma_pattern_index); + void *buf =3D pattern_alloc(p, ar.size); + hwaddr l, addr1; + MemoryRegion *mr1; + uint8_t *ram_ptr; + while (len > 0) { + l =3D len; + mr1 =3D address_space_translate(first_cpu->as, + addr, &addr1, &l, true, + MEMTXATTRS_UNSPECIFIED); + + if (!(memory_region_is_ram(mr1) || + memory_region_is_romd(mr1))) { + l =3D memory_access_size(mr1, l, addr1); + } else { + /* ROM/RAM case */ + ram_ptr =3D qemu_map_ram_ptr(mr1->ram_block, addr1); + memcpy(ram_ptr, buf, l); + break; + } + len -=3D l; + buf +=3D l; + addr +=3D l; + + } + if (qtest_log_enabled) { + /* + * With QTEST_LOG, use a normal, slow QTest memwrite. Prefix the l= og + * that will be written by qtest.c with a DMA tag, so we can reord= er + * the resulting QTest trace so the DMA fills precede the last PIO= /MMIO + * command. + */ + fprintf(stderr, "[DMA] "); + if (double_fetch) { + fprintf(stderr, "[DOUBLE-FETCH] "); + } + fflush(stderr); + } + qtest_memwrite(qts_global, ar.addr, buf, ar.size); + g_free(buf); + + /* Increment the index of the pattern for the next DMA access */ + dma_pattern_index =3D (dma_pattern_index + 1) % dma_patterns->len; +} + /* * Here we want to convert a fuzzer-provided [io-region-index, offset] to * a physical address. To do this, we iterate over all of the matched @@ -349,6 +535,35 @@ static void op_pci_write(QTestState *s, const unsigned= char * data, size_t len) } } =20 +static void op_add_dma_pattern(QTestState *s, + const unsigned char *data, size_t len) +{ + struct { + /* + * index and stride can be used to increment the index-th byte of = the + * pattern by the value stride, for each loop of the pattern. + */ + uint8_t index; + uint8_t stride; + } a; + + if (len < sizeof(a) + 1) { + return; + } + memcpy(&a, data, sizeof(a)); + pattern p =3D {a.index, a.stride, len - sizeof(a), data + sizeof(a)}; + p.index =3D a.index % p.len; + g_array_append_val(dma_patterns, p); + return; +} + +static void op_clear_dma_patterns(QTestState *s, + const unsigned char *data, size_t len) +{ + g_array_set_size(dma_patterns, 0); + dma_pattern_index =3D 0; +} + static void op_clock_step(QTestState *s, const unsigned char *data, size_t= len) { qtest_clock_step_next(s); @@ -409,6 +624,8 @@ static void generic_fuzz(QTestState *s, const unsigned = char *Data, size_t Size) [OP_WRITE] =3D op_write, [OP_PCI_READ] =3D op_pci_read, [OP_PCI_WRITE] =3D op_pci_write, + [OP_ADD_DMA_PATTERN] =3D op_add_dma_pattern, + [OP_CLEAR_DMA_PATTERNS] =3D op_clear_dma_patterns, [OP_CLOCK_STEP] =3D op_clock_step, }; const unsigned char *cmd =3D Data; @@ -438,6 +655,8 @@ static void generic_fuzz(QTestState *s, const unsigned = char *Data, size_t Size) setitimer(ITIMER_VIRTUAL, &timer, NULL); } =20 + op_clear_dma_patterns(s, NULL, 0); + while (cmd && Size) { /* Get the length until the next command or end of input */ nextcmd =3D memmem(cmd, Size, SEPARATOR, strlen(SEPARATOR)); @@ -454,6 +673,7 @@ static void generic_fuzz(QTestState *s, const unsigned = char *Data, size_t Size) /* Advance to the next command */ cmd =3D nextcmd ? nextcmd + sizeof(SEPARATOR) - 1 : nextcmd; Size =3D Size - (cmd_len + sizeof(SEPARATOR) - 1); + g_array_set_size(dma_regions, 0); } _Exit(0); } else { @@ -468,6 +688,9 @@ static void usage(void) printf("QEMU_FUZZ_ARGS=3D the command line arguments passed to qemu\n"= ); printf("QEMU_FUZZ_OBJECTS=3D " "a space separated list of QOM type names for objects to fuzz\= n"); + printf("Optionally: QEMU_AVOID_DOUBLE_FETCH=3D " + "Try to avoid racy DMA double fetch bugs? %d by default\n", + avoid_double_fetches); printf("Optionally: QEMU_FUZZ_TIMEOUT=3D Specify a custom timeout (us)= . " "0 to disable. %d by default\n", timeout); exit(0); @@ -539,9 +762,16 @@ static void generic_pre_fuzz(QTestState *s) if (getenv("QTEST_LOG")) { qtest_log_enabled =3D 1; } + if (getenv("QEMU_AVOID_DOUBLE_FETCH")) { + avoid_double_fetches =3D 1; + } if (getenv("QEMU_FUZZ_TIMEOUT")) { timeout =3D g_ascii_strtoll(getenv("QEMU_FUZZ_TIMEOUT"), NULL, 0); } + qts_global =3D s; + + dma_regions =3D g_array_new(false, false, sizeof(address_range)); + dma_patterns =3D g_array_new(false, false, sizeof(pattern)); =20 fuzzable_memoryregions =3D g_hash_table_new(NULL, NULL); fuzzable_pci_devices =3D g_ptr_array_new(); --=20 2.18.2