From nobody Mon Feb 9 05:33:42 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.65 as permitted sender) client-ip=209.85.221.65; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f65.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1603572664; cv=none; d=zohomail.com; s=zohoarc; b=B8PU/Ws63mi7o73/pFebTPMwO63FWM5xQNVcEonCMkqpWLz8MK7S+LywMNQ0gOtpi9OK6TYNj8ujL6FPzKRI7q/Vno0qXe45W4pt26PTqQ/2RhpMuiHwnFeCyvXdGKYjvXzYPiIkBZmAYURu6OWnk/OA+NEVgLQ+4Tx7eN7zUpY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603572664; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:MIME-Version:Message-ID:Sender:Subject:To; bh=Mf8jmSVivEDI3YZ0cQwYjT/GiMph8yQ9KvEBl9GSzXY=; b=LUtvltcwf1/5hA0le4BPsmuA+M9FKEpy9IlOLZEztCPfes0p+RzYbPTbGT20HfEU4gqdeBWAyONCqzl6gqZLHLSdlrYicIg/3UtbFtLQMqdTvMIn0f0/IcaBwENvOJDkiE7DIgsPHYvSl2GuZy5JVyNtHOEU8aDUf/yluU4jXwA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.65 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by mx.zohomail.com with SMTPS id 1603572664882474.98746331880636; Sat, 24 Oct 2020 13:51:04 -0700 (PDT) Received: by mail-wr1-f65.google.com with SMTP id n18so7085280wrs.5 for ; Sat, 24 Oct 2020 13:51:04 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (237.red-88-18-140.staticip.rima-tde.net. [88.18.140.237]) by smtp.gmail.com with ESMTPSA id e11sm12925120wrj.75.2020.10.24.13.51.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Oct 2020 13:51:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Mf8jmSVivEDI3YZ0cQwYjT/GiMph8yQ9KvEBl9GSzXY=; b=JG+2MJ0ozIaoUvxSW64FhLwdw8QBxovfloRtB4zzDZ9zoBi3mi4A1sIcYkbiFM2gCT 2xQmU1AFOSyGvIvFXJPW6/IYg92dEz4v1q4HtRAqONxOTMljfwtB6n2K9xFP3w0FbHLB ddp2/0OlLf8oCZimhG4k0xiXgkL+1vw2zIayNvjeZ473Wjl9F4lpCFcqU2DGZI8r0Lgx vy8Sxf4Tffk7so0vygZ1cqwKfJhdsm6PQnyLAE41H8nkr5gs1446xFt2oN1J6iNv2axH OQyqTvw87diA7BHztW/AoBLjbSBsNzY72Vw8uPk4Bb2h9jZYvk72RbRQ/p0/f8nl4IPh 1tXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=Mf8jmSVivEDI3YZ0cQwYjT/GiMph8yQ9KvEBl9GSzXY=; b=WmsDT3v9yrGpFYVheRCa4cG9OtYZPOAdCSkTGL0f3IUAH4BslYg1trg1TdAwse3+nq nuBxLaEv19Xyy3mGBjBUpCZU6S2hxAan/EyJCozNmku2843VaRlm79b9k0U29HC7SAb+ 94VUXFWWoLHLu6ltJqxZzME9ip2+Sf3UWcXgrzK+Hway5V4OMg8b/K9Flx/Ej44mUsG0 bF3HdKRzCYqMdSiE21T25PuPzzT1yfOkZ0idHpqz+JBuWm5D6DntMgP9r9GEf3vSMH12 Yq0z61n6y80jkKWPmTQhYBop6gt5Qc+wgsMry7NNwaN8SEu5SgfgsDKF3/tbl2wye7lj unUw== X-Gm-Message-State: AOAM532a73ws6SGA0qHGjuFTs9WRq7TEB08REd1OlrS2DBAhaefKfxOk hY2SNw158xeAV5IkGNPqJAPyG/DPwuM= X-Google-Smtp-Source: ABdhPJxvr5DvipLfkYUxbmsPi4nhIi/phGIF/v7fX/O1iZ4A/vfmBdWAjshtPjn8sdAThhfpc4LCBQ== X-Received: by 2002:adf:e849:: with SMTP id d9mr10118800wrn.25.1603572662949; Sat, 24 Oct 2020 13:51:02 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Mark Cave-Ayland , qemu-devel@nongnu.org Cc: 1892540@bugs.launchpad.net, Gerd Hoffmann , Michael Lorenz , Laurent Vivier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andreas Gustafsson , "Michael S . Tsirkin" , Richard Henderson Subject: [PATCH v3] hw/display/tcx: Allow 64-bit accesses to framebuffer stippler and blitter Date: Sat, 24 Oct 2020 22:51:00 +0200 Message-Id: <20201024205100.3623006-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The S24/TCX datasheet is listed as "Unable to locate" on [1]. However the NetBSD revision 1.32 of the driver introduced 64-bit accesses to the stippler and blitter [2]. It is safe to assume these memory regions are 64-bit accessible. QEMU implementation is 32-bit, so fill the 'impl' fields. Michael Lorenz (author of the NetBSD code [2]) provided us with more information in [3]: > IIRC the real hardware *requires* 64bit accesses for stipple and > blitter operations to work. For stipples you write a 64bit word into > STIP space, the address defines where in the framebuffer you want to > draw, the data contain a 32bit bitmask, foreground colour and a ROP. > BLIT space works similarly, the 64bit word contains an offset were to > read pixels from, and how many you want to copy. > > One more thing since there seems to be some confusion - 64bit accesses > on the framebuffer are fine as well. TCX/S24 is *not* an SBus device, > even though its node says it is. > S24 is a card that plugs into a special slot on the SS5 mainboard, > which is shared with an SBus slot and looks a lot like a horizontal > UPA slot. Both S24 and TCX are accessed through the Micro/TurboSPARC's > AFX bus which is 64bit wide and intended for graphics. > Early FFB docs even mentioned connecting to both AFX and UPA, > no idea if that was ever realized in hardware though. [1] http://web.archive.org/web/20111209011516/http://wikis.sun.com/display/= FOSSdocs/Home [2] http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/dev/sbus/tcx.c.diff?r1=3D1.= 31&r2=3D1.32 [3] https://www.mail-archive.com/qemu-devel@nongnu.org/msg734928.html Reported-by: Andreas Gustafsson Buglink: https://bugs.launchpad.net/bugs/1892540 Fixes: 55d7bfe2293 ("tcx: Implement hardware acceleration") Tested-by: Michael S. Tsirkin Reviewed-by: Richard Henderson Tested-by: Andreas Gustafsson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Since v2: - added Michael's memories - added R-b/T-b tags Since v1: - added missing uncommitted staged changes... (tcx_blit_ops) --- hw/display/tcx.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/hw/display/tcx.c b/hw/display/tcx.c index c9d5e45cd1f..878ecc8c506 100644 --- a/hw/display/tcx.c +++ b/hw/display/tcx.c @@ -549,20 +549,28 @@ static const MemoryRegionOps tcx_stip_ops =3D { .read =3D tcx_stip_readl, .write =3D tcx_stip_writel, .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid =3D { + .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 8, + }, }; =20 static const MemoryRegionOps tcx_rstip_ops =3D { .read =3D tcx_stip_readl, .write =3D tcx_rstip_writel, .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid =3D { + .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 8, + }, }; =20 static uint64_t tcx_blit_readl(void *opaque, hwaddr addr, @@ -651,10 +659,14 @@ static const MemoryRegionOps tcx_rblit_ops =3D { .read =3D tcx_blit_readl, .write =3D tcx_rblit_writel, .endianness =3D DEVICE_NATIVE_ENDIAN, - .valid =3D { + .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 8, + }, }; =20 static void tcx_invalidate_cursor_position(TCXState *s) --=20 2.26.2