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a=rsa-sha256; c=simple/simple; d=keithp.com; s=mail; t=1603489513; bh=o9FSc9IqFdAVRsYbyKeZduUk4m6kW9TmMdzQOXB/0Xw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k9S7XY+mRROGKh0fL8fe1LvmiDJYV/JvgnIhsm9BUlZQrZX3G8HDYfXnoCsXhpzqs vg8kpxl1mOPEtKfFoktaz2NAcf1OmCnNcRtd0qi+uDEBRIt8W4yDBvmCMz7x/iA/fS W8mRS3D+AER0gl15B11H35mXTpAkyVdfQPOzXaMjUZfuu4HyGHOiMzIS1ygIQXqD7D JiqqGvznboHoV/sXvZl2xVlqGepWfnlHcM/d0myX5nJpXW0+J0gYRMQcsNe3j08WUn +ynd+zhDBHculPpLAjbN3v6GTsmZIELKQ/J7BNMeDMYfjmZSbb+7hSdBDBFLFmrKor UI+35QtBlpiUA== To: qemu-devel@nongnu.org Cc: Keith Packard Subject: [PATCH 1/2] riscv: Add sifive test device to sifive_e target Date: Fri, 23 Oct 2020 14:45:05 -0700 Message-Id: <20201023214506.917601-2-keithp@keithp.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201023214506.917601-1-keithp@keithp.com> References: <20201023214506.917601-1-keithp@keithp.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.227.221.253; envelope-from=keithp@keithp.com; helo=elaine.keithp.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/23 17:45:14 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Keith Packard From: Keith Packard via X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The SiFive test device provides a mechanism for terminating the qemu instance from the emulated system. This patch adds that device to the sifive_e target. Signed-off-by: Keith Packard --- hw/riscv/sifive_e.c | 4 ++++ include/hw/riscv/sifive_e.h | 1 + 2 files changed, 5 insertions(+) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index fcfac16816..417e3a5409 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -11,6 +11,7 @@ * 3) PRCI (Power, Reset, Clock, Interrupt) * 4) Registers emulated as RAM: AON, GPIO, QSPI, PWM * 5) Flash memory emulated as RAM + * 6) TEST (Test device) * * The Mask ROM reset vector jumps to the flash payload at 0x2040_0000. * The OTP ROM and Flash boot code will be emulated in a future version. @@ -45,6 +46,7 @@ #include "hw/intc/sifive_clint.h" #include "hw/intc/sifive_plic.h" #include "hw/misc/sifive_e_prci.h" +#include "hw/misc/sifive_test.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/sysemu.h" @@ -57,6 +59,7 @@ static const struct MemmapEntry { [SIFIVE_E_DEV_DEBUG] =3D { 0x0, 0x1000 }, [SIFIVE_E_DEV_MROM] =3D { 0x1000, 0x2000 }, [SIFIVE_E_DEV_OTP] =3D { 0x20000, 0x2000 }, + [SIFIVE_E_DEV_TEST] =3D { 0x100000, 0x1000 }, [SIFIVE_E_DEV_CLINT] =3D { 0x2000000, 0x10000 }, [SIFIVE_E_DEV_PLIC] =3D { 0xc000000, 0x4000000 }, [SIFIVE_E_DEV_AON] =3D { 0x10000000, 0x8000 }, @@ -216,6 +219,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Erro= r **errp) memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, SIFIVE_CLINT_TIMEBASE_FREQ, false); + sifive_test_create(memmap[SIFIVE_E_DEV_TEST].base); create_unimplemented_device("riscv.sifive.e.aon", memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size); sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 83604da805..92bab6d0d4 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -56,6 +56,7 @@ enum { SIFIVE_E_DEV_DEBUG, SIFIVE_E_DEV_MROM, SIFIVE_E_DEV_OTP, + SIFIVE_E_DEV_TEST, SIFIVE_E_DEV_CLINT, SIFIVE_E_DEV_PLIC, SIFIVE_E_DEV_AON, --=20 2.28.0