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charset="utf-8" From: Klaus Jensen Add support for reporting the Deallocated or Unwritten Logical Block Error (DULBE). Rely on the block status flags reported by the block layer and consider any block with the BDRV_BLOCK_ZERO flag to be deallocated. Multiple factors affect when a Write Zeroes command result in deallocation of blocks. * the underlying file system block size * the blockdev format * the 'discard' and 'logical_block_size' parameters format | discard | wz (512b) wz (4kb) wz (64kb) --------------------------------------------------- qcow2 ignore n n y qcow2 unmap n n y raw ignore n y y raw unmap n y y So, this works best with an image in raw format and 4kb LBAs, since holes can then be punched on a per-block basis (this assumes a file system with a 4kb block size, YMMV). A qcow2 image, uses a cluster size of 64kb by default and blocks will only be marked deallocated if a full cluster is zeroed or discarded. However, this *is* consistent with the spec since Write Zeroes "should" deallocate the block if the Deallocate attribute is set and "may" deallocate if the Deallocate attribute is not set. Thus, we always try to deallocate (the BDRV_REQ_MAY_UNMAP flag is always set). Signed-off-by: Klaus Jensen Reviewed-by: Keith Busch --- hw/block/nvme-ns.h | 4 +++ include/block/nvme.h | 5 +++ hw/block/nvme-ns.c | 8 +++-- hw/block/nvme.c | 80 ++++++++++++++++++++++++++++++++++++++++++- hw/block/trace-events | 4 +++ 5 files changed, 97 insertions(+), 4 deletions(-) diff --git a/hw/block/nvme-ns.h b/hw/block/nvme-ns.h index 83734f4606e1..44bf6271b744 100644 --- a/hw/block/nvme-ns.h +++ b/hw/block/nvme-ns.h @@ -31,6 +31,10 @@ typedef struct NvmeNamespace { NvmeIdNs id_ns; =20 NvmeNamespaceParams params; + + struct { + uint32_t err_rec; + } features; } NvmeNamespace; =20 static inline uint32_t nvme_nsid(NvmeNamespace *ns) diff --git a/include/block/nvme.h b/include/block/nvme.h index 8a46d9cf015f..966c3bb304bd 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -687,6 +687,7 @@ enum NvmeStatusCodes { NVME_E2E_REF_ERROR =3D 0x0284, NVME_CMP_FAILURE =3D 0x0285, NVME_ACCESS_DENIED =3D 0x0286, + NVME_DULB =3D 0x0287, NVME_MORE =3D 0x2000, NVME_DNR =3D 0x4000, NVME_NO_COMPLETE =3D 0xffff, @@ -903,6 +904,9 @@ enum NvmeIdCtrlLpa { #define NVME_AEC_NS_ATTR(aec) ((aec >> 8) & 0x1) #define NVME_AEC_FW_ACTIVATION(aec) ((aec >> 9) & 0x1) =20 +#define NVME_ERR_REC_TLER(err_rec) (err_rec & 0xffff) +#define NVME_ERR_REC_DULBE(err_rec) (err_rec & 0x10000) + enum NvmeFeatureIds { NVME_ARBITRATION =3D 0x1, NVME_POWER_MANAGEMENT =3D 0x2, @@ -1023,6 +1027,7 @@ enum NvmeNsIdentifierType { =20 =20 #define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1)) +#define NVME_ID_NS_NSFEAT_DULBE(nsfeat) ((nsfeat >> 2) & 0x1) #define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1) #define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf)) #define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1) diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c index 31c80cdf5b5f..f1cc734c60f5 100644 --- a/hw/block/nvme-ns.c +++ b/hw/block/nvme-ns.c @@ -33,9 +33,7 @@ static void nvme_ns_init(NvmeNamespace *ns) NvmeIdNs *id_ns =3D &ns->id_ns; int lba_index =3D NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas); =20 - if (blk_get_flags(ns->blkconf.blk) & BDRV_O_UNMAP) { - ns->id_ns.dlfeat =3D 0x9; - } + ns->id_ns.dlfeat =3D 0x9; =20 id_ns->lbaf[lba_index].ds =3D 31 - clz32(ns->blkconf.logical_block_siz= e); =20 @@ -44,6 +42,9 @@ static void nvme_ns_init(NvmeNamespace *ns) /* no thin provisioning */ id_ns->ncap =3D id_ns->nsze; id_ns->nuse =3D id_ns->ncap; + + /* support DULBE */ + id_ns->nsfeat |=3D 0x4; } =20 static int nvme_ns_init_blk(NvmeCtrl *n, NvmeNamespace *ns, Error **errp) @@ -92,6 +93,7 @@ int nvme_ns_setup(NvmeCtrl *n, NvmeNamespace *ns, Error *= *errp) } =20 nvme_ns_init(ns); + if (nvme_register_namespace(n, ns, errp)) { return -1; } diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 2896bb49b9c0..1758cfed965c 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -105,6 +105,7 @@ static const bool nvme_feature_support[NVME_FID_MAX] = =3D { =20 static const uint32_t nvme_feature_cap[NVME_FID_MAX] =3D { [NVME_TEMPERATURE_THRESHOLD] =3D NVME_FEAT_CAP_CHANGE, + [NVME_ERROR_RECOVERY] =3D NVME_FEAT_CAP_CHANGE | NVME_FEAT_C= AP_NS, [NVME_VOLATILE_WRITE_CACHE] =3D NVME_FEAT_CAP_CHANGE, [NVME_NUMBER_OF_QUEUES] =3D NVME_FEAT_CAP_CHANGE, [NVME_ASYNCHRONOUS_EVENT_CONF] =3D NVME_FEAT_CAP_CHANGE, @@ -878,6 +879,41 @@ static inline uint16_t nvme_check_bounds(NvmeCtrl *n, = NvmeNamespace *ns, return NVME_SUCCESS; } =20 +static uint16_t nvme_check_dulbe(NvmeNamespace *ns, uint64_t slba, + uint32_t nlb) +{ + BlockDriverState *bs =3D blk_bs(ns->blkconf.blk); + + int64_t pnum =3D 0, bytes =3D nvme_l2b(ns, nlb); + int64_t offset =3D nvme_l2b(ns, slba); + bool zeroed; + int ret; + + /* + * `pnum` holds the number of bytes after offset that shares the same + * allocation status as the byte at offset. If `pnum` is different from + * `bytes`, we should check the allocation status of the next range and + * continue this until all bytes have been checked. + */ + do { + bytes -=3D pnum; + + ret =3D bdrv_block_status(bs, offset, bytes, &pnum, NULL, NULL); + + zeroed =3D !!(ret & BDRV_BLOCK_ZERO); + + trace_pci_nvme_block_status(offset, bytes, pnum, ret, zeroed); + + if (zeroed) { + return NVME_DULB; + } + + offset +=3D pnum; + } while (pnum !=3D bytes); + + return NVME_SUCCESS; +} + static void nvme_rw_cb(void *opaque, int ret) { NvmeRequest *req =3D opaque; @@ -985,6 +1021,15 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeRequest *req) goto invalid; } =20 + if (acct =3D=3D BLOCK_ACCT_READ) { + if (NVME_ERR_REC_DULBE(ns->features.err_rec)) { + status =3D nvme_check_dulbe(ns, slba, nlb); + if (status) { + goto invalid; + } + } + } + status =3D nvme_map_dptr(n, data_size, req); if (status) { goto invalid; @@ -1630,6 +1675,7 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeReq= uest *req) uint8_t fid =3D NVME_GETSETFEAT_FID(dw10); NvmeGetFeatureSelect sel =3D NVME_GETFEAT_SELECT(dw10); uint16_t iv; + NvmeNamespace *ns; =20 static const uint32_t nvme_feature_default[NVME_FID_MAX] =3D { [NVME_ARBITRATION] =3D NVME_ARB_AB_NOLIMIT, @@ -1692,6 +1738,18 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeRe= quest *req) } =20 return NVME_INVALID_FIELD | NVME_DNR; + case NVME_ERROR_RECOVERY: + if (!nvme_nsid_valid(n, nsid)) { + return NVME_INVALID_NSID | NVME_DNR; + } + + ns =3D nvme_ns(n, nsid); + if (unlikely(!ns)) { + return NVME_INVALID_FIELD | NVME_DNR; + } + + result =3D ns->features.err_rec; + goto out; case NVME_VOLATILE_WRITE_CACHE: result =3D n->features.vwc; trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); @@ -1764,7 +1822,7 @@ static uint16_t nvme_set_feature_timestamp(NvmeCtrl *= n, NvmeRequest *req) =20 static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRequest *req) { - NvmeNamespace *ns; + NvmeNamespace *ns =3D NULL; =20 NvmeCmd *cmd =3D &req->cmd; uint32_t dw10 =3D le32_to_cpu(cmd->cdw10); @@ -1831,6 +1889,26 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRe= quest *req) NVME_LOG_SMART_INFO); } =20 + break; + case NVME_ERROR_RECOVERY: + if (nsid =3D=3D NVME_NSID_BROADCAST) { + for (int i =3D 1; i <=3D n->num_namespaces; i++) { + ns =3D nvme_ns(n, i); + + if (!ns) { + continue; + } + + if (NVME_ID_NS_NSFEAT_DULBE(ns->id_ns.nsfeat)) { + ns->features.err_rec =3D dw11; + } + } + + break; + } + + assert(ns); + ns->features.err_rec =3D dw11; break; case NVME_VOLATILE_WRITE_CACHE: n->features.vwc =3D dw11 & 0x1; diff --git a/hw/block/trace-events b/hw/block/trace-events index c1537e3ac0b0..1ffe0b3f76b5 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -43,6 +43,10 @@ pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t = opcode, const char *opna pci_nvme_rw(uint16_t cid, const char *verb, uint32_t nsid, uint32_t nlb, u= int64_t count, uint64_t lba) "cid %"PRIu16" opname '%s' nsid %"PRIu32" nlb = %"PRIu32" count %"PRIu64" lba 0x%"PRIx64"" pci_nvme_rw_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'" pci_nvme_write_zeroes(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t= nlb) "cid %"PRIu16" nsid %"PRIu32" slba %"PRIu64" nlb %"PRIu32"" +pci_nvme_block_status(int64_t offset, int64_t bytes, int64_t pnum, int ret= , bool zeroed) "offset %"PRId64" bytes %"PRId64" pnum %"PRId64" ret 0x%x ze= roed %d" +pci_nvme_dsm(uint16_t cid, uint32_t nsid, uint32_t nr, uint32_t attr) "cid= %"PRIu16" nsid %"PRIu32" nr %"PRIu32" attr 0x%"PRIx32"" +pci_nvme_dsm_deallocate(uint16_t cid, uint32_t nsid, uint64_t slba, uint32= _t nlb) "cid %"PRIu16" nsid %"PRIu32" slba %"PRIu64" nlb %"PRIu32"" +pci_nvme_aio_discard_cb(uint16_t cid) "cid %"PRIu16"" pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t q= size, uint16_t qflags) "create submission queue, addr=3D0x%"PRIx64", sqid= =3D%"PRIu16", cqid=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRIu16"" pci_nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t= size, uint16_t qflags, int ien) "create completion queue, addr=3D0x%"PRIx6= 4", cqid=3D%"PRIu16", vector=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRI= u16", ien=3D%d" pci_nvme_del_sq(uint16_t qid) "deleting submission queue sqid=3D%"PRIu16"" --=20 2.28.0 From nobody Sat May 18 15:08:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.21; envelope-from=its@irrelevant.dk; helo=wout5-smtp.messagingengine.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/21 18:17:42 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Add support for the Dataset Management command and the Deallocate attribute. Deallocation results in discards being sent to the underlying block device. Whether of not the blocks are actually deallocated is affected by the same factors as Write Zeroes (see previous commit). format | discard | dsm (512b) dsm (4kb) dsm (64kb) ------------------------------------------------------ qcow2 ignore n n n qcow2 unmap n n y raw ignore n n n raw unmap n y y Again, a raw format and 4kb LBAs are preferable. See NVM Express 1.3d, Section 6.7 ("Dataset Management command"). Signed-off-by: Klaus Jensen --- hw/block/nvme.h | 2 + hw/block/nvme.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 100 insertions(+), 1 deletion(-) diff --git a/hw/block/nvme.h b/hw/block/nvme.h index e080a2318a50..574333caa3f9 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -28,6 +28,7 @@ typedef struct NvmeRequest { struct NvmeNamespace *ns; BlockAIOCB *aiocb; uint16_t status; + void *opaque; NvmeCqe cqe; NvmeCmd cmd; BlockAcctCookie acct; @@ -60,6 +61,7 @@ static inline const char *nvme_io_opc_str(uint8_t opc) case NVME_CMD_WRITE: return "NVME_NVM_CMD_WRITE"; case NVME_CMD_READ: return "NVME_NVM_CMD_READ"; case NVME_CMD_WRITE_ZEROES: return "NVME_NVM_CMD_WRITE_ZEROES"; + case NVME_CMD_DSM: return "NVME_NVM_CMD_DSM"; default: return "NVME_NVM_CMD_UNKNOWN"; } } diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 1758cfed965c..a6dd8ae8e220 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -959,6 +959,101 @@ static void nvme_rw_cb(void *opaque, int ret) nvme_enqueue_req_completion(nvme_cq(req), req); } =20 +static void nvme_aio_discard_cb(void *opaque, int ret) +{ + NvmeRequest *req =3D opaque; + int *discards =3D req->opaque; + + trace_pci_nvme_aio_discard_cb(nvme_cid(req)); + + if (ret) { + req->status =3D NVME_INTERNAL_DEV_ERROR; + trace_pci_nvme_err_aio(nvme_cid(req), strerror(ret), + req->status); + } + + if (discards && --(*discards) > 0) { + return; + } + + g_free(req->opaque); + req->opaque =3D NULL; + + nvme_enqueue_req_completion(nvme_cq(req), req); +} + +static uint16_t nvme_dsm(NvmeCtrl *n, NvmeRequest *req) +{ + NvmeNamespace *ns =3D req->ns; + NvmeDsmCmd *dsm =3D (NvmeDsmCmd *) &req->cmd; + NvmeDsmRange *range =3D NULL; + int *discards =3D NULL; + + uint32_t attr =3D le32_to_cpu(dsm->attributes); + uint32_t nr =3D (le32_to_cpu(dsm->nr) & 0xff) + 1; + + uint16_t status =3D NVME_SUCCESS; + + trace_pci_nvme_dsm(nvme_cid(req), nvme_nsid(ns), nr, attr); + + if (attr & NVME_DSMGMT_AD) { + int64_t offset; + size_t len; + + range =3D g_new(NvmeDsmRange, nr); + + status =3D nvme_dma(n, (uint8_t *)range, nr * sizeof(NvmeDsmRange), + DMA_DIRECTION_TO_DEVICE, req); + if (status) { + goto out; + } + + discards =3D g_new0(int, 1); + req->opaque =3D discards; + + for (int i =3D 0; i < nr; i++) { + uint64_t slba =3D le64_to_cpu(range[i].slba); + uint32_t nlb =3D le32_to_cpu(range[i].nlb); + + if (nvme_check_bounds(n, ns, slba, nlb)) { + trace_pci_nvme_err_invalid_lba_range(slba, nlb, + ns->id_ns.nsze); + continue; + } + + trace_pci_nvme_dsm_deallocate(nvme_cid(req), nvme_nsid(ns), sl= ba, + nlb); + + offset =3D nvme_l2b(ns, slba); + len =3D nvme_l2b(ns, nlb); + + while (len) { + size_t bytes =3D MIN(BDRV_REQUEST_MAX_BYTES, len); + + blk_aio_pdiscard(ns->blkconf.blk, offset, bytes, + nvme_aio_discard_cb, req); + + (*discards)++; + + offset +=3D bytes; + len -=3D bytes; + } + } + + if (*discards) { + status =3D NVME_NO_COMPLETE; + } else { + g_free(discards); + req->opaque =3D NULL; + } + } + +out: + g_free(range); + + return status; +} + static uint16_t nvme_flush(NvmeCtrl *n, NvmeRequest *req) { block_acct_start(blk_get_stats(req->ns->blkconf.blk), &req->acct, 0, @@ -1088,6 +1183,8 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest = *req) case NVME_CMD_WRITE: case NVME_CMD_READ: return nvme_rw(n, req); + case NVME_CMD_DSM: + return nvme_dsm(n, req); default: trace_pci_nvme_err_invalid_opc(req->cmd.opcode); return NVME_INVALID_OPCODE | NVME_DNR; @@ -2810,7 +2907,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pc= i_dev) id->cqes =3D (0x4 << 4) | 0x4; id->nn =3D cpu_to_le32(n->num_namespaces); id->oncs =3D cpu_to_le16(NVME_ONCS_WRITE_ZEROES | NVME_ONCS_TIMESTAMP | - NVME_ONCS_FEATURES); + NVME_ONCS_FEATURES | NVME_ONCS_DSM); =20 id->vwc =3D 0x1; id->sgls =3D cpu_to_le32(NVME_CTRL_SGLS_SUPPORT_NO_ALIGN | --=20 2.28.0