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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Rather than compare the fractions before subtracting, do the subtract and examine the result, possibly negating it. Looking toward re-using addsub_floats(N**2) for the addition stage of muladd_floats(N), this will important because of the longer fraction sizes. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 4 ++++ fpu/softfloat-parts.c.inc | 32 ++++++++++++++++++++------------ 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 294c573fb9..bf808a1b74 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -732,6 +732,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatPa= rts b, FloatParts c, #define EQ0(P) ((P) =3D=3D 0) #define EQ(P1, P2) ((P1) =3D=3D (P2)) #define GEU(P1, P2) ((P1) >=3D (P2)) +#define NEG(P) (-(P)) #define OR(P1, P2) ((P1) | (P2)) #define SHL(P, C) ((P) << (C)) #define SHR(P, C) ((P) >> (C)) @@ -755,6 +756,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatPa= rts b, FloatParts c, #undef EQ0 #undef EQ #undef GEU +#undef NEG #undef OR #undef SHL #undef SHR @@ -777,6 +779,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatPa= rts b, FloatParts c, #define EQ0(P) (!int128_nz(P)) #define EQ(P1, P2) int128_eq(P1, P2) #define GEU(P1, P2) int128_geu(P1, P2) +#define NEG(P) int128_neg(P) #define OR(P1, P2) int128_or(P1, P2) #define SHL(P, C) int128_shl(P, C) #define SHR(P, C) int128_shr(P, C) @@ -801,6 +804,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatPa= rts b, FloatParts c, #undef EQ0 #undef EQ #undef GEU +#undef NEG #undef SHL #undef SHR #undef SHR_JAM diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc index d2b6454903..9762cf8b66 100644 --- a/fpu/softfloat-parts.c.inc +++ b/fpu/softfloat-parts.c.inc @@ -254,29 +254,37 @@ FUNC(addsub_floats)(PARTS_TYPE a, PARTS_TYPE b, /* Subtraction */ =20 if (likely(ab_mask =3D=3D float_cmask_normal)) { - if (a.exp > b.exp || (a.exp =3D=3D b.exp && GEU(a.frac, b.frac= ))) { - b.frac =3D SHR_JAM(b.frac, a.exp - b.exp); + int shift, diff_exp =3D a.exp - b.exp; + + if (diff_exp > 0) { + b.frac =3D SHR_JAM(b.frac, diff_exp); a.frac =3D SUB(a.frac, b.frac); - } else { - a.frac =3D SHR_JAM(a.frac, b.exp - a.exp); + } else if (diff_exp < 0) { + a.frac =3D SHR_JAM(a.frac, -diff_exp); a.frac =3D SUB(b.frac, a.frac); a.exp =3D b.exp; a.sign ^=3D 1; + } else { + a.frac =3D SUB(b.frac, a.frac); + /* a.frac < b.frac results in carry into the overflow bit.= */ + if (HI(a.frac) & DECOMPOSED_OVERFLOW_BIT) { + a.frac =3D NEG(a.frac); + a.sign ^=3D 1; + } else if (EQ0(a.frac)) { + a.cls =3D float_class_zero; + goto sub_zero; + } } =20 - if (EQ0(a.frac)) { - a.cls =3D float_class_zero; - a.sign =3D s->float_rounding_mode =3D=3D float_round_down; - } else { - int shift =3D CLZ(a.frac) - 1; - a.frac =3D SHL(a.frac, shift); - a.exp -=3D shift; - } + shift =3D CLZ(a.frac) - 1; + a.frac =3D SHL(a.frac, shift); + a.exp -=3D shift; return a; } =20 /* 0 - 0 */ if (ab_mask =3D=3D float_cmask_zero) { + sub_zero: a.sign =3D s->float_rounding_mode =3D=3D float_round_down; return a; } --=20 2.25.1