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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id v6sm3780205wrp.69.2020.10.20.08.57.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2020 08:57:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=24XJoNPc8DTNqAEsM0sOYnp5VshSzc0j1PLW+SwTh3Q=; b=aj1G23Ik8CU6OUJ4eGwiJxMgEW5fcICviPcPd3Ojg9BlE57fkSdC08WBpp2xyLmbpr jdgTjVlx/toYvbjl/m0fiKS4f1BVgWkb3Zgs/ZZXBbkbUc1aAd2skzuykQqaKYCU2hok lH00e245uROQ0sn1TOLHh637AR+9ExkSQU8yx1/aG3uBPZShvUbBxvpgH3q+FZfWEgan mQC1vZr41jds9hfNzWVHLMNCoZL7jHhWSy1491jY0qcfhIERNXj5OwvTF1jq0Qlw1J07 lVMEPRvW/3Tlv45rDFmWSEG1l6Xwhmkv7dU4ZPEuoQs7d45DEfFstLPyc/fVfP+kv/P2 z+JA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=24XJoNPc8DTNqAEsM0sOYnp5VshSzc0j1PLW+SwTh3Q=; b=a8/PEPZ6ZpTgKEhWOkYdOMbytLeUnj7t7k8RX9whh4IM41Xfry6zKDVdsEQ6nYkb+/ G14aHRgAnvI4uSbJaIU0ZwDL33BDVBKyvkCavMnIDYo9kWYjX0DiB7ZA6gGZo/xRB3Qr HGZF0/0RlpN4nf4nP/JimJ1KXmLiNWx1+y0n7H6+3HY7qKTjcnSo/FqtL0SsyGvI7Lxd 8oAicOzJagxqXmKoLY0RTXOnUa/4nCf2YlMsoq0/XBTFwkHPguVRuaHVdkw/3vH6Qleu 13ABO8gZKteqchqbCgqwEVu7dDCYYAUzNxULMBzCDXOZOHCsJOyIOuBulza2gbsFVwQu vRfA== X-Gm-Message-State: AOAM531RDt3s+P5rjj4MyjvU4guMobSOOfiKbNbgpgKEjtb2lLH0IY2h 2maViQGq89adH54Fvg/ywPItNNUcboOrEw== X-Google-Smtp-Source: ABdhPJzzuEgcVpAsqBFYq3S0EPXIWjyNle/LaPWk0vU4M37uxc9+XMBlXUZQ1Jut35rYgUgpnuUtkg== X-Received: by 2002:a1c:8093:: with SMTP id b141mr3613706wmd.139.1603209465513; Tue, 20 Oct 2020 08:57:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/41] linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI Date: Tue, 20 Oct 2020 16:56:46 +0100 Message-Id: <20201020155656.8045-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201020155656.8045-1-peter.maydell@linaro.org> References: <20201020155656.8045-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Transform the prot bit to a qemu internal page bit, and save it in the page tables. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20201016184207.786698-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- include/exec/cpu-all.h | 2 ++ linux-user/syscall_defs.h | 4 ++++ target/arm/cpu.h | 5 +++++ linux-user/mmap.c | 16 ++++++++++++++++ target/arm/translate-a64.c | 6 +++--- 5 files changed, 30 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 61e13b50382..656a2a87888 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -274,6 +274,8 @@ extern intptr_t qemu_host_page_mask; /* FIXME: Code that sets/uses this is broken and needs to go away. */ #define PAGE_RESERVED 0x0020 #endif +/* Target-specific bits that will be used via page_get_flags(). */ +#define PAGE_TARGET_1 0x0080 =20 #if defined(CONFIG_USER_ONLY) void page_dump(FILE *f); diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index 731c3d5341a..cabbfb762dd 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -1277,6 +1277,10 @@ struct target_winsize { #define TARGET_PROT_SEM 0x08 #endif =20 +#ifdef TARGET_AARCH64 +#define TARGET_PROT_BTI 0x10 +#endif + /* Common */ #define TARGET_MAP_SHARED 0x01 /* Share changes */ #define TARGET_MAP_PRIVATE 0x02 /* Changes are private */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 49cd5cabcf2..c18a9167665 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3445,6 +3445,11 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTx= Attrs *x) #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) #define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) =20 +/* + * AArch64 usage of the PAGE_TARGET_* bits for linux-user. + */ +#define PAGE_BTI PAGE_TARGET_1 + /* * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in diff --git a/linux-user/mmap.c b/linux-user/mmap.c index f2615634201..00c05e6a0f1 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -83,6 +83,22 @@ static int validate_prot_to_pageflags(int *host_prot, in= t prot) *host_prot =3D (prot & (PROT_READ | PROT_WRITE)) | (prot & PROT_EXEC ? PROT_READ : 0); =20 +#ifdef TARGET_AARCH64 + /* + * The PROT_BTI bit is only accepted if the cpu supports the feature. + * Since this is the unusual case, don't bother checking unless + * the bit has been requested. If set and valid, record the bit + * within QEMU's page_flags. + */ + if (prot & TARGET_PROT_BTI) { + ARMCPU *cpu =3D ARM_CPU(thread_cpu); + if (cpu_isar_feature(aa64_bti, cpu)) { + valid |=3D TARGET_PROT_BTI; + page_flags |=3D PAGE_BTI; + } + } +#endif + return prot & ~valid ? 0 : page_flags; } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 71888083417..072754fa24d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14507,10 +14507,10 @@ static void disas_data_proc_simd_fp(DisasContext = *s, uint32_t insn) */ static bool is_guarded_page(CPUARMState *env, DisasContext *s) { -#ifdef CONFIG_USER_ONLY - return false; /* FIXME */ -#else uint64_t addr =3D s->base.pc_first; +#ifdef CONFIG_USER_ONLY + return page_get_flags(addr) & PAGE_BTI; +#else int mmu_idx =3D arm_to_core_mmu_idx(s->mmu_idx); unsigned int index =3D tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry =3D tlb_entry(env, mmu_idx, addr); --=20 2.20.1