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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id v6sm3780205wrp.69.2020.10.20.08.57.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2020 08:57:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XUl/ktQBgt0jm/lkqBECj09xhOXM9wD4kdunxxEyOrg=; b=TGeWpeBWpQIt21r3HA9OMxIUIYAV0voUbizywSWhsUvu24t+lBxYGO46JcegAKeTxo h0mBipeTaH14Tx+R7Di9P366jJHzM9VBa1IaY9rfwiu+voYglG+fS4cNqtlCrpEOjoUN fwvj1CH9eS3jJezoG8N3bJTa7EADRbIEN0ETsb8WS3p9vDVz1U1URa7Np+kN/SnrvyG8 9yHvU2SayeCgPmYIfTpkX1oIcYHJbYRVkMUyAo6xnSXG+cy4QavVimAJo38vLdEWuucM cp/CuWMREJHXmBExgX/xxqQydQE/VUVVr7uchJr9KpGj+sRDMXawEqrJwaZSzPCewXd0 umUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XUl/ktQBgt0jm/lkqBECj09xhOXM9wD4kdunxxEyOrg=; b=eNVrhj3+m7PdHaz6i/+uCv53ReIRM8MupReyi0i5dytix7D2EYNw9JU0YfolNhApVr youvzmVc8TrgfQzWV4Akce+omX9SVcfZ3mcrkMbzEVZYgxrVT+oKg70Kfi5kXWV9w6gs R65YCc1Kd8hWtYV7FjPmJPzdRnorr89LiG5WdkDg2eeIOdFj0wuAOsUrokoRNSzP9hQh JGhjNlMV8wkDFTjCN3PBxvGdwxZmqx2i55Poto3eqyH1QuJKBnbtfoayTkYo6+8KwOvR zVqh18zpETdsxtmLvrD7znMPGPn/kCXCxb8BWRhXZ2OoNf7i/KJlhlCLbau7uBUO/k44 Z9hw== X-Gm-Message-State: AOAM530CObvd359EF1R6HN2YGCgiPC+yAx79TfoVvaMWNAudZ7fzT6Y8 5Da2MRtDq+9pNGZGL2zbuZ58iJusRh5BvA== X-Google-Smtp-Source: ABdhPJzm5Qt/Eo+t/TowNDHrlj4TRJcIXt13obYLPJ2YdnA/FvmFPK9tJRvNO65calbwFjsQqALlEg== X-Received: by 2002:a1c:2b05:: with SMTP id r5mr3593511wmr.179.1603209461453; Tue, 20 Oct 2020 08:57:41 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/41] target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16 Date: Tue, 20 Oct 2020 16:56:43 +0100 Message-Id: <20201020155656.8045-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201020155656.8045-1-peter.maydell@linaro.org> References: <20201020155656.8045-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" M-profile CPUs with half-precision floating point support should be able to write to FPSCR.FZ16, but an M-profile specific masking of the value at the top of vfp_set_fpscr() currently prevents that. This is not yet an active bug because we have no M-profile FP16 CPUs, but needs to be fixed before we can add any. The bits that the masking is effectively preventing from being set are the A-profile only short-vector Len and Stride fields, plus the Neon QC bit. Rearrange the order of the function so that those fields are handled earlier and only under a suitable guard; this allows us to drop the M-profile specific masking, making FZ16 writeable. This change also makes the QC bit correctly RAZ/WI for older no-Neon A-profile cores. This refactoring also paves the way for the low-overhead-branch LTPSIZE field, which uses some of the bits that are used for A-profile Stride and Len. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20201019151301.2046-10-peter.maydell@linaro.org --- target/arm/vfp_helper.c | 47 ++++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 19 deletions(-) diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index abfdb6a8e23..364856498c4 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -194,36 +194,45 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t= val) val &=3D ~FPCR_FZ16; } =20 - if (arm_feature(env, ARM_FEATURE_M)) { + vfp_set_fpscr_to_host(env, val); + + if (!arm_feature(env, ARM_FEATURE_M)) { /* - * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits - * and also for the trapped-exception-handling bits IxE. + * Short-vector length and stride; on M-profile these bits + * are used for different purposes. + * We can't make this conditional be "if MVFR0.FPShVec !=3D 0", + * because in v7A no-short-vector-support cores still had to + * allow Stride/Len to be written with the only effect that + * some insns are required to UNDEF if the guest sets them. + * + * TODO: if M-profile MVE implemented, set LTPSIZE. */ - val &=3D 0xf7c0009f; + env->vfp.vec_len =3D extract32(val, 16, 3); + env->vfp.vec_stride =3D extract32(val, 20, 2); } =20 - vfp_set_fpscr_to_host(env, val); + if (arm_feature(env, ARM_FEATURE_NEON)) { + /* + * The bit we set within fpscr_q is arbitrary; the register as a + * whole being zero/non-zero is what counts. + * TODO: M-profile MVE also has a QC bit. + */ + env->vfp.qc[0] =3D val & FPCR_QC; + env->vfp.qc[1] =3D 0; + env->vfp.qc[2] =3D 0; + env->vfp.qc[3] =3D 0; + } =20 /* * We don't implement trapped exception handling, so the * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) * - * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC - * (which are stored in fp_status), and the other RES0 bits - * in between, then we clear all of the low 16 bits. + * The exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in + * fp_status; QC, Len and Stride are stored separately earlier. + * Clear out all of those and the RES0 bits: only NZCV, AHP, DN, + * FZ, RMode and FZ16 are kept in vfp.xregs[FPSCR]. */ env->vfp.xregs[ARM_VFP_FPSCR] =3D val & 0xf7c80000; - env->vfp.vec_len =3D (val >> 16) & 7; - env->vfp.vec_stride =3D (val >> 20) & 3; - - /* - * The bit we set within fpscr_q is arbitrary; the register as a - * whole being zero/non-zero is what counts. - */ - env->vfp.qc[0] =3D val & FPCR_QC; - env->vfp.qc[1] =3D 0; - env->vfp.qc[2] =3D 0; - env->vfp.qc[3] =3D 0; } =20 void vfp_set_fpscr(CPUARMState *env, uint32_t val) --=20 2.20.1