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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id v6sm3780205wrp.69.2020.10.20.08.57.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2020 08:57:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=L0lYmOUonCsI2H/sVY4IV71YZ7WBk/jN9yG1LepsCeQ=; b=VSpgnK1LEpn0kGA3tyU60mbWTI15NvlO9OZqUz/GPAqw/w6xLBJ5J5Lrlphy/szOBP fcGUMkCjVJYYEM6i+TDKoyXwQy+R0yCl/Fz9Z6AGBurZMrWCu94DSZSn5oyu6FTwuj5M CvZg+Yv7P0kcw4J7cvY2wI450FDjglYedmDTl64NGIBBxDVEPhllVso/Tp3nOo/smaLO zIp3OHTi6IiNgFrm2ZNiiOd2dabrTiqhvtn0T2lvU8WAYBHJxf7qY8+/wFKfHng6lHiM BV/stjT/Wv8J7WNeTvVIW+tjG4pQRFtCPKvhSEutNoSuTp0fR6v7ACJzOGRqKgh5HXxo Q4Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L0lYmOUonCsI2H/sVY4IV71YZ7WBk/jN9yG1LepsCeQ=; b=N2iDOgcxzc97zsBTJ52PuGJrkdIL3HbGAX++WpjZzBbIPAchD93SL6YRp1DPep/1ea /6JagGoCy/sQnMFZ45abchq16l4cV7n2YyacP1q8cpkDVyoA1Cs06df3yymsDCNCTVKl g5arT3rQOJGJRTTf+IDFk6zL6ScJ8t7cVo2MLGwjOxXsG/J9kfXafDAm/7znJV3Q9QGT HbxqUmqspDgWSeMij1kgmP02q7/bxBRx9OhVeohbu6mqBk65AK2rNtKpFd0opEhi7uXN lG+nqUsZwpPjzqs3DDbPffwFCdV9Bi6InsHHToX3mV8lXU18wQw0BX/QLtH6G/6UWjvC NXsA== X-Gm-Message-State: AOAM5307SiPs2mzldfi0n4/HIXgMXhxiFg9kLT3bh2jA+rYL+3NT3Ys2 IPSxHye5sExRGRPH8Yq1013ElPWXwykgyA== X-Google-Smtp-Source: ABdhPJw9xpDEM6/8lvjdRXuPRhqj3rooHKWmbhCBef9cHUlvi+ezrysOKpV6h2RyDPY10GnD5rFM0A== X-Received: by 2002:a1c:b40b:: with SMTP id d11mr3543359wmf.152.1603209441497; Tue, 20 Oct 2020 08:57:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/41] hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers Date: Tue, 20 Oct 2020 16:56:28 +0100 Message-Id: <20201020155656.8045-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201020155656.8045-1-peter.maydell@linaro.org> References: <20201020155656.8045-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 Add trace events for GPU and CPU IRQs. Reviewed-by: Luc Michel Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20201017180731.1165871-2-f4bug@amsat.org Signed-off-by: Peter Maydell --- hw/intc/bcm2835_ic.c | 4 +++- hw/intc/trace-events | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/intc/bcm2835_ic.c b/hw/intc/bcm2835_ic.c index 53ab8f58810..9000d995e81 100644 --- a/hw/intc/bcm2835_ic.c +++ b/hw/intc/bcm2835_ic.c @@ -18,6 +18,7 @@ #include "migration/vmstate.h" #include "qemu/log.h" #include "qemu/module.h" +#include "trace.h" =20 #define GPU_IRQS 64 #define ARM_IRQS 8 @@ -51,7 +52,6 @@ static void bcm2835_ic_update(BCM2835ICState *s) set =3D (s->gpu_irq_level & s->gpu_irq_enable) || (s->arm_irq_level & s->arm_irq_enable); qemu_set_irq(s->irq, set); - } =20 static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int level) @@ -59,6 +59,7 @@ static void bcm2835_ic_set_gpu_irq(void *opaque, int irq,= int level) BCM2835ICState *s =3D opaque; =20 assert(irq >=3D 0 && irq < 64); + trace_bcm2835_ic_set_gpu_irq(irq, level); s->gpu_irq_level =3D deposit64(s->gpu_irq_level, irq, 1, level !=3D 0); bcm2835_ic_update(s); } @@ -68,6 +69,7 @@ static void bcm2835_ic_set_arm_irq(void *opaque, int irq,= int level) BCM2835ICState *s =3D opaque; =20 assert(irq >=3D 0 && irq < 8); + trace_bcm2835_ic_set_cpu_irq(irq, level); s->arm_irq_level =3D deposit32(s->arm_irq_level, irq, 1, level !=3D 0); bcm2835_ic_update(s); } diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 527c3f76cae..22782b3f089 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -199,3 +199,7 @@ nvic_sysreg_write(uint64_t addr, uint32_t value, unsign= ed size) "NVIC sysreg wri heathrow_write(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64"= %u: 0x%"PRIx64 heathrow_read(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" = %u: 0x%"PRIx64 heathrow_set_irq(int num, int level) "set_irq: num=3D0x%02x level=3D%d" + +# bcm2835_ic.c +bcm2835_ic_set_gpu_irq(int irq, int level) "GPU irq #%d level %d" +bcm2835_ic_set_cpu_irq(int irq, int level) "CPU irq #%d level %d" --=20 2.20.1