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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y14sm309918wma.48.2020.10.19.08.13.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2020 08:13:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6hKic17i51H/7+th1/P5umqhoIFiqn2jr04cBxU9UUU=; b=XO/pELETpBfePYzggX2WerIDXKceQabShhBSBsEq+UtA//1x/7mx6XFoGSmpHtEpIY fYVOjvtUpzEWyyS+ZNP6Z8hQjvuY6kEUfMXJUv7o0f1g6KReHTgio8+9w7xxtUdaOYPa PJr7Ho/0IGO8lca9gLnAmhJG/tK0IjBUnWStzJ5Q/YMUy/elxGLxVTVZ3zbADPeIQwrv JqPeb7n6NiJiRKoWG7ItUZXuJBtCAHyK4uxnQT2sYcCIz4dcTPtw4PTvYr0/Ve6jXUjH wWQOANOZzdpu4UMvYlRdrdI4lSG++qufwTuHiAPOxASxP/R5R21oJ2g2vZc4WRF11VJ2 F/gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6hKic17i51H/7+th1/P5umqhoIFiqn2jr04cBxU9UUU=; b=gjXdzqwMIDb3CT0dSRU3SK1sdt9KGAZx5Pej39wimBnD4rOIM/njycgP+y2HvF7GrP sHoJGQrW2VbLmX+yfLp3W8olHcb0PCw4d6UL3UMLZpGSArQuCzltX/DWC2UV4TxURjXz ulq0UI3zu419C67ke9Dn1Q1eSpZwRA/DWIXmnpDIJ34oC76y0+fo7RCaH69/NCsO3W93 5Ut7zQU4MCkQkqlR74Qjupc83tQa1Kv7tZGasjdjDeZD/KNjDD/w+V5agC/Nd0olCY0l h9Hobhh7d32rTqsPKcodk2QA/o/ktM+FvIh8LRNU/l22JL8XI9l4zqaIR9e7eSFm2hut 7gCQ== X-Gm-Message-State: AOAM5315iN6V3ggizHUBmdPZxPJdrwNC94rtMnHfkTETbSoeiI5cRLer /2W17OIKJcbjsjgGrevx3BRKyA== X-Google-Smtp-Source: ABdhPJxMd9qOVmibbgB1FDhEnrEoza+fbugjVPKFZaOCwTdMBwemcb/rBW6+X/91QfOTAgGwMQzL8g== X-Received: by 2002:adf:8bd4:: with SMTP id w20mr20242969wra.391.1603120393234; Mon, 19 Oct 2020 08:13:13 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 08/10] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile Date: Mon, 19 Oct 2020 16:12:59 +0100 Message-Id: <20201019151301.2046-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201019151301.2046-1-peter.maydell@linaro.org> References: <20201019151301.2046-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In arm_cpu_realizefn(), if the CPU has VFP or Neon disabled then we squash the ID register fields so that we don't advertise it to the guest. This code was written for A-profile and needs some tweaks to work correctly on M-profile: * A-profile only fields should not be zeroed on M-profile: - MVFR0.FPSHVEC,FPTRAP - MVFR1.SIMDLS,SIMDINT,SIMDSP,SIMDHP - MVFR2.SIMDMISC * M-profile only fields should be zeroed on M-profile: - MVFR1.FP16 In particular, because MVFR1.SIMDHP on A-profile is the same field as MVFR1.FP16 on M-profile this code was incorrectly disabling FP16 support on an M-profile CPU (where has_neon is always false). This isn't a visible bug yet because we don't have any M-profile CPUs with FP16 support, but the change is necessary before we introduce any. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/cpu.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 056319859fb..186ee621a65 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1429,17 +1429,22 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) u =3D cpu->isar.mvfr0; u =3D FIELD_DP32(u, MVFR0, FPSP, 0); u =3D FIELD_DP32(u, MVFR0, FPDP, 0); - u =3D FIELD_DP32(u, MVFR0, FPTRAP, 0); u =3D FIELD_DP32(u, MVFR0, FPDIVIDE, 0); u =3D FIELD_DP32(u, MVFR0, FPSQRT, 0); - u =3D FIELD_DP32(u, MVFR0, FPSHVEC, 0); u =3D FIELD_DP32(u, MVFR0, FPROUND, 0); + if (!arm_feature(env, ARM_FEATURE_M)) { + u =3D FIELD_DP32(u, MVFR0, FPTRAP, 0); + u =3D FIELD_DP32(u, MVFR0, FPSHVEC, 0); + } cpu->isar.mvfr0 =3D u; =20 u =3D cpu->isar.mvfr1; u =3D FIELD_DP32(u, MVFR1, FPFTZ, 0); u =3D FIELD_DP32(u, MVFR1, FPDNAN, 0); u =3D FIELD_DP32(u, MVFR1, FPHP, 0); + if (arm_feature(env, ARM_FEATURE_M)) { + u =3D FIELD_DP32(u, MVFR1, FP16, 0); + } cpu->isar.mvfr1 =3D u; =20 u =3D cpu->isar.mvfr2; @@ -1475,16 +1480,18 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) u =3D FIELD_DP32(u, ID_ISAR6, FHM, 0); cpu->isar.id_isar6 =3D u; =20 - u =3D cpu->isar.mvfr1; - u =3D FIELD_DP32(u, MVFR1, SIMDLS, 0); - u =3D FIELD_DP32(u, MVFR1, SIMDINT, 0); - u =3D FIELD_DP32(u, MVFR1, SIMDSP, 0); - u =3D FIELD_DP32(u, MVFR1, SIMDHP, 0); - cpu->isar.mvfr1 =3D u; + if (!arm_feature(env, ARM_FEATURE_M)) { + u =3D cpu->isar.mvfr1; + u =3D FIELD_DP32(u, MVFR1, SIMDLS, 0); + u =3D FIELD_DP32(u, MVFR1, SIMDINT, 0); + u =3D FIELD_DP32(u, MVFR1, SIMDSP, 0); + u =3D FIELD_DP32(u, MVFR1, SIMDHP, 0); + cpu->isar.mvfr1 =3D u; =20 - u =3D cpu->isar.mvfr2; - u =3D FIELD_DP32(u, MVFR2, SIMDMISC, 0); - cpu->isar.mvfr2 =3D u; + u =3D cpu->isar.mvfr2; + u =3D FIELD_DP32(u, MVFR2, SIMDMISC, 0); + cpu->isar.mvfr2 =3D u; + } } =20 if (!cpu->has_neon && !cpu->has_vfp) { --=20 2.20.1