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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id q2sm14827420wrw.40.2020.10.18.13.55.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Oct 2020 13:55:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xybSrKSg2KE6ujJ+C2r6JVR07E7WgYnPSHZlCpKgLHE=; b=gDzQ2ANgYTh98m6qjcaz1tLYnAs0XnX6uZ9MvJhD3l7iVZ8I/qOtD238/d245Qdc6U RW32s/pY5lT2BIsGfr0zBW3eySqthcwg/RY12lQ8n7Pii2uXNmh2t61llgS2YM+/GxBz hzXJPxPqyAQH25dZKzSjEU2ySRLriLjS2PtxkT3DssaIj4LmmUHuF7p+F9yynbLoT0FO OaRy2qTV6Ejc3XxZVWQiZjQFYwdpNGmXxIIvoBcfxiL+I9Crb6s3yEgpgdUJxbCRzbSI /tZrQRXklf5/fuwPOdb21sXHGvsPd5NWgdvxSpVJFXO6pg5Tq/QwJ/9yabbW9ce5jhVs 47kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=xybSrKSg2KE6ujJ+C2r6JVR07E7WgYnPSHZlCpKgLHE=; b=uHrRqXFJL2qynafENdjO8NnhgNBggEx4mEy0gWMTfqfTDN4FED83icv3sEpbNg/rRL Q4iB9A2pr6vhFr+RSOqSfGWto0OYlUbd5EDtODIXc7cIOzHrYkyZIuD5dMuwL+UZHasj ymItNVKo3bZ2PFPUlBNsQc9p1qzVVTlz9Fq5qG4AaQctMaZmgmL6Kc6fN9jtcny4f6eC 4RaF88jX4yOgh23aQwSInrfTPFOMUR0TJITK2xVgvPAyen4AvgDZZkEthE6u9sIWM+np YlJS7GRA2AnL95rwniQd8qpK7JTSFtxY6G5RnblEOwpnxe3m2lY18fpDcOhX1wf/QzWf yPig== X-Gm-Message-State: AOAM530lwMdMx3YRpyoHZs0fjKzjK+FjWfHDsH/3OF344dECGi420Vam sE7CWbXPZK1Z0JiuSCpz5ao= X-Google-Smtp-Source: ABdhPJyyCnet80EvJyHgJZlJM4gIWHqH1WmLQj+Bo9Q2Yk/eJMKVIHwKpkHTgEtZhTbAKboRRHgOWA== X-Received: by 2002:a1c:a983:: with SMTP id s125mr14851221wme.50.1603054558048; Sun, 18 Oct 2020 13:55:58 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Johnny Sun , Peter Maydell , qemu-arm@nongnu.org, Stewart Hildebrand , Andrew Baumann , Esteban Bosse , Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 1/3] hw/arm/bcm2836: Add the ARMv8 BCM2838 Date: Sun, 18 Oct 2020 22:55:49 +0200 Message-Id: <20201018205551.1537927-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201018205551.1537927-1-f4bug@amsat.org> References: <20201018205551.1537927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The BCM2838 share the same peripheral base block from the BCM283x family, but connects 4 Cortex-A72 cores via a GICv2. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/bcm2836.h | 3 + hw/arm/bcm2836.c | 179 +++++++++++++++++++++++++++++++++++++++ hw/arm/trace-events | 2 + 3 files changed, 184 insertions(+) diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 6f90cabfa3a..92561e96aa2 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -14,6 +14,7 @@ =20 #include "hw/arm/bcm2835_peripherals.h" #include "hw/intc/bcm2836_control.h" +#include "hw/intc/arm_gic.h" #include "target/arm/cpu.h" #include "qom/object.h" =20 @@ -29,6 +30,7 @@ OBJECT_DECLARE_TYPE(BCM283XState, BCM283XClass, BCM283X) #define TYPE_BCM2835 "bcm2835" #define TYPE_BCM2836 "bcm2836" #define TYPE_BCM2837 "bcm2837" +#define TYPE_BCM2838 "bcm2838" =20 struct BCM283XState { /*< private >*/ @@ -40,6 +42,7 @@ struct BCM283XState { struct { ARMCPU core; } cpu[BCM283X_NCPUS]; + GICState gic; BCM2836ControlState control; BCM2835PeripheralState peripherals; }; diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index de7ade2878e..fe795217e26 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -16,6 +16,7 @@ #include "hw/arm/bcm2836.h" #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" +#include "trace.h" =20 typedef struct BCM283XClass { /*< private >*/ @@ -26,6 +27,7 @@ typedef struct BCM283XClass { unsigned core_count; hwaddr peri_base; /* Peripheral base address seen by the CPU */ hwaddr ctrl_base; /* Interrupt controller and mailboxes etc. */ + hwaddr gic_base; int clusterid; } BCM283XClass; =20 @@ -52,6 +54,10 @@ static void bcm2836_init(Object *obj) qdev_prop_set_uint32(DEVICE(obj), "enabled-cpus", bc->core_count); } =20 + if (bc->gic_base) { + object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC); + } + if (bc->ctrl_base) { object_initialize_child(obj, "control", &s->control, TYPE_BCM2836_CONTROL); @@ -170,6 +176,161 @@ static void bcm2836_realize(DeviceState *dev, Error *= *errp) } } =20 +#ifdef TARGET_AARCH64 + +#define GIC400_MAINTAINANCE_IRQ 9 +#define GIC400_TIMER_NS_EL2_IRQ 10 +#define GIC400_TIMER_VIRT_IRQ 11 +#define GIC400_LEGACY_FIQ 12 +#define GIC400_TIMER_S_EL1_IRQ 13 +#define GIC400_TIMER_NS_EL1_IRQ 14 +#define GIC400_LEGACY_IRQ 15 + +/* Number of external interrupt lines to configure the GIC with */ +#define GIC_NUM_IRQS 128 + +#define PPI(cpu, irq) (GIC_NUM_IRQS + (cpu) * GIC_INTERNAL + GIC_NR_SGIS += irq) + +#define GIC_BASE_OFS 0x0000 +#define GIC_DIST_OFS 0x1000 +#define GIC_CPU_OFS 0x2000 +#define GIC_VIFACE_THIS_OFS 0x4000 +#define GIC_VIFACE_OTHER_OFS(cpu) (0x5000 + (cpu) * 0x200) +#define GIC_VCPU_OFS 0x6000 + +#define VIRTUAL_PMU_IRQ 7 + +static void bcm2838_gic_set_irq(void *opaque, int irq, int level) +{ + BCM283XState *s =3D (BCM283XState *)opaque; + + trace_bcm2838_gic_set_irq(irq, level); + qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); +} + +static void bcm2838_realize(DeviceState *dev, Error **errp) +{ + BCM283XState *s =3D BCM283X(dev); + BCM283XClass *bc =3D BCM283X_GET_CLASS(dev); + int n; + + if (!bcm283x_common_realize(dev, errp)) { + return; + } + + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->peripherals), 0, + bc->peri_base, 1); + + /* bcm2836 interrupt controller (and mailboxes, etc.) */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->control), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->control), 0, bc->ctrl_base); + + /* Create cores */ + for (n =3D 0; n < bc->core_count; n++) { + /* TODO: this should be converted to a property of ARM_CPU */ + s->cpu[n].core.mp_affinity =3D (bc->clusterid << 8) | n; + + /* set periphbase/CBAR value for CPU-local registers */ + if (!object_property_set_int(OBJECT(&s->cpu[n].core), "reset-cbar", + bc->peri_base, errp)) { + return; + } + + /* start powered off if not enabled */ + if (!object_property_set_bool(OBJECT(&s->cpu[n].core), + "start-powered-off", + n >=3D s->enabled_cpus, + errp)) { + return; + } + + if (!qdev_realize(DEVICE(&s->cpu[n].core), NULL, errp)) { + return; + } + } + + if (!object_property_set_uint(OBJECT(&s->gic), "revision", 2, errp)) { + return; + } + + if (!object_property_set_uint(OBJECT(&s->gic), "num-cpu", BCM283X_NCPU= S, + errp)) { + return; + } + + if (!object_property_set_uint(OBJECT(&s->gic), + "num-irq", GIC_NUM_IRQS + GIC_INTERNAL, + errp)) { + return; + } + + if (!object_property_set_bool(OBJECT(&s->gic), + "has-virtualization-extensions", + true, errp)) { + return; + } + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, + bc->ctrl_base + bc->gic_base + GIC_DIST_OFS); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, + bc->ctrl_base + bc->gic_base + GIC_CPU_OFS); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, + bc->ctrl_base + bc->gic_base + GIC_VIFACE_THIS_OFS); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, + bc->ctrl_base + bc->gic_base + GIC_VCPU_OFS); + + for (n =3D 0; n < BCM283X_NCPUS; n++) { + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 4 + n, + bc->ctrl_base + bc->gic_base + GIC_VIFACE_OTHER_OF= S(n)); + } + + for (n =3D 0; n < BCM283X_NCPUS; n++) { + DeviceState *cpudev =3D DEVICE(&s->cpu[n]); + DeviceState *gicdev =3D DEVICE(&s->gic); + + /* Connect the GICv2 outputs to the CPU */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n, + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + BCM283X_NCPUS, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + 2 * BCM283X_NCPUS, + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + 3 * BCM283X_NCPUS, + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), n + 4 * BCM283X_NCPUS, + qdev_get_gpio_in(gicdev, + PPI(n, GIC400_MAINTAINANCE_IRQ= ))); + + /* Connect timers from the CPU to the interrupt controller */ + qdev_connect_gpio_out(cpudev, GTIMER_PHYS, + qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_NS_EL1_IR= Q))); + qdev_connect_gpio_out(cpudev, GTIMER_VIRT, + qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_VIRT_IRQ)= )); + qdev_connect_gpio_out(cpudev, GTIMER_HYP, + qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_NS_EL2_IR= Q))); + qdev_connect_gpio_out(cpudev, GTIMER_SEC, + qdev_get_gpio_in(gicdev, PPI(n, GIC400_TIMER_S_EL1_IRQ= ))); + /* PMU interrupt */ + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, + qdev_get_gpio_in(gicdev, PPI(n, VIRTUAL_PMU_IRQ))); + } + + /* Pass through inbound GPIO lines to the GIC */ + qdev_init_gpio_in(dev, bcm2838_gic_set_irq, GIC_NUM_IRQS); + + /* Pass through outbound IRQ lines from the GIC */ + qdev_pass_gpios(DEVICE(&s->gic), DEVICE(&s->peripherals), NULL); +} +#endif /* TARGET_AARCH64 */ + static void bcm283x_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -215,6 +376,20 @@ static void bcm2837_class_init(ObjectClass *oc, void *= data) bc->clusterid =3D 0x0; dc->realize =3D bcm2836_realize; }; + +static void bcm2838_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + BCM283XClass *bc =3D BCM283X_CLASS(oc); + + bc->cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a72"); + bc->core_count =3D BCM283X_NCPUS; + bc->peri_base =3D 0xfe000000; + bc->ctrl_base =3D 0xff800000; + bc->gic_base =3D 0x40000; + bc->clusterid =3D 0x0; + dc->realize =3D bcm2838_realize; +}; #endif =20 static const TypeInfo bcm283x_types[] =3D { @@ -231,6 +406,10 @@ static const TypeInfo bcm283x_types[] =3D { .name =3D TYPE_BCM2837, .parent =3D TYPE_BCM283X, .class_init =3D bcm2837_class_init, + }, { + .name =3D TYPE_BCM2838, + .parent =3D TYPE_BCM283X, + .class_init =3D bcm2838_class_init, #endif }, { .name =3D TYPE_BCM283X, diff --git a/hw/arm/trace-events b/hw/arm/trace-events index c8a4d80f6bd..37487424b28 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -53,3 +53,5 @@ smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifi= er node for iommu mr=3D%s smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu= mr=3D%s" smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, = uint8_t tg, uint64_t num_pages) "iommu mr=3D%s asid=3D%d iova=3D0x%"PRIx64"= tg=3D%d num_pages=3D0x%"PRIx64 =20 +# bcm2836.c +bcm2838_gic_set_irq(int irq, int level) "gic irq:%d lvl:%d" --=20 2.26.2 From nobody Wed May 15 09:48:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.68 as permitted sender) client-ip=209.85.221.68; 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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id o194sm13453555wme.24.2020.10.18.13.56.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Oct 2020 13:56:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VqdKnd4Twgx8yICk/fUvLd4Y9zGgGTiuVIGMLYhnK2s=; b=h46BvoPMlVaL7Ekb8SrICZhfn7Z0J4A4005iNJgFfapG++dos2wR681FZOhgvEXZVH QDchDGE22IZMvpCjlpK3hNDTn5ybXd4llTJmFn7ojHneaAzk4HBw2iodXOreoGvky803 kh4jJQROMomHf5triZkfh9MRBgQlTu3zzyTw7tnoZJHYIbWm2obehVngX9aL3vgq2JPO NUeuU9D/v29iH8srgSvVa8S4eB+f5btOS6hOFWi48RhwEEwH8xegHV1f07xWmZ9HKzkw vJqH34IqI5AXYbZW/BVF+u8jQWerkhW5LrjrELbEHeSUw5BPNxGHJophGAzbSv80iZpT hHuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=VqdKnd4Twgx8yICk/fUvLd4Y9zGgGTiuVIGMLYhnK2s=; b=RtBBcFpxWh6LVp76W+MhvIyVjbIffmN+4eSpIp5WCcRRAKAEczxks2my9zzIWgxfq5 E5M9xA+lAUhwYQNmeFaJ8kEZ+xqsJnR9AxQid9kH72at3igwRbEQN8ACJ1E6MIEZkPYi 0XQj8ZMRQj+UmDABG2c8GVLxeXUiuw5F4txHJUHhSdWAzaJiooJQS4TexkWN2KDHgAzg wt1ZFunGrnS0XH3HLsftHdrw/FXB2A5vZ/hw1JWDASmvrsk9hUZhooHt2D82O8L1j/Eg 2SSOyoO8jLeEprEev0nEfg23FhrXlptdQF9XnAxUPaKvnbu338B2tHfszgcaXG9ZzHLc n9FQ== X-Gm-Message-State: AOAM533UCGG4Q7tFwn8JJuZG10cLII5uY7Fu5YwmlnMzOeDy9kyV9oO3 i+QZP0OpoTbH1N2F+y3gEIU= X-Google-Smtp-Source: ABdhPJywO7sQ100/xbHnc+jGftLDSQUSlT/NI6jUs2/qYJ2jjAif4gI9cjvGJ/m3TzcrEJ/otUxtsA== X-Received: by 2002:adf:9dd1:: with SMTP id q17mr16392270wre.317.1603054562540; Sun, 18 Oct 2020 13:56:02 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Johnny Sun , Peter Maydell , qemu-arm@nongnu.org, Stewart Hildebrand , Andrew Baumann , Esteban Bosse , Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 2/3] hw/arm/raspi: Add the Raspberry Pi 4 model B Date: Sun, 18 Oct 2020 22:55:50 +0200 Message-Id: <20201018205551.1537927-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201018205551.1537927-1-f4bug@amsat.org> References: <20201018205551.1537927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Add 2 variants of the raspi4: - raspi4b1g: Raspberry Pi 4B (revision 1.1, with 1 GiB of RAM) - raspi4b2g Raspberry Pi 4B (revision 1.2, with 2 GiB) Example booting the 2GiB machine using content from [*]: $ qemu-system-aarch64 -M raspi4b2g -serial stdio \ -kernel raspberrypi/firmware/boot/kernel8.img \ -dtb raspberrypi/firmware/boot/bcm2711-rpi-4-b.dtb \ -append 'printk.time=3D0 earlycon=3Dpl011,0xfe201000 console=3DttyAMA= 0' [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd083] [ 0.000000] Linux version 5.4.51-v8+ (dom@buildbot) (gcc version 5.4.0= 20160609 (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.9)) #1333 SMP PREEMPT Mon Aug= 10 16:58:35 BST 2020 [ 0.000000] Machine model: Raspberry Pi 4 Model B [ 0.000000] earlycon: pl11 at MMIO 0x00000000fe201000 (options '') [ 0.000000] printk: bootconsole [pl11] enabled [ 0.000000] efi: Getting EFI parameters from FDT: [ 0.000000] efi: UEFI not found. [ 0.000000] Reserved memory: created CMA memory pool at 0x000000002c00= 0000, size 64 MiB [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible i= d shared-dma-pool [ 0.000000] Detected PIPT I-cache on CPU0 [ 0.000000] CPU features: detected: EL2 vector hardening [ 0.000000] ARM_SMCCC_ARCH_WORKAROUND_1 missing from firmware [ 0.000000] software IO TLB: mapped [mem 0x3bfff000-0x3ffff000] (64MB) [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 [ 0.000000] GIC: Using split EOI/Deactivate mode [ 0.633289] smp: Bringing up secondary CPUs ... [ 0.694226] Detected PIPT I-cache on CPU1 [ 0.699002] CPU1: Booted secondary processor 0x0000000001 [0x410fd083] [ 0.782443] Detected PIPT I-cache on CPU2 [ 0.783511] CPU2: Booted secondary processor 0x0000000002 [0x410fd083] [ 0.848854] Detected PIPT I-cache on CPU3 [ 0.850003] CPU3: Booted secondary processor 0x0000000003 [0x410fd083] [ 0.857099] smp: Brought up 1 node, 4 CPUs [ 0.863500] SMP: Total of 4 processors activated. [ 0.865446] CPU features: detected: 32-bit EL0 Support [ 0.866667] CPU features: detected: CRC32 instructions [ 2.235648] CPU: All CPU(s) started at EL2 ... [*] http://archive.raspberrypi.org/debian/pool/main/r/raspberrypi-firmware/= raspberrypi-kernel_1.20200512-2_armhf.deb Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/raspi.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 4ea200572ea..6a793766840 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -73,6 +73,7 @@ typedef enum RaspiProcessorId { PROCESSOR_ID_BCM2835 =3D 0, PROCESSOR_ID_BCM2836 =3D 1, PROCESSOR_ID_BCM2837 =3D 2, + PROCESSOR_ID_BCM2838 =3D 3, } RaspiProcessorId; =20 static const struct { @@ -82,6 +83,7 @@ static const struct { [PROCESSOR_ID_BCM2835] =3D {TYPE_BCM2835, 1}, [PROCESSOR_ID_BCM2836] =3D {TYPE_BCM2836, BCM283X_NCPUS}, [PROCESSOR_ID_BCM2837] =3D {TYPE_BCM2837, BCM283X_NCPUS}, + [PROCESSOR_ID_BCM2838] =3D {TYPE_BCM2838, BCM283X_NCPUS}, }; =20 static uint64_t board_ram_size(uint32_t board_rev) @@ -366,6 +368,24 @@ static void raspi3b_machine_class_init(ObjectClass *oc= , void *data) rmc->board_rev =3D 0xa02082; raspi_machine_class_common_init(mc, rmc->board_rev); }; + +static void raspi4b1g_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + RaspiMachineClass *rmc =3D RASPI_MACHINE_CLASS(oc); + + rmc->board_rev =3D 0xa03111; + raspi_machine_class_common_init(mc, rmc->board_rev); +}; + +static void raspi4b2g_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + RaspiMachineClass *rmc =3D RASPI_MACHINE_CLASS(oc); + + rmc->board_rev =3D 0xb03112; + raspi_machine_class_common_init(mc, rmc->board_rev); +}; #endif /* TARGET_AARCH64 */ =20 static const TypeInfo raspi_machine_types[] =3D { @@ -390,6 +410,14 @@ static const TypeInfo raspi_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("raspi3b"), .parent =3D TYPE_RASPI_MACHINE, .class_init =3D raspi3b_machine_class_init, + }, { + .name =3D MACHINE_TYPE_NAME("raspi4b1g"), + .parent =3D TYPE_RASPI_MACHINE, + .class_init =3D raspi4b1g_machine_class_init, + }, { + .name =3D MACHINE_TYPE_NAME("raspi4b2g"), + .parent =3D TYPE_RASPI_MACHINE, + .class_init =3D raspi4b2g_machine_class_init, #endif }, { .name =3D TYPE_RASPI_MACHINE, --=20 2.26.2 From nobody Wed May 15 09:48:47 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.68 as permitted sender) client-ip=209.85.221.68; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f68.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1603054569; cv=none; d=zohomail.com; s=zohoarc; b=DDtH/waWlvd68g2Gswp1L0H70MAmi8pk/6eZeR2PHM7qtB3BEJh5UQ6adWhIiqjfuClNZuYeRRhnZfFqm+EZ876dCtzTRZR/Zst/gfg1P7l7KNVdXWoLe2I4kFwPMvuQPpheWpBh/a4F0SQypge7ZrzQ7wWYE1pDJB+DcJ1Hxvc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603054569; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=H4Vj4prHafiErMNGerrw49ZgJ7IM19BsKxuWO4t5AF8=; b=YcrG6Oz4sIxTzmOxAdUp1yySpm4hUFcMfWywD5nIr6k3raTWSgWQ365CnhVNgNp/NjjefCrk1HJe5E3x7XdbN/ox+Hqk5orsihI3WIsSq/aPAbAFFIJBYOpf5GVU5EDZPiVCqGVeL8ZYiCCkfnzV5dXSZyV0zmnPkgFb7CVYl7E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.68 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by mx.zohomail.com with SMTPS id 1603054569060826.1076500879644; Sun, 18 Oct 2020 13:56:09 -0700 (PDT) Received: by mail-wr1-f68.google.com with SMTP id h5so9160151wrv.7 for ; Sun, 18 Oct 2020 13:56:08 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (117.red-83-52-172.dynamicip.rima-tde.net. [83.52.172.117]) by smtp.gmail.com with ESMTPSA id u20sm13159004wmm.29.2020.10.18.13.56.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Oct 2020 13:56:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H4Vj4prHafiErMNGerrw49ZgJ7IM19BsKxuWO4t5AF8=; b=rO1ItjBKyeiW1aL2VZWP1VWyDoieT2uDkEkaSyU4wBw8KpKSsWym96gcMfYja3dRYG hhk39KvxVuZv6cdAdOBe746VUG9oCniDbR4HBu9DFAIMvNZkBr9l1n9vt/HkTeRYn9sn EpvLqp0XKk0C/OWxjbIulNg83ybZVxo0EcUL8ks1jsAk30g6q6gEhSBsl2yLjNjI4p0u 9vde+OlvMkWCBsVaTK/5MQs9gRJkGFPDmocg/p4DLKllDUKaV+Tbx3rXtViIM+IJ383E emQR+JybIovRUz0f26IBEHUgdA57zwt4PyPPvCt+qbOsjL1Dm83qg0BrP1tzD+JREoUe 0OaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=H4Vj4prHafiErMNGerrw49ZgJ7IM19BsKxuWO4t5AF8=; b=hIICvywlpxCdLUWhFHPzjiyTDfhZc+zkd3yLQijyLdNaMGQA+X2uuIX2RbJJutn2cr 4wpZviSxIH2pN3HNlsGrquCb/pAdO8FbAKsO2J0ieWgOjrDMLv2iT1L2x7ehour6ZK4I wvsNA6j7CIa2L0zxgA1Kndj+dDQjeEE8Nbg7geqLtqiKB4xZRQZCUrymIuMo/knu+Syo J9mIDPv/29R1hp8rl5+iUVWBfN2Au3UEbz5Nbxe4CJSsDk+wGWlxXQ7p8ZqCcK49JGg+ ntZ4inbAn7qL+TM6hOk4gUNoDJmrgEP9P9pauMedyLS6kM/euRTEKhpa3wKbJ4bl3ibk OWjg== X-Gm-Message-State: AOAM530eVt46TAH1N9C3ZX+Qp8ReEQ60mGes6HPpWhfeZdT0a1WPfsi1 r6DklQAY00AWvPzqVO1RhFs= X-Google-Smtp-Source: ABdhPJxS32rV2nA5cYZZMxE8yQCXRc/20UUlieVTDzs6VAKfIgViQQsoIroDAY/YTZsE0V6I9qL8FA== X-Received: by 2002:a5d:43c6:: with SMTP id v6mr16119386wrr.20.1603054567144; Sun, 18 Oct 2020 13:56:07 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Johnny Sun , Peter Maydell , qemu-arm@nongnu.org, Stewart Hildebrand , Andrew Baumann , Esteban Bosse , Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [NOTFORMERGE PATCH v2 3/3] hw/arm/raspi: Remove unsupported raspi4 peripherals from device tree Date: Sun, 18 Oct 2020 22:55:51 +0200 Message-Id: <20201018205551.1537927-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201018205551.1537927-1-f4bug@amsat.org> References: <20201018205551.1537927-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Kludge when using Linux kernels to reach userland. No device in DT -> no hardware initialization. Linux 5.9 uses the RPI_FIRMWARE_GET_CLOCKS so we now need to implement that feature too. Look like a cat and mouse game... Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/raspi.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 6a793766840..93eb6591ee8 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -25,6 +25,7 @@ #include "hw/arm/boot.h" #include "sysemu/sysemu.h" #include "qom/object.h" +#include =20 #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS = */ #define MVBAR_ADDR 0x400 /* secure vectors */ @@ -200,6 +201,29 @@ static void reset_secondary(ARMCPU *cpu, const struct = arm_boot_info *info) cpu_set_pc(cs, info->smp_loader_start); } =20 +static void raspi4_modify_dtb(const struct arm_boot_info *info, void *fdt) +{ + int offset; + + offset =3D fdt_node_offset_by_compatible(fdt, -1, "brcm,genet-v5"); + if (offset >=3D 0) { + /* FIXME we shouldn't nop the parent */ + offset =3D fdt_parent_offset(fdt, offset); + if (offset >=3D 0) { + if (!fdt_nop_node(fdt, offset)) { + warn_report("dtc: bcm2838-genet removed!"); + } + } + } + + offset =3D fdt_node_offset_by_compatible(fdt, -1, "brcm,avs-tmon-bcm28= 38"); + if (offset >=3D 0) { + if (!fdt_nop_node(fdt, offset)) { + warn_report("dtc: bcm2838-tmon removed!"); + } + } +} + static void setup_boot(MachineState *machine, RaspiProcessorId processor_i= d, size_t ram_size) { @@ -234,6 +258,9 @@ static void setup_boot(MachineState *machine, RaspiProc= essorId processor_id, } s->binfo.secondary_cpu_reset_hook =3D reset_secondary; } + if (processor_id >=3D PROCESSOR_ID_BCM2838) { + s->binfo.modify_dtb =3D raspi4_modify_dtb; + } =20 /* If the user specified a "firmware" image (e.g. UEFI), we bypass * the normal Linux boot process --=20 2.26.2