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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id v4sm7231835wmg.35.2020.10.17.07.03.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:03:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vLpi4Ok952k/O5t7O1lK6hwZKOdIsy56EvHrjOgW/9g=; b=QI6AoIedhod/25yyws8sXRpP3Ab6b83I/zWtfQlU3GMjCyt1W6Lqlk8eBKIJEZMUtj N1pL2HUoVYvPFM+DPoVkC8FZdlB9GXQ1QKajpuOQZ1A68Tl1p1wm5M03KZE2RzKiqS3D KBGaIC0ErWCpQfh0L0+GjEcqYSfJrnqULvfm1iDCgZpIohnpkLMZqI/2bxvzoyS9Ap97 0YalK/tfMU+Xsw/b39xz9bdpkCycDYjAoMWbcNNXWzczY7VJ3ffuReR68fmWOTFzs74g hSBfXXoEBoWYuvUwkJaaxxxxe+88Atr9bnk2SRu512Do7B4MTH1EyVgIV1CDFVVSW9po ElWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=vLpi4Ok952k/O5t7O1lK6hwZKOdIsy56EvHrjOgW/9g=; b=rCU2jsIJCqcDSF8XT4OKuBscgldiv6ytKYkFkdMNzR/f+UhuO6VyVMUY8PJQUVaPgq 31dH0zyZ3079bJQEZTIytKcI/f3/kivQkPhCSNjuqDiQ63VXL74VcEejvl7Gdwlc4yxO ShctvAA1N+6Nu1fnDybiqy9uo5pKsHsFFKGEDo0AprY7/oEVt5RDiXEdajIrV865jS3I 1a3zLrST0+B6f+qaBNh8Rg2MDIwxh2UxHREFV527CR8KMiN6IfR3FGRh0Ffxo/afScj8 QS7dcQyWojwVk0DYcYxiNcpljmefsWTxvsA5N4pKJiYAQclWopthJaQkObXABAx8wrx6 3arA== X-Gm-Message-State: AOAM533+yE1UilDgFNegS/hbixXMp2qXHm+1TopAYrQKTm5izyxduB6p fFUNKSdDQkL2H/0AbCN2FQ4= X-Google-Smtp-Source: ABdhPJxFe5x167yezDjoEusJwDopfpCmIr6Ukt3R4uGJhJLT6p5SOYhg0gy4lHE2ckaCSGXseGn7rw== X-Received: by 2002:a1c:cc07:: with SMTP id h7mr9065305wmb.55.1602943403353; Sat, 17 Oct 2020 07:03:23 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Huacai Chen , Paul Burton , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aurelien Jarno , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 08/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 1) Date: Sat, 17 Oct 2020 16:02:07 +0200 Message-Id: <20201017140243.1078718-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) From: Jiaxun Yang LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE as "load/store quad word" and "shifted load/store" groups of instructions. This patch add implementation of these instructions: gslq: load 16 bytes to GPR gssq: store 16 bytes from GPR gslqc1: load 16 bytes to FPR gssqc1: store 16 bytes from FPR Details of Loongson-EXT is here: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen Message-Id: <1602831120-3377-3-git-send-email-chenhc@lemote.com> [PMD: Restrict t1 variable to TARGET_MIPS64, remove unused t2/fp0] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 86 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/target/mips/translate.c b/target/mips/translate.c index b4d009078e0..e83954d782f 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -460,6 +460,17 @@ enum { R6_OPC_SCD =3D 0x27 | OPC_SPECIAL3, }; =20 +/* Loongson EXT load/store quad word opcodes */ +#define MASK_LOONGSON_GSLSQ(op) (MASK_OP_MAJOR(op) | (op & 0x802= 0)) +enum { + OPC_GSLQ =3D 0x0020 | OPC_LWC2, + OPC_GSLQC1 =3D 0x8020 | OPC_LWC2, + OPC_GSSHFL =3D OPC_LWC2, + OPC_GSSQ =3D 0x0020 | OPC_SWC2, + OPC_GSSQC1 =3D 0x8020 | OPC_SWC2, + OPC_GSSHFS =3D OPC_SWC2, +}; + /* BSHFL opcodes */ #define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)= )) =20 @@ -5910,6 +5921,79 @@ no_rd: tcg_temp_free_i64(t1); } =20 +static void gen_loongson_lswc2(DisasContext *ctx, int rt, + int rs, int rd) +{ + TCGv t0; +#if defined(TARGET_MIPS64) + TCGv t1; + int lsq_rt1 =3D ctx->opcode & 0x1f; + int lsq_offset =3D sextract32(ctx->opcode, 6, 9) << 4; +#endif + + t0 =3D tcg_temp_new(); + + switch (MASK_LOONGSON_GSLSQ(ctx->opcode)) { +#if defined(TARGET_MIPS64) + case OPC_GSLQ: + t1 =3D tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, lsq_offset); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + gen_store_gpr(t1, rt); + gen_store_gpr(t0, lsq_rt1); + tcg_temp_free(t1); + break; + case OPC_GSLQC1: + check_cp1_enabled(ctx); + t1 =3D tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, lsq_offset); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + gen_store_fpr64(ctx, t1, rt); + gen_store_fpr64(ctx, t0, lsq_rt1); + tcg_temp_free(t1); + break; + case OPC_GSSQ: + t1 =3D tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, lsq_offset); + gen_load_gpr(t1, rt); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); + gen_load_gpr(t1, lsq_rt1); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + tcg_temp_free(t1); + break; + case OPC_GSSQC1: + check_cp1_enabled(ctx); + t1 =3D tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, lsq_offset); + gen_load_fpr64(ctx, t1, rt); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + gen_base_offset_addr(ctx, t0, rs, lsq_offset + 8); + gen_load_fpr64(ctx, t1, lsq_rt1); + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ | + ctx->default_tcg_memop_mask); + tcg_temp_free(t1); + break; +#endif + default: + MIPS_INVAL("loongson_gslsq"); + generate_exception_end(ctx, EXCP_RI); + break; + } + tcg_temp_free(t0); +} + /* Traps */ static void gen_trap(DisasContext *ctx, uint32_t opc, int rs, int rt, int16_t imm) @@ -30774,6 +30858,8 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) /* OPC_BC, OPC_BALC */ gen_compute_compact_branch(ctx, op, 0, 0, sextract32(ctx->opcode << 2, 0, 28)= ); + } else if (ctx->insn_flags & ASE_LEXT) { + gen_loongson_lswc2(ctx, rt, rs, rd); } else { /* OPC_LWC2, OPC_SWC2 */ /* COP2: Not implemented. */ --=20 2.26.2