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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id y5sm8845509wrw.52.2020.10.17.07.06.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:06:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7NPFG3sCe3Q0DWcvvpgh0QRrJIh4WkqraUDSbppp/5Q=; b=BlVy2jYZOLpKi+x8pl78DPw4PuPFNK5Hr9hii+HYldLiagJTlC0DDGRy7zPWkJs6V3 ibVI2ftO1N+gt7++lwBGO/Q4pfFz67tJf8/1lom2sc9nmN+VSWw5pKqlYobRAqPoCO2K +WMHc9bC2Ysxhl9FINkqzJcMZoZUqkPgzWrAAMgdenB0cxRJhNTKR/yGUFD1hvhdmxDG tcPdZMtRE5YtTgG4SNrIlXrjLOmBCsX1oAduAOrBFBIgBG/66SrZXxEiwGuOkJtn1rlc FntM/3Xcf2wYrC3zyqe54H7rernF6exXQpT96pyHzSEeWWDdx3obTfl+lAIv1F71RkMd dXpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=7NPFG3sCe3Q0DWcvvpgh0QRrJIh4WkqraUDSbppp/5Q=; b=XUyoreoIFA71yPuzvaG2onZKDsP6e+mzBi14M44AyIRf/Au92xdrsSPIZDRUVztjT4 jaRuFbTt5AUksAL5Q2In6zMba0zflnBFFgp2RFmH80qPwClHMHjvqm7xL+pt7PRby8Bo VWLr/2QuSA+MLlL7XJN2bIqwcpX3MwhmDKcKrg/NFcTCmUzHK9GVYtqkfIl72WWOjMwJ VT1SJBTlanMNCgVqZCRSJeyKGUwz8c7cfbvPsPy33oJDy9WOuJzbx9XDg34qfi/oAGuH DEkdu+B2n5uZipG1WrDaP2a+o1YxMgjd1EmQVsHqTeud3RsnQLr9Hs4WuSpFcnMvOkb+ LRWg== X-Gm-Message-State: AOAM530OyIyEURYZ9kbzZg5dnOYaqdlq2qrLwsJitdJNnDvZiC91hrsP o3c++VJ46ECfABQym9tMkRY= X-Google-Smtp-Source: ABdhPJwvjfQ7VDOjq7eWWyfNjaZNjJPALCxXvEfbifxYhb2RhMAky8HIvmkfSnFx3t13BMNPBposZg== X-Received: by 2002:a5d:4051:: with SMTP id w17mr10218317wrp.24.1602943571161; Sat, 17 Oct 2020 07:06:11 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Huacai Chen , Paul Burton , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aurelien Jarno , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Victor Kamensky , Richard Henderson Subject: [PULL 44/44] target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64) Date: Sat, 17 Oct 2020 16:02:43 +0200 Message-Id: <20201017140243.1078718-45-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Per "MIPS32 34K Processor Core Family Software User's Manual, Revision 01.13" page 8 in "Joint TLB (JTLB)" section: "The JTLB is a fully associative TLB cache containing 16, 32, or 64-dual-entries mapping up to 128 virtual pages to their corresponding physical addresses." There is no particular reason to restrict the 34Kf core model to 16 TLB entries, so raise its config to 64. This is helpful for other projects, in particular the Yocto Project: Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit MIPS CI loop. It was observed that in this case CI test execution time was almost twice longer than 64bit MIPS variant that runs under MIPS64R2-generic model. It was investigated and concluded that the difference in number of TLBs 16 in 34Kf case vs 64 in MIPS64R2-generic is responsible for most of CI real time execution difference. Because with 16 TLBs linux user-land trashes TLB more and it needs to execute more instructions in TLB refill handler calls, as result it runs much longer. (https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html) Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=3D13992 Reported-by: Victor Kamensky Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20201016133317.553068-1-f4bug@amsat.org> --- target/mips/translate_init.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index c735b2bf667..fb5a9b38e5d 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -254,7 +254,7 @@ const mips_def_t mips_defs[] =3D .CP0_PRid =3D 0x00019500, .CP0_Config0 =3D MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 =3D MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU= ) | + .CP0_Config1 =3D MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU= ) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA)= | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA)= | (1 << CP0C1_CA), --=20 2.26.2