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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id x21sm8374368wmi.3.2020.10.17.07.04.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TadARjLJ/nsMStaSHgFw9Eo2VdlMk7HODNJ8C7SZvtU=; b=bBTJltPSYyk6fzuDWmONLzc21U0QmrLswc5nggfsj6YJElBYXQw6qQSZcseJpxlVG1 FOEF9amcoRivMQL0RXSfsF26Jx8op1ar8r9VwvxMpNq3qBcMftULSX+Ugsy0QW9v6TOR RDZNVhl6mNfdND1SJi94fOb3oYqykTKowMo/IO9JrzFZWzR/VM40NBZ44lgwjYkqtSu0 qW0+IPW9wfUplCE9djOMnV2/SNLT68yI3kMGyZqVs3WMTu/rbQHaHtX05q5VTpyGjx09 UxVxnn0NTfa/jHQWuH8/aj3jstFIt1lZ3ENsCjHEsR8FGqcrfKGMKhTBuw4FCk4Ps+Ns TI5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=TadARjLJ/nsMStaSHgFw9Eo2VdlMk7HODNJ8C7SZvtU=; b=myCA9PHpecFtObpzws376adfC+A1NmKQ60X7v9C8wUSawg8Nqi7dMjclLorgdw94Bw /VNkUXCT/gCqynDzgDNU6lk1w8mGnR+a25qS+Fa42/7/Ceupny3v6KaD1C48i6vzpVWb 6XEegdHlbeaM8QChwFjlZ1kxLpMOB42No209EQXC5J1TKvxLFoPoHtKGOwe5cuwzYJ3i qCdfkzMa77RBy2oDKjuvtH2mpbbI/3XVNWsDLtw99ZjD/JyzULqvzRvqhBjM9PJHbpOI bE10H6bULmU/qCFR+5GVpaxllzpcQHGS+NEBSS5f3sHhcOQvT5HcJ5/+xBEBozqqKekr RpHQ== X-Gm-Message-State: AOAM530enoAW80z9NeUJFo78+iWZphBSPuBPsRgSwyq6PV37dxTH2XKZ NIWYrEnr85417NlYbarpyHo= X-Google-Smtp-Source: ABdhPJyMLICiN8XfsjOPCptb8uC0gmIw7ENPj+i9oQvsXHoqAtdc0o1ikPhnrAV+YT1Um3mGFvtNjQ== X-Received: by 2002:a1c:63c3:: with SMTP id x186mr9070526wmb.66.1602943496369; Sat, 17 Oct 2020 07:04:56 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Huacai Chen , Paul Burton , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aurelien Jarno , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 28/44] hw/mips/malta: Set CPU frequency to 320 MHz Date: Sat, 17 Oct 2020 16:02:27 +0200 Message-Id: <20201017140243.1078718-29-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The CoreLV card with ID 0x420's CPU clocked at 320 MHz. Create a 'cpuclk' output clock and connect it to the CPU input clock. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20201012095804.3335117-20-f4bug@amsat.org> --- hw/mips/malta.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 4019c9dc1a8..1e2b750719e 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -26,6 +26,7 @@ #include "qemu/units.h" #include "qemu-common.h" #include "cpu.h" +#include "hw/clock.h" #include "hw/southbridge/piix.h" #include "hw/isa/superio.h" #include "hw/char/serial.h" @@ -57,6 +58,7 @@ #include "sysemu/kvm.h" #include "hw/semihosting/semihost.h" #include "hw/mips/cps.h" +#include "hw/qdev-clock.h" =20 #define ENVP_ADDR 0x80002000l #define ENVP_NB_ENTRIES 16 @@ -94,6 +96,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA) struct MaltaState { SysBusDevice parent_obj; =20 + Clock *cpuclk; MIPSCPSState cps; qemu_irq i8259[ISA_NUM_IRQS]; }; @@ -1159,7 +1162,7 @@ static void main_cpu_reset(void *opaque) } } =20 -static void create_cpu_without_cps(MachineState *ms, +static void create_cpu_without_cps(MachineState *ms, MaltaState *s, qemu_irq *cbus_irq, qemu_irq *i8259_irq) { CPUMIPSState *env; @@ -1167,7 +1170,7 @@ static void create_cpu_without_cps(MachineState *ms, int i; =20 for (i =3D 0; i < ms->smp.cpus; i++) { - cpu =3D MIPS_CPU(cpu_create(ms->cpu_type)); + cpu =3D mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk); =20 /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); @@ -1189,6 +1192,7 @@ static void create_cps(MachineState *ms, MaltaState *= s, &error_fatal); object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus, &error_fatal); + qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); =20 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); @@ -1203,7 +1207,7 @@ static void mips_create_cpu(MachineState *ms, MaltaSt= ate *s, if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) { create_cps(ms, s, cbus_irq, i8259_irq); } else { - create_cpu_without_cps(ms, cbus_irq, i8259_irq); + create_cpu_without_cps(ms, s, cbus_irq, i8259_irq); } } =20 @@ -1421,10 +1425,19 @@ void mips_malta_init(MachineState *machine) pci_vga_init(pci_bus); } =20 +static void mips_malta_instance_init(Object *obj) +{ + MaltaState *s =3D MIPS_MALTA(obj); + + s->cpuclk =3D qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); + clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */ +} + static const TypeInfo mips_malta_device =3D { .name =3D TYPE_MIPS_MALTA, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(MaltaState), + .instance_init =3D mips_malta_instance_init, }; =20 static void mips_malta_machine_init(MachineClass *mc) --=20 2.26.2