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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id t12sm8996734wrm.25.2020.10.17.07.04.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gcSFIGw0lHwM+wP/lVQPID0kXeFa2b1r5NkvHKAKJbE=; b=MpwL15+QPtIZ6xCu9ADESAqOwHrqfRTIZdDmRTaFxyMJUMPCzJnwXCMdYuYQUH4sRD AQYDr0mxi0MePgS2QoZYDvVa8jepqDiH6nYmxJo6DkWQep9nHkjBKkuYk417keIAL+z7 mGz/oWrNdG0wzGvx38Dds5ERj5vv0noEls5of+E6bepKb1T6kiSnTvQhA/7HHnyw+Gtu 9YufzxmlUA6fOrM64zj5JIASKnfE3hb/7F1/+BYQdLlUXG1Tx8C1r2seCxfa7xJNlMyx kr8jTeN+s0NB9Zwy3mHOv9F/gMGXurpkGoBxrR6hlTAgJ9tRZUdEBcjPOafFJf1pomhs l8nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=gcSFIGw0lHwM+wP/lVQPID0kXeFa2b1r5NkvHKAKJbE=; b=eDnTKsV81kON2T6fGHOP+igdSCgT3nqBwnBgtEptr6os+iNSnk1X7ucp393kjaJYt5 nS3dTdOyVTcx6mxTGnH3PehZLzuvchoqjyYTuvLoFxt1SNM+GG8d/+mZNyRbQn2+jT/Y K5OidhFGqpCuWkzRdEsbw3y1yiZuKShuT63kJOKnDmaL8jnXqVYuyuGUQi2QhtpLxCbl 5LSULMsXVwWY2N8Lt+EV0AHaItLzW1aP4ONM1dNn7Q2sJaK5nUocKNLFY6IXOLxEny+1 gmIwKbOGD0nh5evIaQQlSxV6DrRxYMrmYxx45MTxWVcsjGcUBFlrA2JAWg5fSn1PLBdV iNog== X-Gm-Message-State: AOAM533WP48WEmXoPyV0zUcrDy88YFHaOIiKKJL6Awapq/wtf9JDviVE GWq49RQXOOsaKMPxNwQvii8= X-Google-Smtp-Source: ABdhPJzRtyBDoPYqNfT0aWPyzm/wJqvJoIlqEmjN9V64pFenmfVscg+msq3e/MvC4ANacWN21ug0Rw== X-Received: by 2002:a05:6000:1112:: with SMTP id z18mr10086418wrw.3.1602943454712; Sat, 17 Oct 2020 07:04:14 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Huacai Chen , Paul Burton , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aurelien Jarno , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 19/44] target/mips/cpu: Make cp0_count_rate a property Date: Sat, 17 Oct 2020 16:02:18 +0200 Message-Id: <20201017140243.1078718-20-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Since not all CPU implementations use a cores use a CP0 timer at half the frequency of the CPU, make this variable a property. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20201012095804.3335117-11-f4bug@amsat.org> --- target/mips/cpu.h | 9 +++++++++ target/mips/cpu.c | 19 +++++++++++-------- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 085a88e9550..baeceb892ef 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1151,6 +1151,7 @@ struct CPUMIPSState { /** * MIPSCPU: * @env: #CPUMIPSState + * @cp0_count_rate: rate at which the coprocessor 0 counter increments * * A MIPS CPU. */ @@ -1161,6 +1162,14 @@ struct MIPSCPU { =20 CPUNegativeOffsetState neg; CPUMIPSState env; + /* + * The Count register acts as a timer, incrementing at a constant rate, + * whether or not an instruction is executed, retired, or any forward + * progress is made through the pipeline. The rate at which the counter + * increments is implementation dependent, and is a function of the + * pipeline clock of the processor, not the issue width of the process= or. + */ + unsigned cp0_count_rate; }; =20 =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 46188139b7b..461edfe22b7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -26,7 +26,7 @@ #include "qemu/module.h" #include "sysemu/kvm.h" #include "exec/exec-all.h" - +#include "hw/qdev-properties.h" =20 static void mips_cpu_set_pc(CPUState *cs, vaddr value) { @@ -135,12 +135,7 @@ static void mips_cpu_disas_set_info(CPUState *s, disas= semble_info *info) } =20 /* - * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz - * and a CP0 timer running at half the clock of the CPU (cp0_count_rate = =3D 2). - * - * TIMER_FREQ_HZ =3D CPU_FREQ_HZ / CP0_COUNT_RATE =3D 200 MHz / 2 =3D 100 = MHz - * - * TIMER_PERIOD_NS =3D 1 / TIMER_FREQ_HZ =3D 10 ns + * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz. */ #define CPU_FREQ_HZ_DEFAULT 200000000 #define CP0_COUNT_RATE_DEFAULT 2 @@ -149,7 +144,7 @@ static void mips_cp0_period_set(MIPSCPU *cpu) { CPUMIPSState *env =3D &cpu->env; =20 - env->cp0_count_ns =3D muldiv64(NANOSECONDS_PER_SECOND, CP0_COUNT_RATE_= DEFAULT, + env->cp0_count_ns =3D muldiv64(NANOSECONDS_PER_SECOND, cpu->cp0_count_= rate, CPU_FREQ_HZ_DEFAULT); } =20 @@ -202,6 +197,13 @@ static ObjectClass *mips_cpu_class_by_name(const char = *cpu_model) return oc; } =20 +static Property mips_cpu_properties[] =3D { + /* CP0 timer running at half the clock of the CPU */ + DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate, + CP0_COUNT_RATE_DEFAULT), + DEFINE_PROP_END_OF_LIST() +}; + static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(c); @@ -211,6 +213,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset); + device_class_set_props(dc, mips_cpu_properties); =20 cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; --=20 2.26.2