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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id z11sm8559575wrh.70.2020.10.17.07.04.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:04:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sUvsBgE8lqeGgpqBP2TiIkm6s4bhzj/3ycAdv64yLQA=; b=Pp7diaAgsS4FJ7mRd+CTmuBBGj9+4eZFWSgA7UjfBNWwNRCjejmzgKhcTs4FopZmFI q57zf1mmSZB1FSB5rgr0/H6XPskLG6qyKl+CXIrtY5AcAjJCF9MC6bZUsgOoBMFJjrlE iSZVbizlXj+CO5aYYq1RJzpPwqUeCnFXTaATcCyZbL/syGmtMhiZcifm5yE4ZLQFxOuN CqrqSwHxolrTTsvvwLjUMwYfLcGvXPIO1hYoRMQTQLvyeF53a9zAhQkdRhZSZlGV/R8I lSlW5pdVdr8Cy3a6K7xTplCE78lVyJ7cChNNj+d6TTUX/S6i/2YLIkp5qUlqdNbVzpbZ SFkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sUvsBgE8lqeGgpqBP2TiIkm6s4bhzj/3ycAdv64yLQA=; b=Y8AYkj1Gou95LFobXGrjjcyfNQFKlPFAQv/MbDd5rVdC6nmyZKqy1PLm/+PfIZoXEI v8eVA8UV4ub1vSm75EQNctzQNYObwlDF3kW9Ni3P8txBTTICqtW2XRdXGx1wNp6rAY4Q vhJ9+ngfXBUfjEylJvvJCprZGns4LWbHbij+grCZq4ZIqyyPZxEsgihLrEftvVXAkD02 bYeLg7P/p7HeAd0Alxz+3SIY/nv08u91Ic3bkCRvq4pDPI+O912oBPJ8Pb0NOi0Z1Ra3 tfIxxmJJQjcsgP0Ojs4UVy9qWGrzz1KmYIt4clS5SgxXMn8HFfqYqrGF7jBK+mhpgYCz r1XA== X-Gm-Message-State: AOAM530G3iZ3AOWc9JFEuOpO2rFNX2eTRqXBLWsXZ41LC/buPftLb2z1 eC3uRMdmwRZYmVukt1egFQI= X-Google-Smtp-Source: ABdhPJxsueWVIAKlVmpmTj2PWDv7ldxqtapggtb6nMpfS2wwKjTxCzVRsLtXL0K1ofNTwSlCh/Z0Vw== X-Received: by 2002:adf:84a5:: with SMTP id 34mr10949869wrg.152.1602943445414; Sat, 17 Oct 2020 07:04:05 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Huacai Chen , Paul Burton , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aurelien Jarno , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 17/44] target/mips: Move cp0_count_ns to CPUMIPSState Date: Sat, 17 Oct 2020 16:02:16 +0200 Message-Id: <20201017140243.1078718-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Currently the CP0 timer period is fixed at 10 ns, corresponding to a fixed CPU frequency of 200 MHz (using half the speed of the CPU). In few commits we will be able to use a different CPU frequency. In preparation, move the cp0_count_ns variable to CPUMIPSState so we can modify it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Jiaxun Yang Message-Id: <20201012095804.3335117-9-f4bug@amsat.org> --- target/mips/cpu.h | 1 + target/mips/cp0_timer.c | 23 ++++++----------------- target/mips/cpu.c | 21 +++++++++++++++++++++ 3 files changed, 28 insertions(+), 17 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 7cf7f5239f7..085a88e9550 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1145,6 +1145,7 @@ struct CPUMIPSState { struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ target_ulong exception_base; /* ExceptionBase input to the core */ + uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */ }; =20 /** diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index 6fec5fe0ff7..5ec0d6249e9 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -27,18 +27,6 @@ #include "sysemu/kvm.h" #include "internal.h" =20 -/* - * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz - * and a CP0 timer running at half the clock of the CPU (cp0_count_rate = =3D 2). - * - * TIMER_FREQ_HZ =3D CPU_FREQ_HZ / CP0_COUNT_RATE =3D 200 MHz / 2 =3D 100 = MHz - * - * TIMER_PERIOD_NS =3D 1 / TIMER_FREQ_HZ =3D 10 ns - */ -#define CPU_FREQ_HZ_DEFAULT 200000000 -#define CP0_COUNT_RATE_DEFAULT 2 -#define TIMER_PERIOD 10 /* 1 / (CPU_FREQ_HZ / CP0_COUNT_RATE) = */ - /* MIPS R4K timer */ static void cpu_mips_timer_update(CPUMIPSState *env) { @@ -47,8 +35,8 @@ static void cpu_mips_timer_update(CPUMIPSState *env) =20 now_ns =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); wait =3D env->CP0_Compare - env->CP0_Count - - (uint32_t)(now_ns / TIMER_PERIOD); - next_ns =3D now_ns + (uint64_t)wait * TIMER_PERIOD; + (uint32_t)(now_ns / env->cp0_count_ns); + next_ns =3D now_ns + (uint64_t)wait * env->cp0_count_ns; timer_mod(env->timer, next_ns); } =20 @@ -76,7 +64,7 @@ uint32_t cpu_mips_get_count(CPUMIPSState *env) cpu_mips_timer_expire(env); } =20 - return env->CP0_Count + (uint32_t)(now_ns / TIMER_PERIOD); + return env->CP0_Count + (uint32_t)(now_ns / env->cp0_count_ns); } } =20 @@ -92,7 +80,8 @@ void cpu_mips_store_count(CPUMIPSState *env, uint32_t cou= nt) } else { /* Store new count register */ env->CP0_Count =3D count - - (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PE= RIOD); + (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / + env->cp0_count_ns); /* Update timer timer */ cpu_mips_timer_update(env); } @@ -119,7 +108,7 @@ void cpu_mips_stop_count(CPUMIPSState *env) { /* Store the current value */ env->CP0_Count +=3D (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / - TIMER_PERIOD); + env->cp0_count_ns); } =20 static void mips_timer_cb(void *opaque) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e86cd065483..84b727fefa8 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -134,6 +134,25 @@ static void mips_cpu_disas_set_info(CPUState *s, disas= semble_info *info) } } =20 +/* + * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz + * and a CP0 timer running at half the clock of the CPU (cp0_count_rate = =3D 2). + * + * TIMER_FREQ_HZ =3D CPU_FREQ_HZ / CP0_COUNT_RATE =3D 200 MHz / 2 =3D 100 = MHz + * + * TIMER_PERIOD_NS =3D 1 / TIMER_FREQ_HZ =3D 10 ns + */ +#define CPU_FREQ_HZ_DEFAULT 200000000 +#define CP0_COUNT_RATE_DEFAULT 2 +#define TIMER_PERIOD_DEFAULT 10 /* 1 / (CPU_FREQ_HZ / CP0_COUNT_RATE) = */ + +static void mips_cp0_period_set(MIPSCPU *cpu) +{ + CPUMIPSState *env =3D &cpu->env; + + env->cp0_count_ns =3D TIMER_PERIOD_DEFAULT; +} + static void mips_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -141,6 +160,8 @@ static void mips_cpu_realizefn(DeviceState *dev, Error = **errp) MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 + mips_cp0_period_set(cpu); + cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.26.2