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[83.52.172.117]) by smtp.gmail.com with ESMTPSA id 24sm7284039wmg.8.2020.10.17.07.03.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2020 07:03:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OSp3zRmHarSiGKoLWGfVF0cWMHS0w9Z8Zx5+7o1qy80=; b=oOszRg2xS8PAnc3qzG10flRDpOTzWvT3YzsGr48xb2GWVqM+CG16sv6zsRvq9FY5RH ziRpZ0eZAKZfrKGGyxBsamDXRrrdwmmPEKgDFpwTG6GgdEx4l975qB3hJmywbFzL9wWB 13aC6j4NOoO2r6GeEvvbWRgtKN+0MSr0COK+wviEcw1YWY2TGn7lq14YomD4LPNnC6ME jCLEh7cHpfYvtOWdw6s8KlAx1qon4F3TG73dVeoK/AwYRZgiPJfrHtN/wv1L87wtBxyw RocuRrlT0Nu2UWrrklcwZlh6CRyTikpTLPFgoSZ/zknXaheY45xxC9P5ALsp9nXkezlt 7aOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=OSp3zRmHarSiGKoLWGfVF0cWMHS0w9Z8Zx5+7o1qy80=; b=llSp9TrYozxeVh6cR/Pw7cCdyPht29EAPH9NPD3G12U96vmstPxbKhMVtJbiDAeGeQ I4YD1mjp2zrfRSOjLOV9G14Y4GqyRVuOnvAPg7hbwKqZPVeXI/LIlpXPv1ovveimYV0B OJw1UjKgibUAId88jDD4PbXYoJBEO2sAc1i8SrW/VyPSb1y8MD3HQ+ArdcNahpq+ZF/9 t7rzPNQ+lPZRZHcfd5wkhaDZ9+FdGoN6SqiKDx8TCKd5qtws3d9yKI/Z+NyczpY2vMXq gbKdbEdUDEV5fPUFNUs5p5dysh/Kubhuppb1FZbnra2gRLz4r39mfRLMlVZ3CpNRByme LR6w== X-Gm-Message-State: AOAM5329ERHpuxmUcRsyOGLXItmTaQ3HfqCkGlyNgNX9ko7W0/UjtgAr 7fQVEl/oQbKECAFd/sTruymx3EviU5w= X-Google-Smtp-Source: ABdhPJy35ojWNF+MRnOwgt8mjVHg/+6HIWmo9n5c3IWHWROenbbla51I+0FN+HFP6oGd/gd+xsOIYg== X-Received: by 2002:adf:dfc7:: with SMTP id q7mr9941400wrn.382.1602943408022; Sat, 17 Oct 2020 07:03:28 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Jiaxun Yang , Huacai Chen , Paul Burton , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aurelien Jarno , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 09/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 2) Date: Sat, 17 Oct 2020 16:02:08 +0200 Message-Id: <20201017140243.1078718-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201017140243.1078718-1-f4bug@amsat.org> References: <20201017140243.1078718-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) From: Jiaxun Yang LWC2 & SWC2 have been rewritten by Loongson EXT vendor ASE as "load/store quad word" and "shifted load/store" groups of instructions. This patch add implementation of these instructions: gslwlc1: similar to lwl but RT is FPR instead of GPR gslwrc1: similar to lwr but RT is FPR instead of GPR gsldlc1: similar to ldl but RT is FPR instead of GPR gsldrc1: similar to ldr but RT is FPR instead of GPR gsswlc1: similar to swl but RT is FPR instead of GPR gsswrc1: similar to swr but RT is FPR instead of GPR gssdlc1: similar to sdl but RT is FPR instead of GPR gssdrc1: similar to sdr but RT is FPR instead of GPR Details of Loongson-EXT is here: https://github.com/FlyGoat/loongson-insn/blob/master/loongson-ext.md Signed-off-by: Jiaxun Yang Signed-off-by: Huacai Chen Message-Id: <1602831120-3377-4-git-send-email-chenhc@lemote.com> [PMD: Reuse t1 on MIPS32, reintroduce t2/fp0] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate.c | 182 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 180 insertions(+), 2 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index e83954d782f..b335645e03b 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -471,6 +471,19 @@ enum { OPC_GSSHFS =3D OPC_SWC2, }; =20 +/* Loongson EXT shifted load/store opcodes */ +#define MASK_LOONGSON_GSSHFLS(op) (MASK_OP_MAJOR(op) | (op & 0xc03= f)) +enum { + OPC_GSLWLC1 =3D 0x4 | OPC_GSSHFL, + OPC_GSLWRC1 =3D 0x5 | OPC_GSSHFL, + OPC_GSLDLC1 =3D 0x6 | OPC_GSSHFL, + OPC_GSLDRC1 =3D 0x7 | OPC_GSSHFL, + OPC_GSSWLC1 =3D 0x4 | OPC_GSSHFS, + OPC_GSSWRC1 =3D 0x5 | OPC_GSSHFS, + OPC_GSSDLC1 =3D 0x6 | OPC_GSSHFS, + OPC_GSSDRC1 =3D 0x7 | OPC_GSSHFS, +}; + /* BSHFL opcodes */ #define MASK_BSHFL(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)= )) =20 @@ -5924,12 +5937,13 @@ no_rd: static void gen_loongson_lswc2(DisasContext *ctx, int rt, int rs, int rd) { - TCGv t0; + TCGv t0, t1, t2; + TCGv_i32 fp0; #if defined(TARGET_MIPS64) - TCGv t1; int lsq_rt1 =3D ctx->opcode & 0x1f; int lsq_offset =3D sextract32(ctx->opcode, 6, 9) << 4; #endif + int shf_offset =3D sextract32(ctx->opcode, 6, 8); =20 t0 =3D tcg_temp_new(); =20 @@ -5986,6 +6000,170 @@ static void gen_loongson_lswc2(DisasContext *ctx, i= nt rt, tcg_temp_free(t1); break; #endif + case OPC_GSSHFL: + switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { + case OPC_GSLWLC1: + check_cp1_enabled(ctx); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + t1 =3D tcg_temp_new(); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_andi_tl(t1, t0, 3); +#ifndef TARGET_WORDS_BIGENDIAN + tcg_gen_xori_tl(t1, t1, 3); +#endif + tcg_gen_shli_tl(t1, t1, 3); + tcg_gen_andi_tl(t0, t0, ~3); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_shl_tl(t0, t0, t1); + t2 =3D tcg_const_tl(-1); + tcg_gen_shl_tl(t2, t2, t1); + fp0 =3D tcg_temp_new_i32(); + gen_load_fpr32(ctx, fp0, rt); + tcg_gen_ext_i32_tl(t1, fp0); + tcg_gen_andc_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); +#if defined(TARGET_MIPS64) + tcg_gen_extrl_i64_i32(fp0, t0); +#else + tcg_gen_ext32s_tl(fp0, t0); +#endif + gen_store_fpr32(ctx, fp0, rt); + tcg_temp_free_i32(fp0); + break; + case OPC_GSLWRC1: + check_cp1_enabled(ctx); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + t1 =3D tcg_temp_new(); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_andi_tl(t1, t0, 3); +#ifdef TARGET_WORDS_BIGENDIAN + tcg_gen_xori_tl(t1, t1, 3); +#endif + tcg_gen_shli_tl(t1, t1, 3); + tcg_gen_andi_tl(t0, t0, ~3); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL); + tcg_gen_shr_tl(t0, t0, t1); + tcg_gen_xori_tl(t1, t1, 31); + t2 =3D tcg_const_tl(0xfffffffeull); + tcg_gen_shl_tl(t2, t2, t1); + fp0 =3D tcg_temp_new_i32(); + gen_load_fpr32(ctx, fp0, rt); + tcg_gen_ext_i32_tl(t1, fp0); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); +#if defined(TARGET_MIPS64) + tcg_gen_extrl_i64_i32(fp0, t0); +#else + tcg_gen_ext32s_tl(fp0, t0); +#endif + gen_store_fpr32(ctx, fp0, rt); + tcg_temp_free_i32(fp0); + break; +#if defined(TARGET_MIPS64) + case OPC_GSLDLC1: + check_cp1_enabled(ctx); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + t1 =3D tcg_temp_new(); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_andi_tl(t1, t0, 7); +#ifndef TARGET_WORDS_BIGENDIAN + tcg_gen_xori_tl(t1, t1, 7); +#endif + tcg_gen_shli_tl(t1, t1, 3); + tcg_gen_andi_tl(t0, t0, ~7); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ); + tcg_gen_shl_tl(t0, t0, t1); + t2 =3D tcg_const_tl(-1); + tcg_gen_shl_tl(t2, t2, t1); + gen_load_fpr64(ctx, t1, rt); + tcg_gen_andc_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); + gen_store_fpr64(ctx, t0, rt); + break; + case OPC_GSLDRC1: + check_cp1_enabled(ctx); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + t1 =3D tcg_temp_new(); + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB); + tcg_gen_andi_tl(t1, t0, 7); +#ifdef TARGET_WORDS_BIGENDIAN + tcg_gen_xori_tl(t1, t1, 7); +#endif + tcg_gen_shli_tl(t1, t1, 3); + tcg_gen_andi_tl(t0, t0, ~7); + tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ); + tcg_gen_shr_tl(t0, t0, t1); + tcg_gen_xori_tl(t1, t1, 63); + t2 =3D tcg_const_tl(0xfffffffffffffffeull); + tcg_gen_shl_tl(t2, t2, t1); + gen_load_fpr64(ctx, t1, rt); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); + gen_store_fpr64(ctx, t0, rt); + break; +#endif + default: + MIPS_INVAL("loongson_gsshfl"); + generate_exception_end(ctx, EXCP_RI); + break; + } + break; + case OPC_GSSHFS: + switch (MASK_LOONGSON_GSSHFLS(ctx->opcode)) { + case OPC_GSSWLC1: + check_cp1_enabled(ctx); + t1 =3D tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + fp0 =3D tcg_temp_new_i32(); + gen_load_fpr32(ctx, fp0, rt); + tcg_gen_ext_i32_tl(t1, fp0); + gen_helper_0e2i(swl, t1, t0, ctx->mem_idx); + tcg_temp_free_i32(fp0); + tcg_temp_free(t1); + break; + case OPC_GSSWRC1: + check_cp1_enabled(ctx); + t1 =3D tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + fp0 =3D tcg_temp_new_i32(); + gen_load_fpr32(ctx, fp0, rt); + tcg_gen_ext_i32_tl(t1, fp0); + gen_helper_0e2i(swr, t1, t0, ctx->mem_idx); + tcg_temp_free_i32(fp0); + tcg_temp_free(t1); + break; +#if defined(TARGET_MIPS64) + case OPC_GSSDLC1: + check_cp1_enabled(ctx); + t1 =3D tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + gen_load_fpr64(ctx, t1, rt); + gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx); + tcg_temp_free(t1); + break; + case OPC_GSSDRC1: + check_cp1_enabled(ctx); + t1 =3D tcg_temp_new(); + gen_base_offset_addr(ctx, t0, rs, shf_offset); + gen_load_fpr64(ctx, t1, rt); + gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx); + tcg_temp_free(t1); + break; +#endif + default: + MIPS_INVAL("loongson_gsshfs"); + generate_exception_end(ctx, EXCP_RI); + break; + } + break; default: MIPS_INVAL("loongson_gslsq"); generate_exception_end(ctx, EXCP_RI); --=20 2.26.2