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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id v17sm3856182wrc.23.2020.10.16.06.33.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2020 06:33:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=kjTvXXHneKE+iLOlSjtIgsRLPHz1K53cljjvbS1RzE8=; b=f4lFa8PRWIvtUzdmVuRUntUfeBfTwtmg+/Vv3YM3mM+qeyoMxZdw6LVJNe2XX67CbK aruKz5YwVPTa8IGx0kgCRYj00RRzmzX9rx8TCs8dPdGcDqb1z7WsEO7DnFDamtOOvxPE GZZ+OX5mKKD7IF+kfzPAJLHOr3mn8w8Rp07X95x18XdTS6IQg+lY7TxOfLwkWD/g1NiZ cgHOq3fhLP+UEsFjII5IMoS22SYXvOxavV0pc0VoewcCrsxmCJJVrftiuTS6eSKZLSsz sOVYlz6xkkU83iq2pxFBRzr0A3vIH9XXNzU5zHdiE0HCvWJXFBqVFPOwIwR+hv6NVc2A PdBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=kjTvXXHneKE+iLOlSjtIgsRLPHz1K53cljjvbS1RzE8=; b=dY+m6vwxp5VFuV8cgLxLX2mb9Vk1i4rM8P3CeV7x+mksiRCB+mWh0+6kdjaqvx5nqg bWEIqFtL7eRsiR98JGoARpoVpUXQ7tACh/gKlGh6Z1GlSoEIMvCTa6GhBRrRRQgE7KTv 968cmDts9+H2ps1JwLX57ZPOLp0YtLwkg+avk8bhF230+54f0ualk/I8ADLngNTjaeIi qxP9aY6YQdsvbG/uRuz1OLXcVr2CnayuERGnPv8wdcSK539rZjw+88fk0BrMEo0UEr1b bAvUmfnJjpTNA3aHOr+JcsTe1FQN39Qfy0yVJT7VYbOkT6scsoiKAl1ZiqChEz+Czhd1 yUJA== X-Gm-Message-State: AOAM531uPAt31O3cGSoHG6FUxiHeU5FWsUBek8jJ6d27elprdqpZQIZz M2jTtQQN060mFrsRbeOFcyo= X-Google-Smtp-Source: ABdhPJxasALL/hyCnT2e11Atgt/Hil8biIBuiQL+La7abxrEZKM5qAXayHveSjCXsh1pGqPOht+qLA== X-Received: by 2002:a1c:6a0a:: with SMTP id f10mr4010044wmc.86.1602855199826; Fri, 16 Oct 2020 06:33:19 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Victor Kamensky Cc: Aurelien Jarno , Jiaxun Yang , Richard Purdie , Khem Raj , Richard Henderson , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v3] target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64) Date: Fri, 16 Oct 2020 15:33:17 +0200 Message-Id: <20201016133317.553068-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Per "MIPS32 34K Processor Core Family Software User's Manual, Revision 01.13" page 8 in "Joint TLB (JTLB)" section: "The JTLB is a fully associative TLB cache containing 16, 32, or 64-dual-entries mapping up to 128 virtual pages to their corresponding physical addresses." There is no particular reason to restrict the 34Kf core model to 16 TLB entries, so raise its config to 64. This is helpful for other projects, in particular the Yocto Project: Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit MIPS CI loop. It was observed that in this case CI test execution time was almost twice longer than 64bit MIPS variant that runs under MIPS64R2-generic model. It was investigated and concluded that the difference in number of TLBs 16 in 34Kf case vs 64 in MIPS64R2-generic is responsible for most of CI real time execution difference. Because with 16 TLBs linux user-land trashes TLB more and it needs to execute more instructions in TLB refill handler calls, as result it runs much longer. (https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html) Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=3D13992 Reported-by: Victor Kamensky Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- v3: KISS Supersedes: <20201015224746.540027-1-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/translate_init.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index 637caccd890..ad21756f4d9 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -254,7 +254,7 @@ const mips_def_t mips_defs[] =3D .CP0_PRid =3D 0x00019500, .CP0_Config0 =3D MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 =3D MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU= ) | + .CP0_Config1 =3D MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU= ) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA)= | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA)= | (1 << CP0C1_CA), --=20 2.26.2