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bh=7ACVkbCMHfzJA49UKgjwrRcB/LzEJuhcX8axetBmujU=; b=HOX/nDOOccRmGNUClP1ADqBz3sVC0pJxEd8gvT1kVfNvGMUpU1Bv4kla4v6gDvR1rSS2aU c6kdMsDhj6vXePrezAv+S90c5pviN/s3YJIpys1sMj51gduud1/6vvWBRtHQ+dwa6RADyo h/3qiVbbH5oVtalDZSp3tydRksAlQ68= X-MC-Unique: wMFSjTKJPqCsz0wnbXfkqA-1 From: Gerd Hoffmann To: qemu-devel@nongnu.org Subject: [PATCH 3/4] microvm: add second ioapic Date: Fri, 16 Oct 2020 13:43:27 +0200 Message-Id: <20201016114328.18835-4-kraxel@redhat.com> In-Reply-To: <20201016114328.18835-1-kraxel@redhat.com> References: <20201016114328.18835-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=kraxel@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=63.128.21.124; envelope-from=kraxel@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/16 03:57:19 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Sergio Lopez , "Michael S. Tsirkin" , Gerd Hoffmann , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add more IRQ lines. Depends on ACPI. Also enable this only with userspace ioapic, not sure whenever the kernel can handle two ioapics. Signed-off-by: Gerd Hoffmann Reviewed-by: Igor Mammedov --- include/hw/i386/ioapic_internal.h | 2 +- include/hw/i386/x86.h | 1 + hw/i386/acpi-common.c | 10 ++++++++++ hw/i386/microvm.c | 30 ++++++++++++++++++++++++++++-- 4 files changed, 40 insertions(+), 3 deletions(-) diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_int= ernal.h index 0ac9e2400d6b..4cebd2e32c9f 100644 --- a/include/hw/i386/ioapic_internal.h +++ b/include/hw/i386/ioapic_internal.h @@ -27,7 +27,7 @@ #include "qemu/notify.h" #include "qom/object.h" =20 -#define MAX_IOAPICS 1 +#define MAX_IOAPICS 2 =20 #define IOAPIC_LVT_DEST_SHIFT 56 #define IOAPIC_LVT_DEST_IDX_SHIFT 48 diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index bfa9cb2a258b..6da57033a875 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -120,6 +120,7 @@ bool x86_machine_is_acpi_enabled(const X86MachineState = *x86ms); typedef struct GSIState { qemu_irq i8259_irq[ISA_NUM_IRQS]; qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; + qemu_irq ioapic2_irq[IOAPIC_NUM_PINS]; } GSIState; =20 qemu_irq x86_allocate_cpu_irq(void); diff --git a/hw/i386/acpi-common.c b/hw/i386/acpi-common.c index 8a769654060e..f0689392a39f 100644 --- a/hw/i386/acpi-common.c +++ b/hw/i386/acpi-common.c @@ -103,6 +103,16 @@ void acpi_build_madt(GArray *table_data, BIOSLinker *l= inker, io_apic->address =3D cpu_to_le32(IO_APIC_DEFAULT_ADDRESS); io_apic->interrupt =3D cpu_to_le32(0); =20 + if (object_property_find(OBJECT(x86ms), "ioapic2")) { + AcpiMadtIoApic *io_apic2; + io_apic2 =3D acpi_data_push(table_data, sizeof *io_apic); + io_apic2->type =3D ACPI_APIC_IO; + io_apic2->length =3D sizeof(*io_apic); + io_apic2->io_apic_id =3D ACPI_BUILD_IOAPIC_ID + 1; + io_apic2->address =3D cpu_to_le32(IO_APIC_DEFAULT_ADDRESS + 0x1000= 0); + io_apic2->interrupt =3D cpu_to_le32(24); + } + if (x86ms->apic_xrupt_override) { intsrcovr =3D acpi_data_push(table_data, sizeof *intsrcovr); intsrcovr->type =3D ACPI_APIC_XRUPT_OVERRIDE; diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 638e95c39e8c..15c3e078a4aa 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -99,7 +99,11 @@ static void microvm_gsi_handler(void *opaque, int n, int= level) { GSIState *s =3D opaque; =20 - qemu_set_irq(s->ioapic_irq[n], level); + if (n >=3D 24) { + qemu_set_irq(s->ioapic2_irq[n - 24], level); + } else { + qemu_set_irq(s->ioapic_irq[n], level); + } } =20 static void create_gpex(MicrovmMachineState *mms) @@ -157,6 +161,7 @@ static void microvm_devices_init(MicrovmMachineState *m= ms) ISABus *isa_bus; ISADevice *rtc_state; GSIState *gsi_state; + bool ioapic2 =3D false; int i; =20 /* Core components */ @@ -165,8 +170,13 @@ static void microvm_devices_init(MicrovmMachineState *= mms) if (mms->pic =3D=3D ON_OFF_AUTO_ON || mms->pic =3D=3D ON_OFF_AUTO_AUTO= ) { x86ms->gsi =3D qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_= PINS); } else { + int pins =3D GSI_NUM_PINS; + if (!kvm_ioapic_in_kernel() && x86_machine_is_acpi_enabled(x86ms))= { + ioapic2 =3D true; + pins +=3D 24; + } x86ms->gsi =3D qemu_allocate_irqs(microvm_gsi_handler, - gsi_state, GSI_NUM_PINS); + gsi_state, pins); } =20 isa_bus =3D isa_bus_new(NULL, get_system_memory(), get_system_io(), @@ -175,6 +185,22 @@ static void microvm_devices_init(MicrovmMachineState *= mms) =20 ioapic_init_gsi(gsi_state, "machine"); =20 + if (ioapic2) { + DeviceState *dev; + SysBusDevice *d; + unsigned int i; + + dev =3D qdev_new(TYPE_IOAPIC); + object_property_add_child(OBJECT(mms), "ioapic2", OBJECT(dev)); + d =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(d, &error_fatal); + sysbus_mmio_map(d, 0, IO_APIC_DEFAULT_ADDRESS + 0x10000); + + for (i =3D 0; i < IOAPIC_NUM_PINS; i++) { + gsi_state->ioapic2_irq[i] =3D qdev_get_gpio_in(dev, i); + } + } + kvmclock_create(true); =20 mms->virtio_irq_base =3D 5; --=20 2.27.0