From nobody Wed May 22 02:23:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1602775236; cv=none; d=zohomail.com; s=zohoarc; b=EJR7SuQIBq2tfhVHIvWewRZGCRCmtg93uFpm1jH+AUvLNalhHSviep9cvZ7jaNEmBUvjLsW21sXf9EnI/lpk3D1tmavuZCSb/XE4/iNSP8OFuNBwtGr97WP/+ZKYOmqINPBsulGBzT2XaVPwn/sx5E3evIGrr+ABPZ6gIHpapgA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602775236; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FR7Wjpqj5kmgPjv/umwo7PltWhBgeKSR7fRK4Hm0S9U=; b=YP7XSUezbvq29knrpWsVB+gYyKNRM8icQ8cWS1SJ402A9v8B8mB6x37t4Xy0zqv0YnIFZAYifJJps+7i8QypSmKrvsWkYE6evo0+kOMBrg7QE9qYY2yphKQZzcexzE8zUWuYs4eJJueymS2yemXqRJo6h/olLwMKuC+ncE5xjOw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16027752367382.1094718979029494; Thu, 15 Oct 2020 08:20:36 -0700 (PDT) Received: from localhost ([::1]:33372 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kT53T-00058V-TO for importer@patchew.org; Thu, 15 Oct 2020 11:20:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49224) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kT51X-0003fS-NY for qemu-devel@nongnu.org; Thu, 15 Oct 2020 11:18:35 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:52944) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kT51V-0005ar-Uz for qemu-devel@nongnu.org; Thu, 15 Oct 2020 11:18:35 -0400 Received: by mail-wm1-x341.google.com with SMTP id e23so3575331wme.2 for ; Thu, 15 Oct 2020 08:18:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j13sm5193286wru.86.2020.10.15.08.18.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2020 08:18:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FR7Wjpqj5kmgPjv/umwo7PltWhBgeKSR7fRK4Hm0S9U=; b=BT6loDg8Kda+NBz2j6LCpStQspp7cEKxn0IID108HCFrJxtEWCG93dd7K9BCnwBOtu /gFTiVMkYUsxiXzHFTwTrgDjMB0ncOdsYT/kFLutPxqTi6D1NFiQRzXugHEkfiAUK18/ L6txIQew8AnuO7aixD39UWxFRgdNMnUgy7OLPmzHOXPbiiFHyXYq3I+Sst3sLwe/gVFK f/Hca7ZcaYdvlGPBPkO6px+MIsiN4yPQClhSKhNqr/ATsZHVCZaDnxfDWzdZv9vaggvF vCJD0KRWk0bLxz/ROzN7Npg/Kw9zjqavZRsvaURURa1upaCQfGqcFZMpTgj2X5lrJVWn Oa7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FR7Wjpqj5kmgPjv/umwo7PltWhBgeKSR7fRK4Hm0S9U=; b=i/ozY92P2HKCzHmOPtUKq8vn9ypk2gNeiEilLYqjovbNgU1CmnrKdd6ogMjz4mDT+e IgRvbAf9lKWuT8mtFPq+Ix/8eThadZQC34Gp1Qln7xhQS7sABrsN2b43DFLO1v0g38LI kYPZaZ7VcLXElcIW66XHonS2yKkWuFUHrDPeAjAzjr43dQgnGV0RWvrC967FKDiM8Enc jSfWB/S8pJY9/r334XLwexG9li/3JAGzmGK1Gsa5CL9SK89xLnkHkMKmVxJiMUr0rWxJ /Kkcgtftib7Mi68T516QK1aiC401KoRwv7dDC96qGm71lxozrwvEByNmXe8eho0y4h4z fEOQ== X-Gm-Message-State: AOAM530Ksti2sFuZ2DVUGOWP0X0Mbql2qsi+HBLymuDQs6cySqb8Oge0 hb+xoMXDAk8waINqHm7GwbBEYDVLxV7u/mUJ X-Google-Smtp-Source: ABdhPJysuXcx0AYHklxvyPbuhViySWqmcoRKE7dIRlXUthuIsaPx8XzDMGrKiAhICLvzwQXPf8S5Og== X-Received: by 2002:a1c:b7c6:: with SMTP id h189mr4891224wmf.154.1602775112597; Thu, 15 Oct 2020 08:18:32 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/2] hw/core/ptimer: Support ptimer being disabled by timer callback Date: Thu, 15 Oct 2020 16:18:28 +0100 Message-Id: <20201015151829.14656-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201015151829.14656-1-peter.maydell@linaro.org> References: <20201015151829.14656-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In ptimer_reload(), we call the callback function provided by the timer device that is using the ptimer. This callback might disable the ptimer. The code mostly handles this correctly, except that we'll still print the warning about "Timer with delta zero, disabling" if the now-disabled timer happened to be set such that it would fire again immediately if it were enabled (eg because the limit/reload value is zero). Suppress the spurious warning message and the unnecessary repeat-deletion of the underlying timer in this case. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/ptimer.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/core/ptimer.c b/hw/core/ptimer.c index c6d2beb1dac..2aa97cb665c 100644 --- a/hw/core/ptimer.c +++ b/hw/core/ptimer.c @@ -117,6 +117,10 @@ static void ptimer_reload(ptimer_state *s, int delta_a= djust) } =20 if (delta =3D=3D 0) { + if (s->enabled =3D=3D 0) { + /* trigger callback disabled the timer already */ + return; + } if (!qtest_enabled()) { fprintf(stderr, "Timer with delta zero, disabling\n"); } --=20 2.20.1 From nobody Wed May 22 02:23:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1602775360; cv=none; d=zohomail.com; s=zohoarc; b=fH+M/jLO4OottLehmPFRu7bLQ4rXpTu461xwiAa6sc81JUDmohe8CTWd85h6cN/74fvYZ0/ds0nFL73e6eAvGRenMQg7x7V/bxQiCy5+AQo6Xp+AA5WPrRipNjECwo6YLHMYb989DIkh5Hj37qcoMd/CHiVXo5lRFVycgiPXSmY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602775360; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=K5iqhaoBhm+BUIzunqt9IAhyHHRHwxEr8NDWFaL6LdQ=; b=ZWE/JPC/LP+vyZDlsf7I2wXBMSiay2NYILdRUjMuDvbV6ZfQfyld5Yxh+WnvD9kuxB4DpY/k8QmMiil6jF6GoUXb9sx4NpQ9HAcwgFeq4sW3cud18tvIsYvWahkQMxNiYLYnV7eG8HTmKNfQOdqa7sO1hO6jGRdpgf1yt7qWDEw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1602775360107120.45789354046576; Thu, 15 Oct 2020 08:22:40 -0700 (PDT) Received: from localhost ([::1]:38966 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kT55S-0007bE-1R for importer@patchew.org; Thu, 15 Oct 2020 11:22:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49248) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kT51Z-0003iD-83 for qemu-devel@nongnu.org; Thu, 15 Oct 2020 11:18:37 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:36402) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kT51X-0005bA-1r for qemu-devel@nongnu.org; Thu, 15 Oct 2020 11:18:36 -0400 Received: by mail-wm1-x342.google.com with SMTP id e2so4125130wme.1 for ; Thu, 15 Oct 2020 08:18:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j13sm5193286wru.86.2020.10.15.08.18.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2020 08:18:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=K5iqhaoBhm+BUIzunqt9IAhyHHRHwxEr8NDWFaL6LdQ=; b=jcqPxRhznjSN+r6hbhr2J6PVqR6Y0Muu39a6Mlbv39tMxJQjDPXken67Gj6C1s3Ak2 TusEWl92UbXsaIxhe0huuRgz0JUWzMpDjySB3jhJqMCeSxXOKbeztECK4wK4Fi2RgOde rGM37BCeoUUcQRnNy5+okOg0bYTHvxa2CIJuvNeRGloKn0F2oeT8Cv/DQEpSWoqaNGrG u7G7GUXrhHCulmhIuRsZLRw/foxoAVoJM4ZT2RnOWgRkHJtF99mFSMUs5qV0R7cEJecb H5VIDgH8nr+Y2AO2IsP7jLya4viqT9KrscoA8d1PB/5IYVtwr1WIxFBC3qk2lQwbTokn u57Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K5iqhaoBhm+BUIzunqt9IAhyHHRHwxEr8NDWFaL6LdQ=; b=WIVS+wEXA3b7TM61wW6zMAyyCfHWg0BlN2uXfIu6xAhOTRawoKIfw3AtdtX1Jc12+u x1F+QdB6yuM4bhOq6V8xRuxWp+d3s2aVfWmmLq7Br3q/oAOX0WyO2etEz4onWENxbSej dUNZa6gUfdfFOwnaGp75BgACfLKQgU6HhM0K5vhYUKOToi9buBMdm3OTrUzZ/q4NYFZe TsW14vNkxTr5uyoEwz6i4j7LgB4MZcmvzzeZfLSijTnpcQn0MXd5VuJs66VNfRLDUz0p 9k8Kq3653MV6RphcbsiD/17JO4lH1YSSwadtFpc5moN8t1sSwxRH/1sulo8Sa3R2oXP4 qs8w== X-Gm-Message-State: AOAM532IXUV/TgKkeFPy0HVfubCd9v+zCKEftgwati7zLX22HcH1mlRZ 9U387sPuf5gtIaj2mYNa9P3FXQ== X-Google-Smtp-Source: ABdhPJw3v2WScQ0Q3Rcj1nWXrRGp8ls/ZoJH85QAt14enm/mauKd/ot5o2jGy98/JVAgp6oRAMVnIA== X-Received: by 2002:a1c:6743:: with SMTP id b64mr4359265wmc.157.1602775113650; Thu, 15 Oct 2020 08:18:33 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/2] hw/timer/armv7m_systick: Rewrite to use ptimers Date: Thu, 15 Oct 2020 16:18:29 +0100 Message-Id: <20201015151829.14656-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201015151829.14656-1-peter.maydell@linaro.org> References: <20201015151829.14656-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The armv7m systick timer is a 24-bit decrementing, wrap-on-zero, clear-on-write counter. Our current implementation has various bugs and dubious workarounds in it (for instance see https://bugs.launchpad.net/qemu/+bug/1872237). We have an implementation of a simple decrementing counter and we put a lot of effort into making sure it handles the interesting corner cases (like "spend a cycle at 0 before reloading") -- ptimer. Rewrite the systick timer to use a ptimer rather than a raw QEMU timer. Unfortunately this is a migration compatibility break, which will affect all M-profile boards. Among other bugs, this fixes https://bugs.launchpad.net/qemu/+bug/1872237 : now writes to SYST_CVR when the timer is enabled correctly do nothing; when the timer is enabled via SYST_CSR.ENABLE, the ptimer code will (because of POLICY_NO_IMMEDIATE_RELOAD) arrange that after one timer tick the counter is reloaded from SYST_RVR and then counts down from there, as the architecture requires. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/timer/armv7m_systick.h | 3 +- hw/timer/armv7m_systick.c | 124 +++++++++++++----------------- 2 files changed, 54 insertions(+), 73 deletions(-) diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_sy= stick.h index 97cb345ddb4..84496faaf96 100644 --- a/include/hw/timer/armv7m_systick.h +++ b/include/hw/timer/armv7m_systick.h @@ -14,6 +14,7 @@ =20 #include "hw/sysbus.h" #include "qom/object.h" +#include "hw/ptimer.h" =20 #define TYPE_SYSTICK "armv7m_systick" =20 @@ -27,7 +28,7 @@ struct SysTickState { uint32_t control; uint32_t reload; int64_t tick; - QEMUTimer *timer; + ptimer_state *ptimer; MemoryRegion iomem; qemu_irq irq; }; diff --git a/hw/timer/armv7m_systick.c b/hw/timer/armv7m_systick.c index a8cec7eb56b..2f192011eb0 100644 --- a/hw/timer/armv7m_systick.c +++ b/hw/timer/armv7m_systick.c @@ -39,26 +39,6 @@ static inline int64_t systick_scale(SysTickState *s) } } =20 -static void systick_reload(SysTickState *s, int reset) -{ - /* The Cortex-M3 Devices Generic User Guide says that "When the - * ENABLE bit is set to 1, the counter loads the RELOAD value from the - * SYST RVR register and then counts down". So, we need to check the - * ENABLE bit before reloading the value. - */ - trace_systick_reload(); - - if ((s->control & SYSTICK_ENABLE) =3D=3D 0) { - return; - } - - if (reset) { - s->tick =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - } - s->tick +=3D (s->reload + 1) * systick_scale(s); - timer_mod(s->timer, s->tick); -} - static void systick_timer_tick(void *opaque) { SysTickState *s =3D (SysTickState *)opaque; @@ -70,10 +50,12 @@ static void systick_timer_tick(void *opaque) /* Tell the NVIC to pend the SysTick exception */ qemu_irq_pulse(s->irq); } - if (s->reload =3D=3D 0) { - s->control &=3D ~SYSTICK_ENABLE; - } else { - systick_reload(s, 0); + if (ptimer_get_limit(s->ptimer) =3D=3D 0) { + /* + * Timer expiry with SYST_RVR zero disables the timer + * (but doesn't clear SYST_CSR.ENABLE) + */ + ptimer_stop(s->ptimer); } } =20 @@ -94,30 +76,11 @@ static MemTxResult systick_read(void *opaque, hwaddr ad= dr, uint64_t *data, s->control &=3D ~SYSTICK_COUNTFLAG; break; case 0x4: /* SysTick Reload Value. */ - val =3D s->reload; + val =3D ptimer_get_limit(s->ptimer); break; case 0x8: /* SysTick Current Value. */ - { - int64_t t; - - if ((s->control & SYSTICK_ENABLE) =3D=3D 0) { - val =3D 0; - break; - } - t =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - if (t >=3D s->tick) { - val =3D 0; - break; - } - val =3D ((s->tick - (t + 1)) / systick_scale(s)) + 1; - /* The interrupt in triggered when the timer reaches zero. - However the counter is not reloaded until the next clock - tick. This is a hack to return zero during the first tick. */ - if (val > s->reload) { - val =3D 0; - } + val =3D ptimer_get_count(s->ptimer); break; - } case 0xc: /* SysTick Calibration Value. */ val =3D 10000; break; @@ -149,39 +112,50 @@ static MemTxResult systick_write(void *opaque, hwaddr= addr, switch (addr) { case 0x0: /* SysTick Control and Status. */ { - uint32_t oldval =3D s->control; + uint32_t oldval; =20 + ptimer_transaction_begin(s->ptimer); + oldval =3D s->control; s->control &=3D 0xfffffff8; s->control |=3D value & 7; + if ((oldval ^ value) & SYSTICK_ENABLE) { - int64_t now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); if (value & SYSTICK_ENABLE) { - if (s->tick) { - s->tick +=3D now; - timer_mod(s->timer, s->tick); - } else { - systick_reload(s, 1); - } + /* + * Always reload the period in case board code has + * changed system_clock_scale. If we ever replace that + * global with a more sensible API then we might be able + * to set the period only when it actually changes. + */ + ptimer_set_period(s->ptimer, systick_scale(s)); + ptimer_run(s->ptimer, 0); } else { - timer_del(s->timer); - s->tick -=3D now; - if (s->tick < 0) { - s->tick =3D 0; - } + ptimer_stop(s->ptimer); } } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) { - /* This is a hack. Force the timer to be reloaded - when the reference clock is changed. */ - systick_reload(s, 1); + ptimer_set_period(s->ptimer, systick_scale(s)); } + ptimer_transaction_commit(s->ptimer); break; } case 0x4: /* SysTick Reload Value. */ - s->reload =3D value; + ptimer_transaction_begin(s->ptimer); + ptimer_set_limit(s->ptimer, value & 0xffffff, 0); + ptimer_transaction_commit(s->ptimer); break; - case 0x8: /* SysTick Current Value. Writes reload the timer. */ - systick_reload(s, 1); + case 0x8: /* SysTick Current Value. */ + /* + * Writing any value clears SYST_CVR to zero and clears + * SYST_CSR.COUNTFLAG. The counter will then reload from SYST_RVR + * on the next clock edge unless SYST_RVR is zero. + */ + ptimer_transaction_begin(s->ptimer); + if (ptimer_get_limit(s->ptimer) =3D=3D 0) { + ptimer_stop(s->ptimer); + } + ptimer_set_count(s->ptimer, 0); s->control &=3D ~SYSTICK_COUNTFLAG; + ptimer_transaction_commit(s->ptimer); break; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -210,10 +184,13 @@ static void systick_reset(DeviceState *dev) */ assert(system_clock_scale !=3D 0); =20 + ptimer_transaction_begin(s->ptimer); s->control =3D 0; - s->reload =3D 0; - s->tick =3D 0; - timer_del(s->timer); + ptimer_stop(s->ptimer); + ptimer_set_count(s->ptimer, 0); + ptimer_set_limit(s->ptimer, 0, 0); + ptimer_set_period(s->ptimer, systick_scale(s)); + ptimer_transaction_commit(s->ptimer); } =20 static void systick_instance_init(Object *obj) @@ -229,18 +206,21 @@ static void systick_instance_init(Object *obj) static void systick_realize(DeviceState *dev, Error **errp) { SysTickState *s =3D SYSTICK(dev); - s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s); + s->ptimer =3D ptimer_init(systick_timer_tick, s, + PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | + PTIMER_POLICY_NO_COUNTER_ROUND_DOWN | + PTIMER_POLICY_NO_IMMEDIATE_RELOAD | + PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT); } =20 static const VMStateDescription vmstate_systick =3D { .name =3D "armv7m_systick", - .version_id =3D 1, - .minimum_version_id =3D 1, + .version_id =3D 2, + .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINT32(control, SysTickState), - VMSTATE_UINT32(reload, SysTickState), VMSTATE_INT64(tick, SysTickState), - VMSTATE_TIMER_PTR(timer, SysTickState), + VMSTATE_PTIMER(ptimer, SysTickState), VMSTATE_END_OF_LIST() } }; --=20 2.20.1